Toshiba Cost Model for 3D NAND

Toshiba Cost Model for 3D NAND
by Fred Chen on 10-11-2020 at 8:00 am

Toshiba Cost Model for 3D NAND

Toshiba (now known as Kioxia) was the first company to propose a 3D stacked version of NAND Flash memory called BICS [1]. BICS (BICost Scalable) Flash used explicit process cost reduction based on depositing and etching multiple layers at once, avoiding multiple lithography steps. This strategy replaced the usual approach… Read More


Smartphone Processor Trends and​ Process Differences down through 7nm

Smartphone Processor Trends and​ Process Differences down through 7nm
by Fred Chen on 08-30-2020 at 6:00 am

Transistor density process for Huawei and Apple

This comparison of smartphone processors from different companies and fab processes was originally going to be a post, but with the growing information content, I had to put it into an article. Here, due to information availability, Apple, Huawei, and Samsung Exynos processors will get the most coverage, but a few Qualcomm Snapdragon

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Fully Self-Aligned 6-Track and 7-Track Cell Process Integration

Fully Self-Aligned 6-Track and 7-Track Cell Process Integration
by Fred Chen on 08-23-2020 at 6:00 am

Fully Self Aligned 6 Track and 7 Track Cell Process Integration

For the 10nm – 5nm nodes, the leading-edge foundries are designing cells which utilize 6 or 7 metal tracks, entailing a wide metal line for every 4 or 5 minimum width lines, respectively (Figure 1).

Figure 1. Left: a 7-track cell. Right: a 6-track cell.

This is a fundamental vulnerability for lithography, as defocus can change… Read More


Application-Specific Lithography: 20nm Flash, 3D XPoint, 3D NAND Bit Lines

Application-Specific Lithography: 20nm Flash, 3D XPoint, 3D NAND Bit Lines
by Fred Chen on 08-10-2020 at 6:00 am

Application Specific Lithography SemiWiki

Nonvolatile memory capacity reached 64 Gb levels when NAND Flash half-pitch reached 20 nm [1]. Having reached 14 nm [2], NAND Flash half-pitch is no longer being reduced, now that it has entered the 3D era. However, recently, 3D XPoint has found applications within the Optane platform [3]. The lithography for patterning 20 nm half-pitch… Read More


EUV faces Scylla and Charybdis

EUV faces Scylla and Charybdis
by Fred Chen on 08-03-2020 at 6:00 am

EUV faces Scylla and Charybdis

It is now time for the EUV community to realize they are caught between the proverbial Scylla and Charybdis. In Greek mythology, the two monsters terrorized ships that were unlucky enough to pass between them. By avoiding one, you approached the other.

S for Scylla, or Stochastics

Scylla was a former beautiful nymph turned into

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Application-Specific Lithography: a 28 nm Pitch DRAM Active Area

Application-Specific Lithography: a 28 nm Pitch DRAM Active Area
by Fred Chen on 07-19-2020 at 2:00 pm

Application Specific Lithography 28 nm Pitch DRAM Active Area

In the recent DRAM jargon, “1X”, “1Y”, “1Z”, etc. have been used to express all the sub-20 nm process generations. It is almost possible now to match them to real numbers which are roughly the half-pitch of the DRAM active area, such as 1X=18, 1Y ~ 17, etc. At this rate, 14 nm is somewhere around

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Application-Specific Lithography: The 5nm 6-Track Cell

Application-Specific Lithography: The 5nm 6-Track Cell
by Fred Chen on 07-05-2020 at 10:00 am

Application Specific Lithography The 5nm 6 Track Cell

The 5nm foundry (e.g., TSMC) node may see the introduction of 6-track cells (two double-width rails plus four minimum-width dense lines) with a minimum metal pitch in the neighborhood of 30 nm. IMEC had studied a representative case as its ‘7nm’ case [1]. TSMC had some published 5nm test structures which looked like… Read More


The Stochastic Impact of Defocus in EUV Lithography

The Stochastic Impact of Defocus in EUV Lithography
by Fred Chen on 06-28-2020 at 6:00 am

The Stochastic Impact of Defocus in EUV Lithography

The stochastic nature of imaging has received a great deal of attention in the area of EUV lithography. The density of EUV photons reaching the wafer is low enough [1] that the natural variation in the number of photons arriving at a given location can give rise to a relatively large standard deviation.

In recent studies [2,3], it … Read More


Can Threshold Switches Replace Transistors in the Memory Cell?

Can Threshold Switches Replace Transistors in the Memory Cell?
by Fred Chen on 06-08-2020 at 6:00 am

Threshold switch I V

The overwhelming majority of transistors produced in the world are used in memory cells, either as the memory itself (Flash, SRAM), or as the access device (DRAM). Yet, it is not necessary to have a transistor in every memory cell. In 2015, 3D XPoint, the first major product based on transistor-less memory cells, was announced [1].

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Feature-Selective Etching in SAQP for Sub-20 nm Patterning

Feature-Selective Etching in SAQP for Sub-20 nm Patterning
by Fred Chen on 06-02-2020 at 10:00 am

Feature Selective Etching in SAQP for Sub 20 nm Patterning

Self-aligned quadruple patterning (SAQP) is the most widely available technology used for patterning feature pitches less than 38 nm, with a projected capability to reach 19 nm pitch. It is actually an integration of multiple process steps, already being used to pattern the fins of FinFETs [1] and 1X DRAM [2]. These steps, shown… Read More