AMS design flows can follow a traditional path or consider trying something new. The traditional path goes along the following steps:
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AMS Design, Optimization and Porting
Author: Daniel Payne
Tanner EDA Newsletter – Fall 2011
From the President: Another Great YearThanks to innovative, cost-effective technology and excellence in customer support, we’ve just ended fiscal year 2011 (on May 31st) with solid growth. Revenue was up 8%, we added 139 new customers, and we’re continuing to reach out to technology partners for MEMS and for the analog and mixed-signal… Read More
Hardware Configuration Management approach awarded a Patent
Hardware designers use complex EDA tool flows that have collections of underlying binary and text files. Keeping track of the versions of your IC design can be a real issue when your projects use teams of engineers. ClioSoft has been offering HCM (Hardware Configuration Management) tools that work in the most popular flows of: … Read More
Another Up Year in a Down Economy for Tanner EDA
Almost every week I read about a slowing world economy, yet in EDA we have some bright spots to talk about, like Tanner EDA finishing its 24th year with an 8% increase in revenue. More details are in the press release from today.
I spoke with Greg Lebsack, President of Tanner EDA on Monday to ask about how they are growing. Greg has been… Read More
Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics
Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented… Read More
Transistor Level IC Design?
If you are doing transistor-level IC design then you’ve probably come up against questions like:
- What Changed in this schematic sheet?
- How did my IC layout change since last week?
In the old days we would hold up the old and new versions of the schematics or IC layout and try to eye-ball what had changed. Now we have an automated… Read More
Third Generation DFM Flow: GLOBALFOUNDRIES and Mentor Graphics
Introduction
Mentor Graphics and GLOBALFOUNDRIES have been working together for several generations since the 65nm node on making IC designs yield higher. Michael Buehler-Garcia, director of Calibre Design SolutionsMarketing at Mentor Graphics spoke with me by phone today to explain how they are working with GLOBALFOUNDRIES… Read More
Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
Solido – Variation Analysis and Design Software for Custom ICs
Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More
How Tektronix uses Hardware Configuration Management tools in an IC flow
Last Monday I sat down with Grego Sanguinetti in Beaverton, Oregon at the campus of Tektronix to hear about how they design their ICs using EDA tools from multiple vendors.… Read More
Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI