Another Up Year in a Down Economy for Tanner EDA

Another Up Year in a Down Economy for Tanner EDA
by Daniel Payne on 09-13-2011 at 11:00 am

Almost every week I read about a slowing world economy, yet in EDA we have some bright spots to talk about, like Tanner EDA finishing its 24th year with an 8% increase in revenue. More details are in the press release from today.

I spoke with Greg Lebsack, President of Tanner EDA on Monday to ask about how they are growing. Greg has been… Read More


Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics

Manufacturing Analysis and Scoring (MAS): GLOBALFOUNDRIES and Mentor Graphics
by Daniel Payne on 09-05-2011 at 3:37 pm

Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented… Read More


Transistor Level IC Design?

Transistor Level IC Design?
by Daniel Payne on 08-26-2011 at 1:23 pm

If you are doing transistor-level IC design then you’ve probably come up against questions like:

  • What Changed in this schematic sheet?
  • How did my IC layout change since last week?

In the old days we would hold up the old and new versions of the schematics or IC layout and try to eye-ball what had changed. Now we have an automated… Read More


Third Generation DFM Flow: GLOBALFOUNDRIES and Mentor Graphics

Third Generation DFM Flow: GLOBALFOUNDRIES and Mentor Graphics
by Daniel Payne on 08-26-2011 at 11:17 am

calibre yield analyzer

Introduction
Mentor Graphics and GLOBALFOUNDRIES have been working together for several generations since the 65nm node on making IC designs yield higher. Michael Buehler-Garcia, director of Calibre Design SolutionsMarketing at Mentor Graphics spoke with me by phone today to explain how they are working with GLOBALFOUNDRIESRead More


Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM

Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM
by Daniel Payne on 08-18-2011 at 10:30 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


Solido – Variation Analysis and Design Software for Custom ICs

Solido – Variation Analysis and Design Software for Custom ICs
by Daniel Payne on 08-15-2011 at 7:11 pm

Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More


Best EDA company for work life balance?

Best EDA company for work life balance?
by Daniel Payne on 08-10-2011 at 1:25 pm

What was the first EDA company name that came to your mind after reading that title?

At Forbes magazine they rated both Mentor Graphics and Synopsys in the top 25 best companies for work life balance.

That’s quite an honor for both Mentor and Synopsys so I can say that EDA dominated the list this year.

Here are some of the factors… Read More


August 11th – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC

August 11th – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC
by Daniel Payne on 08-06-2011 at 9:29 pm

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


Smart Fill Replaces Dummy Fill Approach in a DFM Flow

Smart Fill Replaces Dummy Fill Approach in a DFM Flow
by Daniel Payne on 07-30-2011 at 7:11 pm

I met with Jeff Wilson, Product Marketing Manager at Mentor in the Calibre product group to learn more about Smart Fill versus Dummy Fill for DFM flows. Jeff works in the Wilsonville, Oregon office and we first meet at Silicon Compilers back in the 1990’s.

Dummy Fill

This diagram shows an IC layout layer on the left as originallyRead More