Using "Apps" to Take Formal Analysis Mainstream

Using "Apps" to Take Formal Analysis Mainstream
by Daniel Payne on 02-02-2012 at 12:47 pm

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On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”

My response was, “Yes, however only the parts that we have been able to simulate.”

Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More


Design & Verification of Platform-Based, Multi-Core SoCs

Design & Verification of Platform-Based, Multi-Core SoCs
by Daniel Payne on 02-02-2012 at 11:16 am

Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More


How Is Your IC Design Flow Glued Together?

How Is Your IC Design Flow Glued Together?
by Daniel Payne on 01-25-2012 at 2:36 pm

Most IC designers I talk to really enjoy the creative process of developing a new SoC design, debugging it, then watching it go into production. They don’t really like spending time learning how to make their EDA tools work together in an optimal IC design flow where they may have a dozen tools each with dozens of options. Fortunately… Read More


Manage Your Cadence Virtuoso Libraries, PDKs & Design IPs (Webinar)

Manage Your Cadence Virtuoso Libraries, PDKs & Design IPs (Webinar)
by Daniel Payne on 01-24-2012 at 5:01 pm

Users of Cadence Virtuoso tools for IC layout and schematics can make their design flow easier by using Design Data Management tools from ClioSoft. Keeping track of versions across schematics, layout, IP libraries and PDKs can be daunting. Come and learn more about this at a Webinar hosted by ClioSoft next Tuesday.… Read More


Analog Panel Discussion at DesignCon

Analog Panel Discussion at DesignCon
by Daniel Payne on 01-20-2012 at 7:59 pm

DesignCon is coming up and the panel discussions look very interesting this year. The one panel session that I recommend most is called, “Analog and Mixed-Signal Design and Verification” which is moderated by Brian Bailey, one of my former Mentor Graphics buddies and fellow Oregonian.… Read More


EDA Tool Flow at MoSys Plus Design Data Management

EDA Tool Flow at MoSys Plus Design Data Management
by Daniel Payne on 01-20-2012 at 4:50 pm

I’ve read about MoSys over the years and had the chance this week to interview Nani Subraminian, Engineering Manager about the types of EDA tools that they use and how design data management has been deployed to keep the design process organized. My background includes both DRAM and SRAM design, so I’ve been curious… Read More


What is a Hierarchical SPICE Circuit Simulator?

What is a Hierarchical SPICE Circuit Simulator?
by Daniel Payne on 01-19-2012 at 2:56 pm

Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:

  • Mask Data
  • IC Layout
  • Schematic Netlists
  • Gate level netlists
  • RTL netlists

But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More


Low-power IC design in Switzerland

Low-power IC design in Switzerland
by Daniel Payne on 01-18-2012 at 7:17 pm

My wife and I have traveled to Switzerland on vacation and marveled at the natural beauty of the mountains, efficient train system, tasty chocolate, and wonderful foods. I only wished that our American dollar bought more in Swiss currency than it did. Recently I discovered a high-tech IC design company called Microdul that designs… Read More


Kindle Touch – My Experience

Kindle Touch – My Experience
by Daniel Payne on 01-09-2012 at 11:08 am

Mostly I blog about EDA software however the end objective of IC design is to produce an electronic system like the Kindle Touch, a popular e-book reader from Amazon introduced in late 2011.

Tear Down
This particular model has the following components (Source: Tech Republic):

Read More

What Dolpin Technology Uses for SPICE Circuit Simulation of IP

What Dolpin Technology Uses for SPICE Circuit Simulation of IP
by Daniel Payne on 01-06-2012 at 12:32 pm

Mo Tamjidi founded two Semiconductor IP companies Virage Logic and Dolphin Technology. After reading a press release about how Dolphin Technology is using FineSIM SPICE from Magma I decided to contact him and learn more about why they are now using that circuit simulator in the design of their memory, standard cells, and IO cells.… Read More