Author: Daniel Payne

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IC Custom IP Blocks – EM and IR Drop Effects

IC Custom IP Blocks – EM and IR Drop Effects
by Daniel Payne on 03-06-2012 at 5:33 pm
Categories: EDA, Synopsys

Designing custom IP blocks is a challenge at the transistor-level and I wanted to learn what the recommended methodology and EDA tool flow was at Synopsys. They have a webinar that you can register for and it takes 30 minutes to learn what they have to say, or you can read a White Paper. If you cannot spare that much time, then my summary… Read More

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HSPICE Users Talking about Their Circuit Simulation Experience

HSPICE Users Talking about Their Circuit Simulation Experience
by Daniel Payne on 02-28-2012 at 4:46 pm
Categories: EDA, Synopsys

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HSPICE users gathered in January 2012 at the HSPICE SIG(Special Interest Group) to talk about their experiences using this circuit simulator for a variety of IC and signal integrity issues. I wasn’t able to attend in person however I did watch the video and wanted to summarize what I heard:… Read More

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Seminar on IC Yield Optimization at DATE on March 14th

Seminar on IC Yield Optimization at DATE on March 14th
by Daniel Payne on 02-22-2012 at 3:59 pm
Categories: EDA, Siemens EDA

My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced… Read More

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Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS

Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS
by Daniel Payne on 02-15-2012 at 10:27 am
Categories: Cadence, EDA

Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.
… Read More

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Why X-Fab uses 3D Resistance Extraction and Analysis

Why X-Fab uses 3D Resistance Extraction and Analysis
by Daniel Payne on 02-09-2012 at 11:18 am
Categories: Uncategorized
10 Comments

At DAC in 2011 I visited an EDA company called Silicon Frontline Technology because they offered some 3D field solver tools used to create the highest accuracy netlists that can then be simulated with a SPICE circuit simulator to predict timing, power and IR drop. A recent press release with X-FAB and Silicon Frontline looked interesting… Read More

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Using "Apps" to Take Formal Analysis Mainstream

Using "Apps" to Take Formal Analysis Mainstream
by Daniel Payne on 02-02-2012 at 12:47 pm
Categories: EDA, Events

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On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”

My response was, “Yes, however only the parts that we have been able to simulate.”

Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More