In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More
Author: Daniel Payne
Managing Differences with Schematic-Based IC Design
At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.
The Challenge
Hand-crafted … Read More
Robustness, Reliability and Yield at DAC
On Wednesday at DAC I met with Bob Slee, distributor and Michael Siu, AE for MunEDA to get an update on what’s new. MunEDA has EDA software for:
- Schematic porting
- Nominal circuit analysis
- Nominal circuit optimization
- Statistical circuit analysis
- Statistical circuit optimization
- IP porting
- Circuit model generation
Methodics update at DAC
Fergus Slorach, CTO and Founder of Methodics met with me at DAC on Wednesday afternoon to provide an update on software configuration management for hardware designers.… Read More
Photo and Video Overview of DAC 2012
Sunday Night – you have to network at the EDAC kick-off party.… Read More
Analog FastSPICE update at DAC
Paul Estrada, COO of Berkeley DA met with me on the final day of DAC to provide an update. BDA coined the phrase Analog FastSPICE and have continued to dominate that market segment in the world of SPICE circuit simulators.… Read More
AMS Simulation Update from Mentor Graphics at DAC
I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.… Read More
FinFET Standard Cells at DAC
Rajiv Bhateja, Dhrumil Gandhi and Neal Carney met with me at DAC on Wednesday to give an update on what’s new in 2012 for Tela Innovations, a provider of lithography optimized IP and tools. This team has a rich history in EDA and IP from companies like: ARM, Artisan, Mentor Graphics and Silicon Compilers.… Read More
Finding RTL Bugs Live Using Formal Techniques
Most of what you see at DAC is canned PowerPoint presentations, however on Tuesday afternoon I spotted a company called Oski Technology that was doing something almost unheard of – they had an engineer debugging a digital design from Nvidia using formal tools live. I later found out the engineer found 4 bugs in just three days… Read More
Electromagnetic Simulation Update from Nimbic
Dr. Raul Camposano, CEO of Nimbic talked with me on Wednesday at DAC to provide an update on what’s new with their electromagnetic simulation tools.… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot