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SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis and represents a class of EDA software used by circuit designers at the transistor-level to predict the timing, frequency, voltage, current or power of an IC or interconnect before fabrication.
In 1971 there was a tool called CANCER (Computer Analysis… Read More
At SemiWiki we’ve blogged before about 3D field solvers and the different approaches that trade off accuracy, speed and capacity:… Read More
I’m watching the latest Mars rover landing tonight called “Curiosity” and wondering about all of the electronic systems designed to control the project and hopefully send back some stunning new images along with new data on the micro-biology and chemistry of the red planet. JPL gets all the glory for designing… Read More
Another week in EDA and yet another acquisition by Synopsys as they buy SpringSoft this time for $406 million in cash. Paul McLellan wrote a good blog on this merger too.
Last week I blogged about the product overlap and integration challenges that Synopsys faces with the acquisition of Ciranova.
Let’s take a look at the IC … Read More
Ken Brockof Synopsys presented on how to optimize your SoC design for low power at 40nm, 28nm and 20nm nodes in a webinar today. Ken and I both worked together at Silicon Compilers back in the late 1980’s, the best EDA/IP company that I’ve had the pleasure to join.
The webinar made a brief mention of 14nm and FinFETS but … Read More
In April I blogged about using the iPad for schematic capture and SPICE circuit simulation. My conclusion was that the technology was interesting but not quite ready for commercial use. Today I tried out the web-based version using my Google Chrome browser instead of the iPad. Install the Chrome app here or visit www.ischematic.com… Read More
Consolidation continues in the EDA industry with Synopsys announcing today that they acquired Ciranova, a provider of software to automate custom IC layout. Remember that Synopsys invested in Ciranova back in March 2008 and September 2010 (along with Intel Capital, Mentor Graphics and Alloy Ventures), so this deal has some … Read More
I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More
At Intel we used to hand-craft every single transistor size to eek out the ultimate in IC performance for DRAM and graphic chips. Today, there are many libraries that you can choose from for an SoC design in order to reach your power, speed and area trade-offs. I’m going to attend a Synopsys webinar on August 2nd to learn more … Read More
The press has been buzzing about 3D everything for the past few years, so when it comes to IC design it’s a fair question to ask how would you actually extract 3D IC structures for use by analysis tools like a circuit simulator. I read a white paper by Christen Decoin and Vassilis Kourkoulos of Mentor Graphics this week and became… Read More
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Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools