I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.… Read More
Author: Daniel Payne
FinFET Standard Cells at DAC
Rajiv Bhateja, Dhrumil Gandhi and Neal Carney met with me at DAC on Wednesday to give an update on what’s new in 2012 for Tela Innovations, a provider of lithography optimized IP and tools. This team has a rich history in EDA and IP from companies like: ARM, Artisan, Mentor Graphics and Silicon Compilers.… Read More
Finding RTL Bugs Live Using Formal Techniques
Most of what you see at DAC is canned PowerPoint presentations, however on Tuesday afternoon I spotted a company called Oski Technology that was doing something almost unheard of – they had an engineer debugging a digital design from Nvidia using formal tools live. I later found out the engineer found 4 bugs in just three days… Read More
Electromagnetic Simulation Update from Nimbic
Dr. Raul Camposano, CEO of Nimbic talked with me on Wednesday at DAC to provide an update on what’s new with their electromagnetic simulation tools.… Read More
DesignSync update from Dassault Systems at DAC
At DAC on Wednesday Rick Stanton of Dassault Systems gave me an update on what’s new with DesignSync, a design data management tool offered since 1998. Rick and I both worked at Viewlogic in the 90’s along with Dennis Harmon who then founded Synchronicity, later acquired by Dassault Systems.… Read More
Laker IC Layout Update at DAC
Taiwan’s most famous EDA company is SpringSoft so on Wednesday at DAC I met wtih Dave Reed, Director of Marketing to get an update on what’s new with their IC layout tools.… Read More
Designing a Wafer-Scale Image Sensor for use in X-Rays
At Intel we mused about designing wafer-scale integration (WSI) back in the 70’s however I just learned about how Dr.Renato Turchetta at the Science and Technology Facilities Council (STFC) designed a wafer-scale imaging sensor chip for X-Ray applications. I was also able to interview Dr. Turchetta to learn more about… Read More
EDA Tools to Optimize Memory Design
I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they’ve expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more… Read More
IC Cell Library Characterization at DAC
Edmond Macaluso, President of Z-Circuit Automation met with me at DAC on Tuesday afternoon to provide an overview of how their EDA tools characterize cell libraries. … Read More
Double Patterning Technology at DAC
David Abercrombie from Mentor Graphics met with me on Tuesday at DAC to provide an update on DPT – Double Patterning Technology, something new required for several layers starting at the 20nm node in order to get any IC yield. DPT is also part of Multiple-Patterning.… Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing