Frederick Chen • 1st Looking at tech differentlyLooking at tech differently3h •
At FMS 2025, TechInsights projected the 4F^2 DRAM cell architecture to come in at 0a node, overlapping 1d in 2029: https://lnkd.in/g6hhPYTV.
The most recent exciting development: at ISSCC 2026, Samsung Electronics demonstrated a 16Gb DRAM with a 4F^2 vertical channel transistor (VCT) cell architecture. A key achievement was the separation of the circuitry outside the array (core/periphery) from the array on different wafers and the use of hybrid copper bonding to put them together. This allows design rules to be loosened, i.e., features can be spread out more within the same chip area. The paper specifically mentioned upsizing the core circuits. D1a minimum pitches (~27-28 nm) on a 4F^2 process would give the same cell area (~0.0007-0.0008 um2) as D0a on a 6F^2 process.
Reference: https://lnkd.in/gZf7PvRr
SK hynix had apparently done the same thing at VLSI 2025, but apparently not at Gb-scale: https://lnkd.in/g59PkxXa.
Even earlier, in 2023, Micron Technology had unveiled a 32 Gb 4F^2 NVDRAM (Non-Volatile DRAM), which is not only 4F^2 with vertical cell transistors, but also 3D, having two stacked layers on one chip. No wafer bonding was necessary, but the capacitor is in fact ferroelectric, so polarization rather than conventional charge sensing was used. See: https://lnkd.in/g636f-Y4
Note: the wafer bonding requirement can be eschewed by using polysilicon (as Micron had done) or IGZO (or other oxide semiconductor) channels in the VCT. Then, it would simply be peripheral CMOS under array.