Challenges of 20nm IC Design

Challenges of 20nm IC Design
by Daniel Payne on 04-29-2013 at 11:38 am

Designing at the 20nm node is harder than at 28nm, mostly because of the lithography and process variability challenges that in turn require changes to EDA tools and mask making. The attraction of 20nm design is realizing SoCs with 20 billion transistors. Saleem Haider from Synopsys spoke with me last week to review how Synopsys… Read More


10 to 100X faster HDL Simulation Speeds

10 to 100X faster HDL Simulation Speeds
by Daniel Payne on 04-24-2013 at 10:44 am

Speed, capacity, accuracy – these are the three major EDA tool metrics that we pay attention to and that enable us to design and verify an SoC. Talk to any design or verification engineer and ask if they are satisfied with the time that it takes to simulate their latest design, or to verify that it meets spec and is functionally… Read More


Variation-aware IC Design

Variation-aware IC Design
by Daniel Payne on 04-15-2013 at 4:18 pm

We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, … Read More


Two New TSMC-Cadence Webinars for Advanced Node Design

Two New TSMC-Cadence Webinars for Advanced Node Design
by Daniel Payne on 04-15-2013 at 3:43 pm

Foundries and EDA vendors are cooperating at increasing levels of technical intimacy as we head to the 20nm and lower nodes. Cadence has a strong position in the EDA tools used for IC design and layout of custom and AMS (Analog Mixed-Signal) designs. They have created a series of webinars to highlight the design challenges and new… Read More


SoC Power Integrity Challenges

SoC Power Integrity Challenges
by Daniel Payne on 04-08-2013 at 4:46 pm

At DAC in 2012 I visited a few dozen EDA companies and blogged 32 articles, however I didn’t get to see what Apache Design (now a subsidiary of ANSYS) had to say. I did have 20 minutes today to watch their latest video on SoC Power Integrity Challenges and decided to share what I learned. If you want to watch the video at Tech Online,… Read More


RTL Restructuring

RTL Restructuring
by Daniel Payne on 04-04-2013 at 2:34 pm

Hierarchical IC design has been around since the dawn of electronics, and every SoC design today will use hierarchy for both the physical and logical descriptions. During the physical implementation of an SoC you will likely run into EDA tool limits that require a re-structure of the hierarchy. This re-partitioning will cause… Read More


Circuit Analysis & Debugging

Circuit Analysis & Debugging
by Daniel Payne on 03-30-2013 at 3:18 pm

Spice Debugger

In EDA we often talk about how fast a SPICE circuit simulator is, or about capacity and accuracy compared to silicon measurements. Yes, speed, capacity and accuracy are important, however when talking to actual transistor-level circuit designers you discover something quite different, most of their time is spent doing debugging,… Read More


An Analog IC Router

An Analog IC Router
by Daniel Payne on 03-29-2013 at 8:10 pm

Earlier this week I wrote about a Goliath in EDA, Synopsys, and their new analog router, today it’s the David in EDA, Pulsic and their Unity Analog Router. I spoke with several people from Pulsic by phone:

  • Christopher Jost – San Jose
  • Dave Noble – San Jose
  • Fumiaki Sato – Tokyo, Japan
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