EDA and Semi IP Stocks in 2013: MENT, ARMH, CDN, SNPS, ANSS, CEVA, IMG.L

EDA and Semi IP Stocks in 2013: MENT, ARMH, CDN, SNPS, ANSS, CEVA, IMG.L
by Daniel Payne on 12-20-2013 at 12:39 am

2013 was an up year for the stock markets as both the DJIA and the tech-heavy NASDAQ showed significant growth, so how did EDA and Semi IP companies do in the past 12 months? A quick stock plot from Yahoo Finance shows us that only two of the seven companies beat the NASDAQ: ARMH, MENT.… Read More


The Most Popular Blog Posts at Cadence in 2013

The Most Popular Blog Posts at Cadence in 2013
by Daniel Payne on 12-19-2013 at 11:42 am

I spend about an hour a day reading blogs from EDA companies, foundries, independent bloggers and of course, SemiWiki. Richard Goering at Cadence assembled a top 10 list of the most popular blogs posted on their site in 2013, revealing that engineers were most interested in: FinFETs, 20nm and smaller nodes, memory technology and… Read More


Verification of Multirate Systems with Multiple Digital Blocks

Verification of Multirate Systems with Multiple Digital Blocks
by Daniel Payne on 12-13-2013 at 8:27 pm

Our popular smart phones have a whole slew of RF-based radios in them for: Bluetooth, WiFi, LTE, GSM, NFC. Using just a single clock frequency for a DSP function or SoC is a thing of the past, so the design of multirate systems is here to stay. So now the challenge on the design and verification side is to use a methodology that supports:… Read More


Impact Conference: Focus on the IP Ecosystem

Impact Conference: Focus on the IP Ecosystem
by Daniel Payne on 12-11-2013 at 7:07 pm

Jim Feldhan, President of Semico Research presented earlier this month at the Impact Conference on the topic: Focus on the IP Ecosystem. I’ve reviewed his 19 page presentation, and summarize it with:

  • End markets like smart phones and tablets are dominant
  • Growth drivers include the Internet of Things (IoT)
  • World semi forecast
Read More

Designing a DDR3 System to Meet Timing

Designing a DDR3 System to Meet Timing
by Daniel Payne on 12-11-2013 at 12:00 pm

My very first thought when hearing about HSPICE is using it for IC simulation at the transistor-level, however it can also be used to simulate a package or PCB interconnect very accurately, like in the PCB layout of a DDR3 system where timing is critical. I attended a webinar this morning that was jointly presented by Zuken and Synopsys… Read More


Capturing Analog Design Intent with Verification

Capturing Analog Design Intent with Verification
by Daniel Payne on 12-08-2013 at 10:05 am

Analog IC designers are gradually adopting what digital IC designers have been doing for years, metric driven verification. When you talk with analog designers about their methodology and approach, you hear terms like artisan being used which implies mostly a manually-oriented methodology. Thanks to automation from EDA companies,… Read More


Virtual Prototypes Made Easier for SoC Design

Virtual Prototypes Made Easier for SoC Design
by Daniel Payne on 12-06-2013 at 6:24 pm

Using a virtual prototype for your SoC design is accepted, conventional wisdom today because it can save development time by eliminating design iterations and avoid costly bugs that will cause an expensive product recall. In order to simulate your virtual prototype you need models, so a major question has always been, “Where… Read More


Simplified Assertion Adoption with SystemVerilog 2012

Simplified Assertion Adoption with SystemVerilog 2012
by Daniel Payne on 12-02-2013 at 7:01 pm

SystemVerilog as an assertion language improved and simplified with the 2012 version compared to the 2005 version. I recently viewed a webinar on SystemVerilog 2012 by consultant Srinivasan Venkataramanan, who works at CVC Pvt. Ltd. There’s been a steep learning-curve for assertions in the past, and hopefully you’ll… Read More