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When I started my IC design career back in 1978 all IC routing was done manually, today however we have many automated approaches to IC routing that save time and do a more thorough job than manual routing. To get an update on space-based routers for IC design I connected with Yuval Shay at Cadence today. The basic idea behind a spaced-based… Read More
In January 2001 we had a new American president, George W. Bush, I was working at Mentor Graphics, and Apple introduced an MP3 player called the iPod with a hard drive capable of holding 1,000 songs. In the previous decades we enjoyed portable music from tape-based, CD, or mini-CD devices like the Sony Walkman. The first several generations… Read More
I’ve been using SPICE circuit simulators since 1978, both internally and commercially developed, and a lot has changed since the early days where netlists were simulated in batch mode on time-share mainframes. We used to wait overnight for our simulations to complete, and in the morning had to pickup our output results … Read More
SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it’s also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all… Read More
SoC hardware designers could learn a thing or two from the world of software development, especially when it comes to the topic of managing complexity. Does that mean that hardware designers should literally use a software development environment, and force fit hardware design into file and class-based software methodologies?… Read More
DesignCon brings together engineers from around the world that are interested in IC design, package design and board design, plus the signal integrity issues of creating high-speed systems. In just two weeks there’s a Special Interest Group(SIG) just for users of HSPICE in their tool flow, and it meets for three hours during… Read More
IC designers use EDA tools to implement their logical and physical design, and these tools require foundry-specific information for:
I’ve been blogging about EDA and Semiconductor companies using social media to create new ways to talk and listen to engineers, so today I looked at Aldec and how they are using social media. Aldec offers EDA products for: FPGA Simulation, functional verification, emulation, and MIL/Aero verification. Their Home page … Read More
I’ve been quite impressed that modern ICs use a lithography process with 193nm light sources to resolve final feature sizes at 20nm and smaller dimensions. We’ve been blogging about Double Patterning Technology (DPT) some 45 times in the past few years that enable 20nm fabrication, so one big question for me is, “How… Read More
In the 1970’s we designed ICs first and when silicon came back then we measured the power and junction temperature. At that time there were no EDA simulation tools or models for full-chip power and temperature analysis. Fast forward to 2013 and we find that temperature and power are still demanding requirements for MPSoC … Read More
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[rootClass:protected] => XF\Entity\Node
[_useReplaceInto:protected] =>
[_newValues:protected] => Array
(
)
[_values:protected] => Array
(
[node_id] => 2
[title] => SemiWiki Main Forum ( Ask the Experts! )
[description] => Post your questions to the experts here!
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[node_type_id] => Forum
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[display_order] => 1
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[lft] => 2
[rgt] => 3
[depth] => 1
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[navigation_id] =>
[effective_navigation_id] =>
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[_relations:protected] => Array
(
)
[_previousValues:protected] => Array
(
)
[_options:protected] => Array
(
)
[_deleted:protected] =>
[_readOnly:protected] =>
[_writePending:protected] =>
[_writeRunning:protected] =>
[_errors:protected] => Array
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)
[_whenSaveable:protected] => Array
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[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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)
[_previousValues:protected] => Array
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[_options:protected] => Array
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[_whenSaveable:protected] => Array
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[_cascadeSave:protected] => Array
(
)
[_behaviors:protected] =>
)
)
[_previousValues:protected] => Array
(
)
[_options:protected] => Array
(
)
[_deleted:protected] =>
[_readOnly:protected] =>
[_writePending:protected] =>
[_writeRunning:protected] =>
[_errors:protected] => Array
(
)
[_whenSaveable:protected] => Array
(
)
[_cascadeSave:protected] => Array
(
)
[_behaviors:protected] =>
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[populated:protected] => 1
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Facing the Quantum Nature of EUV Lithography