A Picture is worth a 1,000 words

A Picture is worth a 1,000 words
by Daniel Payne on 12-28-2017 at 7:00 am

Semiconductor IP re-use is a huge part of the productivity gains in SoC designs, so instead of starting from a clean slate most chip engineers are re-using cells, blocks, modules and even sub-systems from previous designs in order to meet their schedule and stay competitive in the market place. But what happens when you intend to… Read More


Embedded In-chip Monitoring, Webinar Recap

Embedded In-chip Monitoring, Webinar Recap
by Daniel Payne on 12-21-2017 at 12:00 pm

Six years ago I first interviewed Stephen Crosher, CEO and Co-founder of Moortecas they were in startup mode with some new semiconductor IP for temperature sensing, and earlier this month I attended their webinar all about embedded in-chip monitoring to get caught up with their technology and growing success. Ramsay Allen is … Read More


35 Semiconductor IP Companies Hold 2nd Annual Conference

35 Semiconductor IP Companies Hold 2nd Annual Conference
by Daniel Payne on 12-04-2017 at 12:00 pm

Our smart phone driven semiconductor economy consumes a lot of IP blocks to enable quick product development cycles, often annually updating with new models to choose from. So where do you find all of the best semiconductor IP, verification IP and embedded software? Well, one place is at the 2nd annual REUSE conference, scheduled… Read More


Making Your Next Chip Self-Aware

Making Your Next Chip Self-Aware
by Daniel Payne on 12-01-2017 at 12:00 pm

One holy grail of AI software developers is to create a system that is self-aware, or sentient. A less lofty goal than sentient AI is for chip designers to know how each specific chip responds to Process variations, Voltage levels and Temperature changes. If a design engineer knew exactly which process corner that each chip was fabricated… Read More


Hierarchy Applied to Semiconductor IP Reuse

Hierarchy Applied to Semiconductor IP Reuse
by Daniel Payne on 11-30-2017 at 12:00 pm

When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More


Protecting electronics around the world, SEMI insights

Protecting electronics around the world, SEMI insights
by Daniel Payne on 11-27-2017 at 12:00 pm

SEMI is a worldwide organization with local chapters like the one here in Oregon, where I attended a recent half-day presentation by several industry experts on the topic – Globalization, How it shapes the Semiconductor industry:

  • Michael Chen, Director, Mentor – A Siemens Business
  • John Brewer, CEO, Amorphyx
  • Ed
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A Brief History of PSS at Breker

A Brief History of PSS at Breker
by Daniel Payne on 11-14-2017 at 12:00 pm

Verification engineers are hearing a lot about the Portable Stimulus Standard (PSS), and for good reason because it could potentially save them time and effort in doing their jobs much better. In order to get the big picture on what PSS is all about I contacted Adnan Hamid, founder and CEO of Breker Verification Systems, because … Read More


12 Year-old Semiconductor IP and Design Services Company Receives New Investment

12 Year-old Semiconductor IP and Design Services Company Receives New Investment
by Daniel Payne on 11-07-2017 at 12:00 pm

I have a transistor-level IC design background so was intrigued to learn more from the CEO of an IP and services company that started out in India 12 years ago. Last week I spoke with Samir Patel, CEO of Sankalp Semiconductorabout the newest $5 million financial investment in his company from Stakeboat Capital Fund. The Stakeboat… Read More


Using a TCAD Tool to simulate Electrochemistry

Using a TCAD Tool to simulate Electrochemistry
by Daniel Payne on 11-02-2017 at 12:00 pm

In college I took courses in physics, calculus, chemistry and electronics on my way to earn a BSEE degree, then did an 8 year stint as a circuit designer, working at the transistor level and interacting with fab and test engineers. My next adventure was working at EDA companies in a variety of roles. As a circuit designer I knew that … Read More


1st Annual International Conference, Semiconductors ISO 26262

1st Annual International Conference, Semiconductors ISO 26262
by Daniel Payne on 10-31-2017 at 12:00 pm

When we talk about the promise of ADAS and autonomous cars then along the way we also hear about this functional safety standard called ISO 26262 which semiconductor companies all pay close attention to. I recently learned about a new conference called Semiconductors ISO 26262, scheduled for December 5-7 in Munich, Germany. The… Read More