Accuracy of In-Chip Monitoring for Thermal Guard-banding

Accuracy of In-Chip Monitoring for Thermal Guard-banding
by Daniel Payne on 01-28-2019 at 12:00 pm

I remember working at Intel and viewing my first SPICE netlist for a DRAM chip, because there was this temperature statement with a number after it, so being a new college graduate I asked lots of questions, like, “What is that temperature value?”

My co-worker answered, “Oh, that’s the estimated junction… Read More


Intel Swaggers at CES

Intel Swaggers at CES
by Daniel Payne on 01-24-2019 at 7:00 am

Intel started out as a DRAM company using planar NMOS technology, then later on added EPROM and Microprocessors to the product mix. Their CPU technology enabled the dynamic growth of the PC industry starting with the IBM PC back in 1981 and continuing all of the way to this day. They long ago dropped out of the DRAM marketplace and began… Read More


Applying Generative Design to Automotive Electrical Systems

Applying Generative Design to Automotive Electrical Systems
by Daniel Payne on 01-15-2019 at 12:00 pm

Scanning headlines of technology news every day I was somewhat familiar with the phrase “Generative Design” and even browsed the Wikipedia page to find this informative flow-chart that shows the practice of generative design.


Generative design is an iterative design process that involves a program that will generateRead More


CES 2019 and Cycling

CES 2019 and Cycling
by Daniel Payne on 01-11-2019 at 7:00 am

It’s January so time for my annual update on all things cycling that are being shown at CES this week. For 2018 my cycling goal was 11,440 miles, but an accident on September 1st cut into my goal, however I did reach 10,887.6 miles according to Strava.

eBikes
This category continues to grow in 2019, with many vendors offering … Read More


SoC Design Partitioning to Save Time and Avoid Mistakes

SoC Design Partitioning to Save Time and Avoid Mistakes
by Daniel Payne on 12-18-2018 at 12:00 pm

I started designing ICs in 1978 and continued through 1986, and each chip used hierarchy and partitioning but our methodology was totally ad-hoc, and documented on paper, so it was time consuming to make revisions to the chip or train someone else on the history or our chip, let alone re-use any portion of our chips again. Those old,… Read More


DVCon is coming in February, now is the time to register early

DVCon is coming in February, now is the time to register early
by Daniel Payne on 12-12-2018 at 7:00 am

As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project… Read More


Using IP in a SoC Compliant with ISO 26262

Using IP in a SoC Compliant with ISO 26262
by Daniel Payne on 11-19-2018 at 12:00 pm

The automotive segment is being well served by semiconductor suppliers of all sizes because of the unit volumes, and the constant push to automate more of the driving decisions to silicon and software can raise lots of questions about safety, reliability and trust. Fortunately the ISO standards body has already put in place a functional… Read More


Make Versus Buy for Semiconductor IP used in PVT Monitoring

Make Versus Buy for Semiconductor IP used in PVT Monitoring
by Daniel Payne on 10-01-2018 at 12:00 pm

As an IC designer I absolutely loved embarking on a new design project, starting with a fresh, blank slate, not having to use any legacy blocks. In the early 1980’s we really hadn’t given much thought to re-using semiconductor IP because each new project typically came with a new process node, so there was no IP even ready… Read More


Beyond DRC and LVS, why Reliability Verification is used by Foundries

Beyond DRC and LVS, why Reliability Verification is used by Foundries
by Daniel Payne on 09-18-2018 at 12:00 pm

Reliability of ICs isn’t a new thing, because back in 1980 I was investigating why a DRAM chip using 6um technology was having yield loss due to electromigration effects. I recall looking through a microscope at a DRAM layout and slowly ramping up the Vdd level then suddenly the shiny aluminum interconnect started to change… Read More


Affordable EDA Tools for IoT Designs, Guess which Vendor

Affordable EDA Tools for IoT Designs, Guess which Vendor
by Daniel Payne on 09-10-2018 at 12:00 pm

I just had to drive my car 7 miles from Tualatin, Oregon to visit with an EDA veteran who has played a lot of diverse roles in his career, including: IC Mask Designer, Layout Manager, Account Manager, Business Development, Director, Foundry Relations Director. His name is John Stabenow, with Mentor, a Siemens Business, and we met… Read More