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If you’ve spent any time at all in the semiconductor industry, you’ve heard the statement that verification consumes two-thirds or more of the total resources on a chip project. The estimates range up to 80%, in which case verification is taking four times the effort of the design process. The exact ratio is subject to debate, but… Read More
As a professional conference attendee I look for the most meaningful way to spend my time and workshops is one of the best. Especially when a customer is involved and there is no bigger EDA customer than Intel, absolutely.
System Level Flows for SoC Architecture Analysis and Design
Speakers:
Swaminathan Ramachandran – … Read More
Are you ready for the premier conference for functional design and verification of electronic systems?
Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP)… Read More
In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More
The semiconductor industry lost another good one last week, my friend, co-worker, and longtime SemiWiki contributor, Randy Smith. Randy published sixty blogs on SemiWiki over the last eight years that have been viewed more than a half million times. That is quite a digital legacy, absolutely.
Like myself, and many other semiconductor… Read More
Howie began his career at Digital Equipment Corporation working on real-time device drivers, but within a few years started working at the other end of the stack with one of the pioneering electronic mail systems. Since then, Howie has worked on developing systems involving electronic mail, workflow processing, configuration… Read More
Now that the dust has settled and I’m out of cronovirus quarantine let’s talk about the Intel and AMD conference calls. Unfortunately, the Intel and AMD marketing teams are still outpacing engineering so it is difficult to write something serious but I will do my best.
Spoiler Alert: Both CEOs disappoint.
First an Intel 10nm update:… Read More
The next generation FPGAs have been announced, and they are BIG! Intel is shipping its Stratix 10 GX 10M FPGA, and Xilinx has announced its VU19P FPGA for general availability in the Fall of next year. The former is expected to support about 80M ASIC gates, and the latter about 50M ASIC gates. And, to bring this mind-boggling gate… Read More
Our friends at Threshold Systems have a new class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last May. As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE. And… Read More
FPGAs, today and throughout the history of semiconductors, play a critical role in design enablement and electronic systems. Which is why we included the history of FPGAs in our book “Fabless: The Transformation of the Semiconductor Industry” and added a new chapter in the 2019 edition on the history of Achronix.
In a recent blog… Read More
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Should Intel be Split in Half?