Dynamic event-based simulation of RTL models has traditionally been the workhorse verification methodology. A team of verification engineers interprets the architectural specification to write testbenches for various elements of the design hierarchy. Test environments at lower levels are typically exercised then … Read More
Author: Daniel Nenni
Security Requirements for IoT Devices
Designing for secure computation and communication has become a crucial requirement across all electronic products. It is necessary to identify potential attack surfaces and integrate design features to thwart attempts to obtain critical data and/or to access key intellectual property. Critical data spans a wide variety… Read More
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
We are delighted to showcase our “Bridging Analog and Digital worlds at high speed with the JESD204 Serial Interface” webinar on April 20th, in case you missed the live webinar back in February 2022.
To meet the increased demand for converter speed and resolution, JEDEC proposed the JESD204 standard describing a new efficient … Read More
Cadence and DesignCon – Workflows and SI/PI Analysis
DesignCon 2022 is back to a live conference, from Tuesday, April 5th through Thursday, April 7th, at the Santa Clara Convention Center.
Introduction
DesignCon is a unique gathering in our industry. Its roots incorporated a focus on complex design and analysis requirements of (long-reach) high-speed interfaces. Technical… Read More
CEO Interview: Kelly Peng of Kura Technologies
This interview is with Kelly Peng, Co-founder, and CEO of Kura Technologies. Kura Gallium, Kura’s first product, was named Best of CES 2022 and received a 2022 CES Innovation Award as well. Kelly is an inventor, engineer and entrepreneur that leads a team of dedicated innovators that are redefining the term “Augmented Reality”.… Read More
Synopsys Announces FlexEDA for the Cloud!
There’s been a lot of discussion and hype regarding use of the cloud for chip design for quite a while, more than ten years I would say. I spoke with Synopsys to better understand their recent Synopsys Cloud announcement to determine if it is different. Briefly, it is different, and here is why:
If you’re trying to design a complex SoC,… Read More
Analog Bits and SEMIFIVE is a Really Big Deal
Given the recent acquisitions the ASIC business is coming full circle as a critical part of the fabless semiconductor ecosystem. The most recent one being the SEMIFIVE acquisition of IP industry stalworth Analog Bits. These two companies came to the industry from opposite directions which make them a perfect match, absolutely.… Read More
WEBINAR: Overcome Aging Issues in Clocks at Sub-10nm Designs
We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected… Read More
Webinar: Simulate Trimming for Circuit Quality of Smart IC Design
Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more.
However, more aggressive time-to-market and higher performance… Read More
Alphawave IP and the Evolution of the ASIC Business
Alphawave IP has agreed to acquire OpenFive, a SiFive business unit (formerly Open-Silicon) for $210m in cash. Having spent many years in the ASIC business which included working with Open-Silicon, Alphawave, and OpenFive here is my perspective on the acquisition:
This acquisition accomplishes two things: First it trims down… Read More






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