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Emulation as a Service Benefits New AI Chip

Emulation as a Service Benefits New AI Chip
by Bernard Murphy on 09-10-2020 at 6:00 am

It’s no secret that innovation in AI chip architectures is on a tear. When you put together the spatial complexity of highly parallelized algorithms with the need to localize memory accesses on-chip to the greatest extent possible, we’re seeing a proliferation of all kinds of domain-specific architectures. Which in the normal cycle of these things inevitably leads to wondering if there might be a good general-purpose architecture for AI chips. One recent entry in this field is from Simple Machines, based in San Jose. They have a novel approach they call Composable Computing, in which they build on four fundamental behaviors: data gathering, computational dataflow, synchronization between algorithm stages, and control. Using this platform, they illustrate how they can reconfigure on-the-fly to implement multiple different types of accelerator. To do that, the needed help from Emulation as a Service (EaaS).

Emulation as a Service

Early software prove-out through EaaS

The tricky part is the software. To take advantage of that composability and specialization in behaviors a compiler needs to manage computation placement, data routing, event timing, resource utilization and other goals. This is not a regular compiler and must be tested very carefully. Compounding the problem, workloads for AI engines are huge. So how are you going to test, debug and refine that software while the hardware is still in development?

The normal answer would be an FPGA prototype. Which would work for a small inference engine. But these big general-purpose engines are designed for training as well as inference. They barely fit in an SoC reticle, much less in a single FPGA. And custom FPGA boards come with their own problems. So Simple Machines turned to emulation, with Mentor.

The emulation challenge for startups

Simple Machines is a young company, still on their Series A round and still proving themselves to early stage customers. I’m guessing that they are talking to strategic investors who might want to participate in a Series B round. To raise that level of interest, Simple Machines will need to show a proof of concept to those investors, perhaps early silicon or an emulation prototype. But emulators are expensive. How could Mentor help?

Through Emulation as a Service is how. The ‘as a Service’ concept has taken off widely for organizations that doesn’t have the constant heavy workloads to justify purchasing hardware and software. Emulation needs in a startup are a good example of a cyclic need. Simple Machines can buy access in blocks rather than buying the emulator.

The EaaS flow

John Anderson, Verification Consulting Manager at Mentor told me how this works. Mentor establishes a secure chamber (a virtual Linux host) loaded with Mentor software for emulation and debugging. They also establish an encrypted Mentor Secure Transport (MST) channel for a customer to support secure transfer of data between their site and that chamber. That customer also gets remote desktop software to allow VPN-like access to their own chamber.

As needed Simple Machines were able to upload their design and software to the chamber. The Mentor’s EaaS team provided expert consulting to optimize the cost- and time-efficiency advantages of the Veloce emulation hardware technology. Simple Machines could then compile code, launch jobs, debug and edit designs in the remote chamber via their desktop interface. Once they were done, they could pull results back to their own machines via MST.

Performance and power modeling

One more noteworthy point. Simple Machines were using EaaS not only to model performance but also to model power consumption to assess key power metrics in this pre-silicon design. Modeling the most important aspects of their prototype in preparation for discussions with those strategic investors.

You can read the press release HERE.

Also Read:

WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido

Creating Analog PLL IP for TSMC 5nm and 3nm

Getting Physical to Improve Test – White Paper

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