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An update here: https://frederickchen.substack.com/p/stochastic-pupil-fill-in-euv-lithography, particularly relevant to Stochastic Effect of Large Pupil Fill.
We are hiring! Are you passionate about microprocessor architecture? We need you! As a Post-silicon Validation Engineer, you will work within the Validation Team and play a crucial role in ensuring the correctness and functionality of complex digital designs using advanced verification methodologies and tools to validate the designs.
What do we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)
Requirements
Master or PhD
English C1
Industrial experience +8 years
Proficiency in SystemVerilog and UVM
Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
Experience with simulation and simulation tools
Knowledge of revision control methodology and tools (git, svn)
Experience in block level and sub-system or top level verification
Experience with formal and dynamic verification
Strong problem-solving skills and attention to detail
Excellent communication and teamwork abilities
Good understanding of hardware architectures and knowledge how to create test scenarios for system level IC designs
Experience in FPGA prototype emulation and debug
Well versed in the usage of advanced lab equipment (scopes, BERTs, programmable power supplies, etc).
Knowledge of scripting languages (Python, Bash)
Knowledge of peripheral interfaces like SPI, UART, I2C and JTAG
Experience in using emulation and prototyping systems like HAPS, Veloce or Zebu is a plus
An update here: https://frederickchen.substack.com/p/stochastic-pupil-fill-in-euv-lithography, particularly relevant to Stochastic Effect of Large Pupil Fill.
Podcast EP267: The Broad Impact Weebit Nano’s ReRAM is having with Coby Hanoch