TSMC statement on next-generation EUV

[Fred Chen]

TSMC says it doesn't need High-NA EUV chipmaking tools for 1.6nm-class node, but Intel has championed the tech

Maybe some other time?

www.tomshardware.com

TSMC says its newest process tech doesn't need ASML's High-NA EUV chipmaking tools that have been championed by Intel, but the foundry is exploring the tech for future use.

According to Reuters, Zhang told attendees of the event that the A16 process technology will not need the next-generation EUV lithography tools. This implies means that TSMC has found ways to cost-efficiently use EUV double patterning and pattern shaping to increase the achievable critical dimension of a modern Low-NA litho system beyond 13nm. In contrast, Intel plans to insert High-NA EUV tools with its 14A manufacturing technology after it learns how to efficiently use them with its 18A production node.

TSMC is not standing still, though. The company is exploring High-NA EUV lithography for its future process technologies. The A14 node will follow A16, and as TSMC noted in its 2023 Annual Report, A14 development is well underway.

"TSMC started development and made good progress on 14 Angstrom (A14) technology, which aims to further improve speed, power, density and cost," the company's Annual Report reads. "Looking ahead to A14 and beyond, TSMC R&D will continue to explore next generation EUV (extreme ultraviolet) lithography scanners, conduct research on mask pellicles and blanks to support leading-edge technology and extend Moore's Law."

Using High-NA EUV lithography systems greatly increases fab costs as each tool costs $385 million or more depending on the configuration. Chipmakers tend to re-use as many tools as possible, so TSMC may not be inclined to use High-NA EUV before it runs out of ways to introduce improvements to its production capabilities using Low-NA EUV tools. For example, last year, the company improved the critical dimension and pattern fidelity as well as lowered defect density by modifying photoresist and blank materials as well as optimizing mask process recipes. It also uses deep learning for inspection and discovering defects.

"In 2023, to achieve the wafer yield and productivity for lithography requirements at 2nm node, the R&D team improved the critical dimension, pattern fidelity, overlay stability, exposure durability, and defect mitigation of curvilinear patterns by EUV photoresist and blank material modification, multi-beam writer resolution enhancement, mask process recipe optimization, and advanced deep learning inspection," TSMC said in the report. "Future improvements will focus on developing new blank materials and new mask process technology at the A14 node and beyond."

TSMC's announcement of its A16 process technology (1.6nm-class) with Super Power Rail backside power delivery came as a surprise at the company's North America Technology Symposium 2024. Kevin Zhang, Vice President of Business Development at TSMC, said that the world's largest contract chipmaker had to speed up development of the production node due to rising demand from the AI sector, reports Reuters.

 

[SteveD]

Since A16 was initially defined as N2P + backside power, it makes sense that it doesn't use High-NA EUV.

 

[Fred Chen]

Since A16 was initially defined as N2P + backside power, it makes sense that it doesn't use High-NA EUV.

It looks like A14 development is not hinging on High-NA either:

"TSMC started development and made good progress on 14 Angstrom (A14) technology, which aims to further improve speed, power, density and cost," the company's Annual Report reads. "Looking ahead to A14 and beyond, TSMC R&D will continue to explore next generation EUV (extreme ultraviolet) lithography scanners, conduct research on mask pellicles and blanks to support leading-edge technology and extend Moore's Law."

 

[IanD]

Since A16 was initially defined as N2P + backside power, it makes sense that it doesn't use High-NA EUV.

And N2 isn't much different to N3 really, some pitches are a bit smaller but nothing radical, the main difference is GAA transistors instead of FinFET. Whatever fab technology is good enough for N3 is absolutely fine for N2 and A16, they're all the same process family with addition of first GAA and then SPR.

What happens with A14 is unknown, there are no process details yet. Even so High-NA only makes sense when it becomes cheaper or higher-yielding than double-patterning and enough machines are available to fill giga-fabs, and I don't think it's obvious yet when this will happen -- maybe A14 will use both, DP at first switching over to more high-NA as cost drops and volumes go up? Or maybe A14v1 will use DP and A14v2 will use high-NA?

In the end it doesn't matter how sexy high-NA is, it'll get used for high volume TSMC fabs when it's cheaper/better than DP (including yield) and ASML can make enough of them.

 

[Fred Chen]

Right now a bigger problem than High-NA is the EUV resist, a little surprised that was not explicitly mentioned in the TSMC report:

(from ASML's HNA print)

 

[cxy11]

if people are already discussing about DUV SAQP feasibility for N5 patterning, then why High-NA EUV is a must for A14 (even A10) ?

 

[IanD]

if people are already discussing about DUV SAQP feasibility for N5 patterning, then why High-NA EUV is a must for A14 (even A10) ?

It's not a must, double-patterned EUV will work fine, just like it does for N3/N2/A16 where there are already a few double-patterned EUV layers.

However if the pitches shrink significantly for A14 the number of DP EUV layers will rise rapidly, and if a single high-NA EUV exposure replaces two DP ones the TAT and cost will drop and yield will improve -- but only so long as the high-NA cost and machine throughput and availability work economically, which may well not be the case for some time.

This isn't a "hero experiment", it's a question of which method -- DP or high-NA EUV -- gives the best economics in mass production, and can support the required volume. And it's not clear when this will be and at which node, regardless of how much Intel brag about having the first high-NA EUV machine... ;-)

 

[Daniel Nenni]

I was there for this Q&A, it was pretty lame. Privately however I was told HNA-EUV would not be production ready in time for A16 and TSMC really wanted to get BSPD out for the big AI companies. I also asked if TSMC is getting the second HNA-EUV machine that ASML is shipping and I got a no comment with a sly grin.

TSMC is bringing N2 and A16 in fast to compete with Intel, even though Intel is still not perceived as a real threat to the foundry business, yet. Quite a few people wondered if HNA-EUV would be ready for A14. Remember, TSMC will need MANY systems. Today they have more than half of the EUV systems in the field. I'm still looking for the ASML HNA delivery schedule. They will need to ship enough systems for Intel, Samsung, and TSMC.

If we are talking about the low risk plan, HNA-EUV may not be available to TSMC customers until 2030 which would probably be TSMC A10, my opinion.

 

[Xebec]

Is Apple still (“demand”) driving the “1 new node [of some kind] per year” from TSMC or has it actually pivoted to AI products?

 

[hskuo]

Right now a bigger problem than High-NA is the EUV resist, a little surprised that was not explicitly mentioned in the TSMC report:

View attachment 1890
(from ASML's HNA print)

Fred: Millions of EUV printed wafers using EUV resist had been produced. There are always problems in the processes to be continuously improved. The most problem I heard in the field is how to lower resist dose-to-size and improve scanner productivity. That is the reason intel promoted DSA rectified EUV patterning in SPIE 2024 which showed >60% dose reduction with similar or lower LWR result, which attracted a lot of attentions. FYI.

 

[Daniel Nenni]

Is Apple still (“demand”) driving the “1 new node [of some kind] per year” from TSMC or has it actually pivoted to AI products?

Apple is intimately partnered with TSMC so they are steering the mobile processes. Apple is part of TSMC's risk aversion program so they get what they get.

Apple does get a new node version every year, one that no one else can use, that has not changed. Apple will get a new N3 version this year and hopefully N2 next year, we shall see. I think all Apple phones and Macs will be on N3 this year, unlike last year.

 

[Fred Chen]

The most problem I heard in the field is how to lower resist dose-to-size and improve scanner productivity. That is the reason intel promoted DSA rectified EUV patterning in SPIE 2024 which showed >60% dose reduction with similar or lower LWR result, which attracted a lot of attentions. FYI.

Maybe Intel just gave away their power is not so high, possibly a pellicle limitation.

 

[cxy11]

It's not a must, double-patterned EUV will work fine, just like it does for N3/N2/A16 where there are already a few double-patterned EUV layers.

However if the pitches shrink significantly for A14 the number of DP EUV layers will rise rapidly, and if a single high-NA EUV exposure replaces two DP ones the TAT and cost will drop and yield will improve -- but only so long as the high-NA cost and machine throughput and availability work economically, which may well not be the case for some time.

This isn't a "hero experiment", it's a question of which method -- DP or high-NA EUV -- gives the best economics in mass production, and can support the required volume. And it's not clear when this will be and at which node, regardless of how much Intel brag about having the first high-NA EUV machine... ;-)

so, Intel's late EUV adoption was a bad decision, now their early High-NA EUV adoption maybe another one ?!

 

[Daniel Nenni]

so, Intel's late EUV adoption was a bad decision, now their early High-NA EUV adoption maybe another one ?!

Had Intel 10/7 come out when TSMC N7 and Samsung 7nm (non EUV), Intel would have done very well. But Intel had organizational issues and a serious lack of leadership. If you want to blame someone blame the Intel board for hiring BK as CEO.

I think Intel's early HNA EUV R&D is great for the industry, absolutely. And I do believe they will get good PR out of it. On the IDM side Intel can use HNA EUV for CPU and GPU chiplets in limited quantities. I do not however think Intel Foundry will benefit from it since HNA EUV for foundry HVM is a long ways away, my opinion.

 

[hskuo]

Had Intel 10/7 come out when TSMC N7 and Samsung 7nm (non EUV), Intel would have done very well. But Intel had organizational issues and a serious lack of leadership. If you want to blame someone blame the Intel board for hiring BK as CEO.

I think Intel's early HNA EUV R&D is great for the industry, absolutely. And I do believe they will get good PR out of it. On the IDM side Intel can use HNA EUV for CPU and GPU chiplets in limited quantities. I do not however think Intel Foundry will benefit from it since HNA EUV for foundry HVM is a long ways away, my opinion.

Daniel:
1. I membered tsmc started N7 without EUV, but Samsung used EUV in SF7.
2. IMO, IFS is with high probability to lose big money for a long period of time and hope intel has deep pocket and always injects fresh blood to save the life. Because
a. Historically, it takes at least 2-3 years to win a big customer from engagement to ramp, to HVM. If 14A will be HVM ready in 2026 and everything will be executed
precisely and successfully, I would expect the tipping point will be after 2029.
b. In catch-up mode and as follower, it will need 10~20% die price lower as switching cost. As we all know, manufactured in US might have ~20% wafer cost higher
than in Taiwan. If tsmc's N2/A16/A14 GM is ~40%, then intel could start from GM 10~0% if the D0 is comparable and use the same EUV tools as tsmc. It is quite
challenging. Now intel bets on more expensive and not HVM ready HiNA EUV scanner. Intel needs not just deliver 14A on-time, but superfast yield ramp.

I would not say it is impossible, but I think intel bets on the goal which has very high possibility of missing the tight schedule, too many uncertainties.

 

[nghanayem]

so, Intel's late EUV adoption was a bad decision, now their early High-NA EUV adoption maybe another one ?!

Why would anyone assume it is a bad decision. Intel wasn’t forced to adopt high-NA for 14A. They looked at the numbers and thought that this would give either the best cost or at worst the most reasonable tradeoff between cost and ease of use (something that presumably matters more for an upstart like intel than someone who is the default like TSMC). Intel also showed off a wafer at IFC-DC before their first R&D tool has even run a single development wafer. Well gee I wonder if the company that said all process modules are now troubleshooted in a vacuum with contingencies in place has a low-NA version of 14A pre intel having any high-NA tools to develop 14A with . To further support this line of reasoning, if we assume that intel is around as fast at TD as TSMC is then intel would have started 14A development 2-4 years ago.

If we assume that intel is making a wrong call to use high-NA for even a single layer, and that there is no design rule simplification either. Well okay then TSMC is in the wrong too. On their recent call while they did say that A16 wouldn’t “need” high-NA, they also said it would “cost less to make” if they did use high-NA. Are we to assume the integrators and the lithographers for TSMC AND intel don’t know how to do their jobs? While it isn’t great that TSMC’s teams will effectively be starting a whole quarter behind. I wouldn’t exactly call that a rejection of high-NA like folks make it out to be. They also get to pick up ASML’s learnings from IMEC/intel on their own path to their first install/qual. That would be like saying TSMC rejected EUV because intel/IBM got the first development tools and Samsung had a roadmap with an earlier intercept. But I will leave it there since I already commented on why there are plenty of non economic and non tool quantity reasons for TSMC to not use it on N2/A16.

 

[hskuo]

Why would anyone assume it is a bad decision. Intel wasn’t forced to adopt high-NA for 14A. They looked at the numbers and thought that this would give either the best cost or at worst the most reasonable tradeoff between cost and ease of use (something that presumably matters more for an upstart like intel than someone who is the default like TSMC). Intel also showed off a wafer at IFC-DC before their first R&D tool has even run a single development wafer. Well gee I wonder if the company that said all process modules are now troubleshooted in a vacuum with contingencies in place has a low-NA version of 14A pre intel having any high-NA tools to develop 14A with . To further support this line of reasoning, if we assume that intel is around as fast at TD as TSMC is then intel would have started 14A development 2-4 years ago.

If we assume that intel is making a wrong call to use high-NA for even a single layer, and that there is no design rule simplification either. Well okay then TSMC is in the wrong too. On their recent call while they did say that A16 wouldn’t “need” high-NA, they also said it would “cost less to make” if they did use high-NA. Are we to assume the integrators and the lithographers for TSMC AND intel don’t know how to do their jobs? While it isn’t great that TSMC’s teams will effectively be starting a whole quarter behind. I wouldn’t exactly call that a rejection of high-NA like folks make it out to be. They also get to pick up ASML’s learnings from IMEC/intel on their own path to their first install/qual. That would be like saying TSMC rejected EUV because intel/IBM got the first development tools and Samsung had a roadmap with an earlier intercept. But I will leave it there since I already commented on why there are plenty of non economic and non tool quantity reasons for TSMC to not use it on N2/A16.

Some inputs for you.
1. Hi NA EUV scanner is still under development and HVM tool will be introduced as early as 2025. It will take some time to mature the tool from vendor's HVM to really mass production ready. For EUV scanners, I do not see any tool schedule has been pull-in up to now. Will ASML achieve it this time?
From ASML roadmap, we can see for low NA HVM tool, it will take two years cadence to introduce new tool, Will we see 1 year cadence in HNA EUV tool which has a lot of innovated modules? Let's see.
2. tsmc A16 is basically N2P+SPR (Backside, Super Power Rail). EXE5200 seem not meet schedule. So it makes sense not see HNA EUV in A16. For tsmc A14, it is still early to reveal the detail plan. As you might know, when intel or tsmc showed off their new technology, it will benchmark POR to new processes. It means we would expect the yield data comparison between Low NA EUV multiple patterning wafers vs. HiNA wafers in conferences like IEDM or SPIE as early as next year. No need to jump to conclusion from PPT results now.
We all wish ASML, intel, Samsung and tsmc go well, compete with each other and the end users enjoy the product price lower eventually.

 

[Fred Chen]

Why would anyone assume it is a bad decision. Intel wasn’t forced to adopt high-NA for 14A. They looked at the numbers and thought that this would give either the best cost or at worst the most reasonable tradeoff between cost and ease of use (something that presumably matters more for an upstart like intel than someone who is the default like TSMC). Intel also showed off a wafer at IFC-DC before their first R&D tool has even run a single development wafer. Well gee I wonder if the company that said all process modules are now troubleshooted in a vacuum with contingencies in place has a low-NA version of 14A pre intel having any high-NA tools to develop 14A with . To further support this line of reasoning, if we assume that intel is around as fast at TD as TSMC is then intel would have started 14A development 2-4 years ago.

If we assume that intel is making a wrong call to use high-NA for even a single layer, and that there is no design rule simplification either. Well okay then TSMC is in the wrong too. On their recent call while they did say that A16 wouldn’t “need” high-NA, they also said it would “cost less to make” if they did use high-NA. Are we to assume the integrators and the lithographers for TSMC AND intel don’t know how to do their jobs? While it isn’t great that TSMC’s teams will effectively be starting a whole quarter behind. I wouldn’t exactly call that a rejection of high-NA like folks make it out to be. They also get to pick up ASML’s learnings from IMEC/intel on their own path to their first install/qual. That would be like saying TSMC rejected EUV because intel/IBM got the first development tools and Samsung had a roadmap with an earlier intercept. But I will leave it there since I already commented on why there are plenty of non economic and non tool quantity reasons for TSMC to not use it on N2/A16.

There were some hints the decision by Intel to pursue High-NA was made without thinking everything through. The clearest evidence is their sudden push for a larger (2X) mask size, supposedly driven by cost.

 

[hist78]

Daniel:
1. I membered tsmc started N7 without EUV, but Samsung used EUV in SF7.
2. IMO, IFS is with high probability to lose big money for a long period of time and hope intel has deep pocket and always injects fresh blood to save the life. Because
a. Historically, it takes at least 2-3 years to win a big customer from engagement to ramp, to HVM. If 14A will be HVM ready in 2026 and everything will be executed
precisely and successfully, I would expect the tipping point will be after 2029.
b. In catch-up mode and as follower, it will need 10~20% die price lower as switching cost. As we all know, manufactured in US might have ~20% wafer cost higher
than in Taiwan. If tsmc's N2/A16/A14 GM is ~40%, then intel could start from GM 10~0% if the D0 is comparable and use the same EUV tools as tsmc. It is quite
challenging. Now intel bets on more expensive and not HVM ready HiNA EUV scanner. Intel needs not just deliver 14A on-time, but superfast yield ramp.

I would not say it is impossible, but I think intel bets on the goal which has very high possibility of missing the tight schedule, too many uncertainties.

In the past 15 years Intel spent precious money in share buyback program, dividends, and the infamous "contra- revenue" gimmick, there's no deep pocket left for Intel.

Intel needs to sell more products to maintain revenue and improve its cash flow, no matter the products are made in house or by external foundries. Intel Foundry's revenue and profit (if any) won't be big enough and quick enough to help.

 

[nghanayem]

Some inputs for you.
1. Hi NA EUV scanner is still under development and HVM tool will be introduced as early as 2025. It will take some time to mature the tool from vendor's HVM to really mass production ready. For EUV scanners, I do not see any tool schedule has been pull-in up to now. Will ASML achieve it this time?
From ASML roadmap, we can see for low NA HVM tool, it will take two years cadence to introduce new tool, Will we see 1 year cadence in HNA EUV tool which has a lot of innovated modules? Let's see.

Valid input. But for what’s worth intel said 14A was 2 years after 18A so intel has 2 years rather than 1. It is also is worth baring in mind this is a far smaller labor from ASML than EUV was. As a result I have to assume there is comparatively little uncertainty around the tool’s capabilities.

2. tsmc A16 is typically N2P+SPR (Backside, Super Power Rail). EXE5200 seem not meet schedule. So it makes sense not see HNA EUV in A16. For tsmc A14, it is still early to reveal the detail plan.

Bingo. If A14 was lacking high-NA I think there would be a stronger argument that intel wants to jump the gun too early. But as you pointed out N2 family is just coming out too soon for this to make sense, with a retrofit making even less sense. But in the meantime I have no reason to believe that they won’t since TSMC stated that they think it would be more economical. I would never claim to be a litho expert, but I would bet on 2 major logic houses and Scotten over the uncertainties we might have.

As you might know, when intel or tsmc showed off their new technology, it will benchmark POR to new processes. It means we would expect the yield data comparison between Low NA EUV multiple patterning wafers vs. HiNA wafers in conferences like IEDM or SPIE as early as next year. No need to jump to conclusion from PPT results now. We all wish ASML, intel, Samsung and tsmc go well, compete with each other and the end users enjoy the product price lower eventually.

Agreed. I just don’t make assumptions around others failing. So it is just perplexing that I see all the talk of how intel is destined to have made the “wrong call”, but TSMC making the same claim is somehow a rejection of intel’s theory and is objectivity the “correct” move. My personal philosophy is that assuming competitors can’t do what they say they will is a great way to fall behind. This is especially true when all three of the logic houses are as fearsome as they are.

There were some hints the decision by Intel to pursue High-NA was made without thinking everything through. The clearest evidence is their sudden push for a larger (2X) mask size, supposedly driven by cost.

Why would that constitute a hint? Wouldn’t intel always want to move to larger reticles if they have made the choice to go to high-NA? Even if high-NA was 50% the cost of EUV SALELE instead of the 90% that Scotten projected in his article, you would always want to go to that larger reticle to get costs even lower. If someone doing a reticle sized die is using IF then they would also no longer need to worry about stitching which is a cost improvement for the foundry and the customer who now needs less work/fewer masks. If I was to pick any evidence of intel leaping before looking it would be announcing the intent to use high-NA before even having their first development scanner up. Either way it is incomprehensible that from mid level lithographers/intergrators, to Mark, Ann, and then Pat didn’t do their due diligence before deciding that high-NA would be valuable to the 14A program. If a decision that big can go through the whole chain without good feasibility studies I have genuinely no clue how intel lucked into figuring out how to fix 10nm or how to ship intel 4/3.