Is Low Power a Challenge? ICE-Grain Answers the Challenge

Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.

It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they are automatic, take them. But to get serious power saving you have to power down blocks, gate clocks, scale voltages and so forth. But this stuff is hard. The most advanced design groups have teams that specialize in this stuff but mainstream SoC groups find it challenging. It usually requires interaction between software and hardware and, unfortunately, the embedded software engineers do not really understand much about the chip, and the designers don’t really understand the software peoples’ issues. Often power saving registers are unused, at least in the first version of the design, since there isn’t time to get it all working together. There is complex timing associated with powering blocks up and down or varying their frequency, and this is complex to manage in software since the software has other stuff it has to do in parallel. So the processor has to do more than run a device driver for as much as a millisecond or two while it all happens and that sort of programming is hard. Despite working in Semiconductor/EDA all my career, my PhD is in operating systems so I have the scars. I have written my share of device drivers.

The biggest savings come from basically exploiting when blocks are going to be idle. To make the design manageable, it is attractive to have relatively few blocks to worry about, but then the chance of them being completely idle diminishes compared to a higher number of smaller blocks. An additional complexity comes from not really knowing if it is worth powering a block down in advance, which can lead to a power-thrashing whereby a block is not even fully turned-off before it is required and has to be brought up again, which wastes power.

So what what would an ideal power manager look like?

• Instantly detect idle blocks (and somehow know they would continue to be idle for long enough in the future)
• Instantaneously reduce the power
• Instantly notice when a block needs to be active and instantly power it up again
• Across a huge number of fine-grained domains with no power or area overhead
• And a pony

Well, OK, that is a dream. You are not going to get it. But how close can we get?

Sonics ICE-Grain Power Architecture is an approach that comes close. Note that at this stage Sonics are not announcing a full product, this is technology that they have been working on for 5 years and where they are starting to engage with lead partners and are looking for more. It is also perhaps worth pointing out that the initial products will be targeted at mainstream SoC groups who struggle with this sort of power management, not with very large groups who already understand the technology and have specialized teams and methodologies in place. Plus, although there are some gains from using ICE-Grain with Sonics NoC technology, it is not necessary; the two are independent.

So what’s with the weird name? ICE-Grain comes from two things:
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