ASIC Days Are Here Again

Technology often goes in cycles. Thirty years ago the dominant mode of computing was a shared computing resource with comparatively dumb terminals. Think of a Vax accessed by terminals. Then workstations and the PC came along and the dominant mode became a computer on everyone’s desk. Then the smartphone came along and so now the dominant mode is back to a centralized cloud with comparatively under-resourced terminals (although much smarter than the old VT100 terminals of the 1980s.).

Drew Wingard, the CTO of Sonics, gave a presentation at IP-SoC on the ASIC/ASSP cycle. He started with a digression on Makimoto’s wave which predicts these types of transitions on a decadal timescale. For the last ten years or so the market (foundries, EDA flows, IP requirements) have been driven almost entirely by application processors for mobile (except inside Intel) delivered as ASSPs (such as Qualcomm’s Snapdragon).

Let’s look at 3 markets.

First, application processors. So how can system companies differentiate their products? If they all use the same SoCs they cannot. So Samsung and Apple changed the rules and designed their own chips, going to something closer to an ASIC model (not really the old ASIC model where the interface was netlist though). This took away so much of the market that many players were forced out: ST, Freescale, even Texas Instruments (which had #1 market share in 2010 and exited the market and shutdown their Villneuve-Loubet facility in the south of France in 2012). The market is now dominated by Apple and Samsung, with ASICs, and Qualcomm and Mediatek (with ASSPs).

Next market, cellular basestations. This was traditionally an ASSP business then the market started to fragment with the need for higher performance LTE basestations at the same time as the need for smaller cells for infill and overlay. So one part no longer worked for all and so this market has also largely gone back to an ASIC model, although with custom IP from companies like Ceva, Tensilica/Cadence and ARC/Synopsys to build the processors flexibly.

Third market, wearables (and probably other segments of the IoT market). Form factor and battery life reqire high integration but the end requirements are unclear. This creates the requirement for “premature integration.” Right now the only thing that can be done is to sacrifice cost to learn from the market, since unattractive prototypes that are too large or too power-hungry will automatically be unsuccessful and no learning will take place. So for now this is an ASIC or ASIC-like market too.

Wearables are a special challenge having these contradictory dimensions. Sonics NoCs can help. At first glance this seems like it might be overkill for such a simple design but probably it is not so simple:

Using a NoC allows an AgileIC methodology, allowing rapid prototyping, followed by rapid creation of production designs once the learning has taken place.

More information on Sonics NoC technology is here. For an introduction watch the webinar here.