NoC 101, a Sonics Webinar

One of the things that I’ve been telling the people at Sonics when they will listen is that they should do a bit more basic education on Networks on Chip (NoC). Sure, the people who actually use Sonics’s products care about deep details such as security and power management, but there is a whole host of designers who have never used a NoC and have only the vaguest idea of what it is. Increasingly, designing an SoC is assembling a lot of IP blocks, perhaps hundreds, and a NoC is the best way to hook them up. It is prohibitively expensive in terms of area, power and design effort to put buses all over the chip as would have been done ten years ago. On November 20th at 10am (Pacific) Sonics are presenting an introductory webinar entitled NoC 101. I will be there to introduce the speakers and moderate the Q&A. The main speaker will be Drew Wingard the Sonics CTO.

One of the things that a NoC does is separate functionality in way that makes the design much more flexible. If every block has to know about the bus architecture details then designers are forced to work at too low a level and the design becomes very tightly-coupled, as in the picture above. This is especially important when doing derivative designs, or taking a design from one generation to the next. Changing the communication architecture becomes an enormous task. In a modern process, wire delay can become dominant and can become the limiting factor of the overall system frequency.

What a NoC brings is that it decouples the communication infrastructure from the blocks. The NoC can interface to any type of block, synchronous or asynchronous, new or legacy, different bus widths and so on. It means that designing and assembling the blocks is orthogonal to designing and implementing the communication architecture. If the performance is not met it is fairly easy to change the NoC. When a design goes from one generation to the next then the NoC goes too, and all the additional blocks for the next generation design can be added in a straightforward manner.

The webinar will cover:

• what is a NoC and why should I care?
• design abstraction levels
• limitations of the tightly coupled approach
• using a decoupled NoC approach
• design example using both approaches
• clock and power domain crossing issues
• NoC design input and verification
• wrap up

There will be a Q&A at the end of the webinar.

Register for the webinar here.