Sonics Performance Monitor and Hardware Trace

As SoCs have got more complex, and with a larger and larger software content, it is no longer good enough to just monitor how the design behaves using simulation and then completely forget about it once the design is complete. What is required is the capability to monitor the design in real time (in silicon or FPGA) to see how it is behaving. If there are problems then potentially these can be fixed in software (or hardware when using FPGA prototypes).

Sonics have just announced Sonics Performance Monitor and Hardware Trace (SMT) that does just this. To make things easier for users the technology is integrated in with ARM’s Coresight. People use Coresight today to see the transaction traffic at the processor core(s). Now that can use SMT to see at at each IP block in the system, of which there may be hundreds. They can see, for example, why some transaction seems to be delayed, perhaps because there is other higher priority traffic using up the bandwidth. This can be especially important when monitoring traffic to off-chip memory, which is always one of the critical activities that affect performance.

SMT automatically inserts functionality into the NoC that allows the designer to:

• Profile system behavior and performance metrics
• Tune SW for optimal performance
• Characterize power behavior
• Full chip visualization

Easy integration into ARM CoreSight debug systems

• Compliant with CoreSight Visible Component Architecture
• Full support for CoreSight features: cross-triggering, authentication and global timestamps
• Discovery and programming via CoreSight Debug Access Point (DAP)
• Automatic support from CoreSight-compliant debuggers

There is also basic support for other (non-CoreSight) debug systems. And performance monitor-only support does not require any debug system

By using SMT with FPGA prototypes, the hardware can be tuned, and the software optimized. By using it in silicon, the detailed performance of the design can be analyzed in real time in detail.