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Custom IC Panel: Winning the Custom IC Design Race!

Custom IC Panel: Winning the Custom IC Design Race!
by Daniel Nenni on 05-19-2015 at 12:00 pm

 Back in the day, EDA companies enabled the foundries. Seriously, those pesky little foundries chased us EDA companies around like puppies who needed a walk. Now, emerging EDA and IP companies are the puppies and we chase the foundries. Solido Design Automation is one of the hardest working puppies that I have ever helped with strategic foundry relationships. I know them well and can tell you that Solido is THE most exciting EDA company focused on custom IC design today. They are technology and market leaders with 90% revenue growth last year, absolutely.

Solido will be a busy little pup at #52DAC next month. They will be hosting a Custom IC Panel

Winning the Custom IC Design Race at Nanometer & Low Power Processes

which will discuss how companies are navigating the tradeoff between reducing underdesign to improve yield, and reducing overdesign to improve power, performance and area. Panelists will share techniques to accelerate high performance, low power custom IC design, while reducing risk of re-spins due to increased variation at nanometer and low power process nodes. Memory, standard cell, custom digital and analog/RF design applications will be discussed.

Panelists include Alfred Yeung (Applied Micro Circuits), Dragomir Nikolic (Cypress Semiconductor), Sifuei Ku (Microsemi) and Jeff Dyck (Solido). Solido CEO Amit Gupta will be giving an opening presentation on custom IC market data. Register here for the panel: https://www.surveymonkey.com/s/7CPXFM6

This is my all time favorite Solido slide. See the guy falling off the edge? That’s you if you don’t use Solido Variation Designer. Especially if you are designing with FinFETs!

Solido will be presenting at the TSMC DAC OIP Theater on their software integration at TSMC FinFET and low power processes. Dates and times will be announced shortly.

Solido will also have 3 demos at the DAC booth, showing how their product is being used in industry for memory, standard cell, and analog/RF/custom digital design. Details are below, register here for a demo: http://www.solidodesign.com/page/dac-2015-demo-signup/

Solido Variation Designer for Memory

Full Chip Memory and Cell Level Statistical Verification
See how Solido’s customers are using Variation Designer for memory design:

  • Hierarchical Monte Carlo: Verify full-chip memories with perfect statistical accuracy with Solido’s newest memory technology

    • Statistically correct verification of replicated structures
    • Correct application of both global and local variation
  • High-Sigma Monte Carlo: Verify columns, bitcells, sense amps, and other memory blocks to high-sigma quickly and with perfect Monte Carlo and SPICE accuracy
  • Scale to support real-world circuits (such as memory columns and critical paths)
  • Solve pass/fail, binary, and multi-modal output measurements
  • Efficiently debug high-sigma variation problems
  • Produce trustworthy high-sigma verification results
  • Variation Designer 4.0: Preview Solido’s upcoming Variation Designer major release with a suite of brand new features for memory designers

Solido Variation Designer for Standard Cell
Statistical Verification and Sizing of Cell Libraries
See how Solido’s customers are using Variation Designer for standard cell design:

  • High-Sigma Monte Carlo: Fast, accurate, scalable, and verifiable high-sigma verification of standard cell libraries

    • Accurately capture performance and power vs. sigma tradeoffs for the entire sigma range
  • Cell Optimizer: Fast, accurate optimization of standard cells
  • Variation-aware optimization across PVT corners, Monte Carlo corners, and High-Sigma Monte Carlo corners
  • Highly flexible setup of variables, goals, and constraints
  • Batch operation for optimizing complete cell libraries
  • Variation Designer 4.0: Preview Solido’s upcoming Variation Designer major release and its suite of enhancements for batch analysis of standard cell libraries

Solido Variation Designer for Analog/RF and Custom Digital
Statistical & PVT Verification and Debug
See how Solido’s customers are using Variation Designer for analog/RF and custom digital design:

  • Statistical PVT: Solido’s all-new capability delivers unprecedented accuracy and coverage across 3-sigma statistical variation and operating conditions
  • Fast PVT: 2-50X faster verification across corners & operating conditions
  • Fast Monte Carlo: Fast, accurate 3-sigma verification & corner extraction
  • High-Sigma Monte Carlo: Fast, accurate, scalable, and verifiable high-sigma Monte Carlo verification and design for analog/RF and custom digital circuits
  • Variation Designer 4.0: Preview Solido’s upcoming Variation Designer major release and its enhancements to make variation-aware design of analog/RF and custom digital circuits even faster, more thorough, and easier than ever

Register here for a demo: http://www.solidodesign.com/page/dac-2015-demo-signup/

Bottom line:
Solido wrote the book on variation, literally. See a Solido demo at #52DAC and get one while they last!


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