Analyzing Power Nets

One of the big challenges in a modern SoC is doing an accurate analysis of the power nets. Different layers of metal have very different resistance characteristics (since they vary so much in width and height). Even vias can cause problems due to high resistance. Typically power is distributed globally on high-level metal layers, which have the lowest resistance, but eventually, of course, the power has to get all the way down to the transistors through the much higher resistance metal 1 and 2 and the associated vias. A full analysis requires accurate resistance in order to do IR drop analysis, electromigration (EM) analysis and thus the implications for reliability and timing.

Silicon Frontline’s P2P (it stands for point-to-point) performs full-chip transistor level IR drop and EM analysis for the power net design. It is focused on providing easy-to-setup and easy-to-use analysis that has the speed and unlimited capacity to handle the whole chip.

Power nets form very complex systems, reaching all parts of the chip. One of the guiding principles of P2P is progressive verification—find the gross errors first, in a straightforward way, and save the compute-intensive verification for the troublesome layout issues.

First, for a qualitative view of the power net the user performs resistance analysis. The user provides the GDS and top-level pad(s), and P2P automatically calculates resistance across the complete net and provides graphical and textual output of the results, color coded from blue to red as to how high the resistance is. The user can see at a glance the absolute resistance to every point on each power net, as well as the resistance gradient, making problem identification easy.

For more detailed quantitative view the user performs IR drop/EM analysis. The user just specifies the voltage sources and current sinks and P2P does the rest, doing a complete power net analysis in minutes. Static currents can be given for any level of hierarchy and refinement. Currents can be given for block (e.g. IP), for cell (e.g. cell library element), or for transistor (e.g. P2P automatically characterizes device current according to device width).

There are several ways of making use of this capability. One is full-chip, with currents for each circuit block defined as needed (determined by model availability and stage of design refinement). An alternative method is box based where the various blocks on the SoC are analyzed one after the other, in isolation, before all blocks are analyzed together in context. Additionally, the user can annotate arbitrary currents obtained from a variety of sources. For example, pick the peak block current from a SPICE simulation for one block, and a maximum IP block current from the provider’s datasheet. In this way, the user can analyze different time points with the SoC in different modes of operation, where these modes may have very different demands on the power distribution networks.

P2P visualization allows display of resistance mapping, voltage distribution, and current density in metal interconnect and vias. It can also highlight excessive current and produce layer-by-layer resistance reports making it easy to zero-in on critical contributors to total resistance.

In summary, P2P provides:

• easy to set-up and highly configurable, with no perturbation to existing flow
• fast and easy to use analysis of power nets, with unlimited capacity
• accurate resistance extraction for pad to pad, point to point, and multipoint to multipoint resistance, with layer by layer reporting for each power net
• resistance mapping of interconnect
• fast, accurate static IR drop analysis
• current density analysis highlighting EM issues

P2P can be used at any stage of design and verification, and by providing accessible data covering resistance/potential/current distribution guides users to designing robust power nets able to reliably provide needed currents to all areas of the die.