Semiconductor IP Validation Gets Faster

Semiconductor IP continues to grow in use for SoC design, and many chips can now use hundreds of IP blocks from multiple vendors. Validating the quality of the IP blocks is an important step in the design process, and you could perform manual validation and inspection of each new IP block at the expense of time and engineering effort. Another approach is to automate the process of IP validation, and you could start to write your own scripts and create your own IP validation system after spending many man-years of effort. There is a faster way to validate IP and that is to consider using EDA software from a company that has specialized in this area, and that company is Fractal Technologieswho offers a tool called Crossfire.

IP Validation Flow using Crossfire

Out of the box Crossfire already performs over 150 validation checks on your logical and physical IP file and database formats, but what if you needed to create your own customized checks? Newly added is the ability for you to code your own checks called a Crossfire setup by using an API (Application Procedural Interface). Most EDA companies offer you an API in only one language, however Fractal was quite accommodating by providing their new API in three languages: Python, Perl and TCL.

Here are some applications for writing user specified checks:

• Logical Design Checks

  • Check for busses when they may not be used
  • Check for your own bus naming conventions
• IC Layout Checks

  • Checking the area of a cell
  • Is the boundary layer on a correct grid
  • Does the boundary match the cell statements for dimensions and origin
  • Checking for half design rule distance at the boundary of a cell
  • Is the boundary layer on the top-level
  • Is the text hierarchy placed correctly

So, whether you simply use the built-in library validation checks with Crossfire, or add your own checks, the end result is that your latest SoC has a higher verification confidence level so that you can sleep better at night and improve your chances of first silicon success.

Redesigned Web Site

If you haven’t visited their web site in a while, then consider browsing their newly re-designed site. I found it much easier to navigate and find the info I was looking for. Their new header is a bit hypnotic as it gradually changes colors like a chameleon.

ChipEx and DAC

For our IC designers in Israel, you can visit the Fractal engineers at the ChipEx 2014conference from April 29-30 in Tel Aviv. Then in June 2-4 you can visit booth 507at the DACconference in San Francisco. I visited their booth at DAC last year and blogged about it here.

Further Reading

• Correct by Construction Semiconductor IP
• Semiconductor IP Library QA Just Got Easier
• Validating Hard IP & Std Cell Libraries at DAC
• Quality in Design Formats has become a must!
• Do my tests certify the quality of my products?
• Is my Library or Semi IP really OK to use?
• Crossfire – Builds Quality with Design

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