Variation Alphabet Soup

On-chip variation (OCV) is a major issue in timing signoff, especially at low voltages or in 20/16/14nm processes. For example, the graph below shows a 20nm inverter. At 0.6V the inverter has a delay of 2 (nominalized) units. But due to on-chip variation this might be as low as 1.5 units or as high as 3 units, which is a difference from slow to fast of 100%. Variation is not so bad at 1V but, for power reasons, everyone wants to get the voltage as low as possible since it is squared in the power equation also reduces leakage. Voltage is like sailing, if you want to win races, you have to sail close to the wind even though it is more difficult.

See also Voltage Limbo Dancing; How Low Can You Go?

The problem is on-die variation. We can’t assume that if one transistor is faster than typical that the transistor it is driving is also faster. There are a number of reasons for this but one big one is that optical proximity correction (OPC) means that identical transistors do not end up identical on the mask since that depends on what is around them.

In response, foundries have broken out on-die variation as a separate component in their SPICE models. They created global corners for slow, typical and fast. These global corners, called SSG (slow global), TTG (typical global) and FFG (fast global), only include between wafer variance. On-die variance is separated out as a set of local parameters as part of the SPICE model that work with Monte-Carlo (MC) SPICE around the global corners. Analog designers routinely use these global corners and local parameters to validate cells. These same global corners and local variance parameters can be used to create derates or adjustment factors for static timing and physical optimization of digital designs (and the digital parts of mixed-signal designs).

But how do you put this into the sign-off timing flow and delay models?

Obviously something needs to be done so everyone did something. Cadence, Synopsys and TSMC have all used multiple acronyms: OCV, AOCV, SBOCV, SOCV, POCV and LVF. Too many TLAs (and FLAs).

So how is all this represented? That’s what all the alphabet soup is about. The three main ingredients to the soup are OCV (on-chip variation), AOCV (advanced on-chip variation) and LVF (Liberty variance format). The table below shows the details.

So how is all this represented? That’s what all the alphabet soup is about. The three main ingredients to the soup are OCV (on-chip variation), AOCV (advanced on-chip variation) and LVF (Liberty variance format). The table below shows the details.

The bottom line is that OCV works well for 45nm and above but isn’t good enough for 28nm and below. SBOCV is TSMC’s name for adding more accuracy, and AOCV is what Cadence and Synopsys call it in their timing tools.

AOCV suffers from a major limitation though. There are only 8 values to cover all the different timing arcs through a cell. Even a simple two-input NAND gate may have 128 different AOCV multipliers: two inputs times 4 input slew rates times rising/falling times 8 output loads. To get it down to 8, the worst-case derates (or near worst) need to go in the file. But this means that AOCV is still unnecessarily pessimistic.

The solution is to use Liberty Variance Format (LVF). Why?

• unlike OCV (1 value per process corner) or AOCV (8 values per cell per corner), LVF models all possible conditions for a cell. Every arc, load and slew has unique variance information
• it is an independent standard governed by the Liberty TAB (that also controls the Liberty library format) approved in 2013 and revised in summer 2014 to support constraint uncertainty and slew sigma
• SOCV (a TSMC format) maps back and forth with LVF since the contents are largely the same, so there is no problem using LVF for designs that will be manufactured by TSMC
• PrimeTime (Synopsys) and Tempus (Cadence) both support LVF

The biggest advantage of LVF is that it drives static timing accuracy much closer to MC SPICE, the ultimate benchmark. As a result, it will also produce more accurate slack numbers. On the whole, when compared with OCV, this will improve overall slack as compared with OCV or AOCV.

The graph below shows it. Red is MC SPICE so the goal is to be as close to red as possible. LVF is green and is clearly closer than either OCV or AOCV. LVF’s rich data set enables an STA tool to dramatically improve overall accuracy compared with other approaches relative to MC SPICE.

So, in conclusion, LVF is the clear long-term winner. It will be in full production usage over the course of 2015. It is the most robust solution, and addresses all of the limitations of AOCV. Semiconductor teams that are intent on delivering 16nm, 14nm or 10nm silicon would be well advised to begin investing in an LVF design flow today.

TL;DR Use LVF

Download A Brief Introduction to Liberty Variance Format from CLKda here.

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