Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.

Notes

What’s New in 2011 at Blue Pearl Software

New designer experience, ease of use. Brand new GUI.

Work with RTL to synthesis tools to get best timing in your layout.

GUI – windows 7 and Linux, same look and feel.
–All new in 2011
–Inline help

Blue Pearl Analyze – Linting, race checks,
–Demo: support languages: verilog 1995, 2001, 2005, System Verilog, VHDL 2008
–Read your libraries
–Modules can be grey box or black box
–Clocks can be automatically identified or manually setup
–Schematic view auto generated based on your source code
o Cross probe between RTL and schematic view
o Quick browsing of hierarchy
–About 250 checks are run on the source code
o LInting
o Low power
o Timing constraints
o DFT
o CDC
o Etc
–Visual Verification
o 200K gate design
o Lint, structural checking, CDC analysis, CDC identification,
o Using FlexLM for licensing
o False path, multicycle paths
o Only 45 seconds needed on a laptop
o Faster than others who synthesize to gates, instead of staying at RTL level
o About 10X faster than other approaches (Atrenta)
o Run the tool from the bottom up
o All the CDC unsynched paths are shown in text list, clicking creates a schematic view
o Designer decides what to do with the violations to accept or ignore
o User can filter the messages, warnings, errors (Use rules, patterns, modules, names, severity)

Blue Pearl Create –
–Creates an SDC file automatically
–All false paths are displayed in a tree view and schematic view
–Assertions are shown for each false path
–An audit trail explains why the control values are creating a conflict
–The SDC file will help other tools (STA, Synthesis, ATPG) to reduce their run times
–Can save weeks of time compared to manual SDC constraint generation
–200K design run in minutes
–Customers: Microsoft, KLA, Cypress Technologies

Usage: Block level designs, run on PC or Linux boxes

Users: IC (Constraint generation), FPGA (Help on large designs like Virtex with 10M gates, PC and Windows. Find Clock Gating opportunities), IP (want more tool flexibility)

Version 5.0 (Blue Pearl Software Suite)

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers: single port, multi port, ROM
7 families to choose from

28nm libraries nominal VDD of 1.0V

Processor Optimization Package (POP)
–Physical IP
–Reference flow, documentation, guidelines
–ARM certified benchmarking

Cortex A9 – 1.3GHz performance now

Silicon Validated – created Test Chips for GLOBALFOUNDRIES and Samsung at 32nm and 28nm nodes

Fab Synch – migrate any design from one fab to another one

Ready to Start – http://designstart.arm.com/

Andy Potemski – Director of Global Technical Services, Synopsys

Lynx Design System – About 2 years old, design system of silicon realization tools
–Off the shelf productivity
–A core flow for building an ARM Cortex A9
–Configure Flow with High Performance Libraries and IP
o Use DesignWare or 3[SUP]rd[/SUP] party IP
–Optimize the methodology for design specific needs
–Optimize the design floor plan in the context of the full chip
o Quad core A9 floor plan
o Explore and optimize
–Optimize performance and power
o Detailed routing
o Trend analysis of design metrics like power, area, speed
–Optimize the design flow turn around time
o Track execution of all tools
o Analyze the profile of each tool
o Identify tool bottlenecks

Q: The ARM brochure says up to 25% higher performance or 80% less power. Can I get both?
A: That’s very difficult. It’s really a tradeoff that you have to choose between.

Q: How will work on 28nm help 20nm, especially in light of litho effects?
A: We’re collaborating early in the development of 20nm to learn from our Common Platform partners. Double patterning is needed for 20nm. Expect to see a 50% improvement in density going from 28nm to 20nm node. Computational lithography required on 20nm. Another level of litho complexity make architectural exploration a challenge. Trying to minimize the number of double patterning layers required.

Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.

Notes
2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing
– Post-layout debug

o Tracing – which signal triggered that net that rose or fall?
o Trace back to a Primary input
o Cross-probe between auto-generated Schematic and the waveforms
o Pricing: $50K per year
– ADDS Wave
o Pricing: $2K per year
– PCSim
o Pricing: $25K per year
o Post-layout simulation speed improved, 3X
o True SPICE simulator, flattened
o Compete with HSPICE, SPectre, ELdo

Customers – Ali (Taiwan)
– Extreme DA

Based: Santa Clara, CA

Employees: 10

Next Year: Double revenues

Sales: Direct mostly, some distributors

Summary
ADDS Debugger reminded me a lot of what Concept Engineering has been offering for several years now in a transistor-level debugger. What makes this different is that you’re inside of a circuit simulation run when you can visualize the netlist as a schematic and see the node voltages and branch currents.

The SPICE circuit simulator market is crowded with many EDA vendors (Synopsys, Mentor, Cadence, Magma, Berkeley, Tanner EDA), so Cyber EDA has to do something special in order to make PCSIM stand out from the crowd (speed, accuracy, capacity, features).

Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.

Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)

John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:

Demo – 1.5 million instance design, 1.59 million nets, fully P&R, three libraries
– QCP: Gate Level (Star RC competitor)
– QuickCapNX: 3D field solver (Raphael competitor)
– QCP TX: Transistor Level (RC XT competitor)
– QCP
o 10X faster than Star RC
o 20X faster with multi-corner extraction
o Accuracy: +-2% of QuickCap NX
o TSMC qualified at 28nm
o Inputs: LEF, DEF, GDS II
o Scaling: can add multiple corners using only 20% run time, can be distributed across more boxes
o Capacity: 50M instance designs, memory efficiency
o Accuracy (vs Star RC)
o Example: TSMC 40nm, 38K nets
o 1 corner at 5 hrs, 12 corners at 8.4 hours (27X faster than Star RC), using 3.3GHZ CPU, 148GB and 12 CPUs
o One license per four cores (after that add a multi-core to add up to 32 cores)
o 16 Synopsys licenses for a runtime of 60 minutes, vs 2 licenses in 34 minutes
o ½ the run time, ¾ the HW, 1/8 the licenses (compared to Synopsys with 80% market share)
o 3D on demand (add QuickCap NX), name the nets you want best accuracy on
– Tekton – a STA tool
o Reads SPEFS
o Fast STA in minutes
o Concurrent MM/MC
o Accurate with SPICE integration
– Old flow
o Implement, output a GDS II
o Extract, output SPEF
o STA
– New Flow
o Implement
o QCP and Tekton
– QuickCap NX: Industry Golden 3D Field Solver
o Same run time independent on
o Three methods:
 Finite Element (Slowest)
 Boundary Integral (Slow, what Mentor 3D XACT uses)
 QuickCap (Fastest)
o Field-solver accuracy (within 1% of Silicon)
o Good for library characterization, custom, analog
o Flow Inputs: ITF or iRCS from foundary, GDS II layout
o Industry standard solver at IDMs, Foundries
o Edge effects
o Qualified by TSMC
– QCP TX – transistor level extraction
o Millions of transistor capacity
o To be released in 6 months
o For: Custom design, memory, AMS
o CCI – Calibre Connectivity Interface, stress parameters, well proximity
– QCP Demo
o 18 million nets extracted per hour on 8 threads

Summary
Star RC (Synopsys) has plenty of competition from Magma, Mentor and Cadence for IC extraction. I also learned more about 3D Field Solvers on Tuesday at the Pavilion Panel session.

At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

Greg Curtis – Product Director, Custom Design Business Unit

– Talus for Digital Design
– FineSim does: SPICE, FastSPICE, Characterization
– Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
– What’s New in FineSim?o RF
o TCL circuit checks
– ADC design trendso Parasitics dominate performance now
o Sensitivity to noise and cross talk
o Operating at low power
o Requires more SPICE, more corners, more analysis
– Cell phone trendso 10+ radios per phone
o Maximum battery life
– FineSim SPICEo Multi-cpu and multi-machine capability
o Standard netlist inputs (HPSICE, ELdo, Spectre)
o ER and IR drop analysis
o Co-simulate with Verilog and VHDL
o New:
 Tcl based circuit checks (interactive simulation)• Customized check that you write to check currents, voltages, timing
• Set breakpoints
• Demo: find all outputs above 2.6V
• Demo: At 5th rising edge, wait 25ns, capture signals, check sum of currents, trigger if >50uA used
• Could write Tcl code to calculate the jitter of a PLL real time during simulation
• Technology could traverse a netlist similar to Calibre PERC, but not there yet
 RF Analysis (Harmonic Balance, Periodic AC Analysis, Periodic Noise, Periodic Transfer, Oscillator Phase Noise)• Multi-CPU capability
• Due in November 2011
• Beta in September 2011
• A new option to FineSim SPICE
• Demo of a 9 stage ring oscillatoro One CPU run first, 25 seconds
o Four CPUs run next, 12 seconds
o FineWave used to show the waveform results
o AC wave, phase noise plot shown
 EM/IR Analysis• Titan is being used for EM/IR Analysis
• Demo of NAND gates in a layout and schematic
• Titan uses the Analog Simulation Environment (AVE)
• EM/IR analysis results viewed on top of the layout using color codes, layout zoomed in when clicking on a specific EM/IR result
• Capacity is a few million MOS devices
o 1.5X Faster than Berkeley (PLL)
o 1.4X faster than Cadence APS (Sigma Delta Modulator)
o 5X faster than Eldo
– FineSim PROo Multi-rate engine, hierarchical processing (but not hierarchical simulation)
o Same features as FineSim HSPICE
o Capacity example had only 4.6M devices
o 7.9X to 16X faster than NanoSim, Hsim,XA (under 2M MOS devices)
Improvements:
– 2011.04 release versus 2010.08o 1CPU, 7.5% less memory. 1.23X run time improvement
Foundry Support
– TSMC, GlobalFoundries, TowerJazz, Lfoundry

Customer Usage:
– 12 of top 20 Semiconductor companies using FineSIM
– Analog Bits, 10X speed up wit FineSim
– ESNUG user: 3X to 10X over HSPICE

Anand Ganesan – Senior Product Engineer (demonstrations)

Summary
FineSIM catches up to HSPICE, Eldo and Spectre in simulating RF circuits.

The Tcl Circuit Check looks similar to the technology in Mentor’s Calibre PERC. Let’s see if they create a product to detect ESD best practices like PERC does.