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Why does AT&T Fear OTT?

Why does AT&T Fear OTT?
by Paul McLellan on 05-29-2012 at 9:00 pm

OTT stands for “over the top”. But in the telecom sense it does not mean outrageous, it means providing a service using the data network that competes with some service that the carrier offers and uses as a revenue stream. The most obvious of these is running Skype and so not making a voice call but perhaps the biggest threat is messaging services. After all, young people rarely use their phones for making calls anyway, and even old fogies like me send more and more text messages.

In fact there are over 6 trillion text messages sent per year, according to the ITU (2010 data). That’s 17 billion per day, or 2½ for every person on the planet (including babies and other people who don’t have phones). Retrevo in the UK reported that 10% of young people in Britain think it is OK to send a text message while having sex.

If you have an iPhone and you send a “text” to another iPhone then it will show up in blue not green. This means that in fact you didn’t send a text at all. Apple simply bypassed the carrier and used the data service to transfer whatever you typed. Except to the extent that this uses a miniscule amount of your data cap (which is measured in gigabytes per month) the carrier gets nothing. For a text they get several cents depending on what sort of plan you are on, more if it crosses an international frontier. In the same way, if you use Whatsapp or similar messaging services (Skype, AIM, Blackberry Messenger etc) the carrier is cut out of the loop. It is their worst nightmare, being reduced to a dumb pipe.

Texting is huge. And hugely profitable. How big? Texting is as big as handsets. That’s right, carriers make as much revenue selling text messaging services as they do selling handsets. They make about a quarter of their revenue on the hardware side. Of the remaining $1T in service revenue, 85% comes from voice and text messaging.

But texts require essentially no bandwidth and so have minimal cost. As a result they are very profitable. How profitable: 45% of carrier profits (another 50% comes from voice calls and just 5% from everything else). This is perhaps a bit distorted since handsets are sold at a loss in some countries such as the US, and it is made up on the service revenue, but the bottom line is that nearly half the profits of the network operators (AT&T, Verizon, Sprint, Vodaphone, Orange, China Mobile etc) comes from text messaging.

Here is an interviewfrom a couple of weeks ago with Randal Stephenson, the CEO of AT&T in which he says:“You lie awake at night worrying about what is that which will disrupt your business model. Apple iMessage is a classic example. If you’re using iMessage, you’re not using one of our messaging services, right? That’s disruptive to our messaging revenue stream.”

To make it worse, it turns out that the heaviest users (young people, people who travel a lot, people communicating internationally where text messaging has a premium price) are the most likely to use these services that bypass the carrier. A similar phenomenon happens with voice. Carriers make a lot of their voice profits on international calls, since the rates are outrageous and they don’t even pretend to compete on price. But those are exactly the calls most likely to be bypassed by users switching to Skype instead and creating no revenue at all (for anyone, not even Microsoft who owns Skype these days).

So if people are making fewer voice calls and texting more, and more and more of the texting is bypassing the carriers then how does the system hang together. With next generation LTE networks, there won’t really much of a technical distinction between the carrier’s voice and Skype, or the carrier’s text message and Apple’s iMessage. They are all carried over the same packet switched infrastructure. There will no longer be a separate voice channel and a separate channel for text messages (which were originally only intended for network administration). It is just the billing that is different. The carriers are desperate to find a way to make more money than just providing a data service that smart hardware uses to deliver premium services such as voice in which the carrier doesn’t get a cut.

Since the cost of all the network infrastructure (base stations, backhaul, billing etc) has to be paid for out of carrier revenue, expect data rates to go up a lot and voice/text rates to come down. At least that’s my prediction. And they had better or the carriers won’t be able to afford to (indirectly) buy all those chips that go into smartphones and the base stations to serve them. Or alternatively the carriers will successfully block certain services such as Skype (indeed one carrier in Sweden already excludes use of Skype from their fixed price data bundle).


Intel’s Tri-Gate May Have Moore Problems Than You Think!

Intel’s Tri-Gate May Have Moore Problems Than You Think!
by Daniel Nenni on 05-29-2012 at 7:00 pm


Clever title but it’s not mine. Piper Jaffray Analysts Auguste Richard and Jennifer Baxter released a report last week which echoed the concerns of others, including myself. The concerns reported are with the 22nm process and not the chipsets themselves. To me this is all part of ramping a leading edge process but the concerns are real and should be discussed.

Continue reading “Intel’s Tri-Gate May Have Moore Problems Than You Think!”


SystemVerilog 2012 at DAC

SystemVerilog 2012 at DAC
by Daniel Payne on 05-29-2012 at 3:59 pm

I first met Stuart at Mentor Graphics back in 1995 or so, and he is one of the most knowledgable persons around for all things Verilog.


Stuart Sutherland is the editor for the IEEE 1800 SystemVerilog standard, so if you’re attending DAC and care about SystemVerilog then consider attending the Birds of a Feather meeting held 7 to 8 PM Tuesday evening, room 306.


There will be a presentation summarizing the many significant new features that have been added to SystemVerilog, followed by informal discussion on the importance and proper application of these new features in design and verification projects. The presentation will be by Stuart Sutherland, editor of the IEEE 1800 SystemVerilog standard, and expert trainer of using SystemVerilog. Please invite any SystemVerilog users or tool developers who will be at DAC to attend this session. The DAC link for this meeting is: http://www.dac.com/additional+meetings.aspx?event=355&topic=5


Jasper at DAC: ARM, Broadcom, Nvidia, ST

Jasper at DAC: ARM, Broadcom, Nvidia, ST
by Paul McLellan on 05-28-2012 at 7:01 pm

At DAC (next week, in case you have been under a rock for the last few months) Jasper has four of their customers presenting. Of course they are also presenting themselves making a total of 5 seminars.

nVidia is presenting on Sequential Equivalency Checking for Power Optimization with JasperGold Apps. It is on Monday at 11am, Tuesday at 4pm and Wednesday at 11am.

ST is presenting on Low Power Verification and Optimization with Jasper Formal. It is on Monday at 1pm, Tuesday at 9.30am and Wednesday at 1pm.

Broadcom is presenting on Clock Sensitive FIFO Verification with JasperGold Apps. It is on Monday at 2.30pm (only).

ARM is presenting on Multi-processor Verification Success with Jasper Formal—the Proof is in the ROI. It is on Tuesday at 2pm (only).

Jasper is presenting onAchieving Coverage Closure with Jasper Formal. It is on Monday at 12pm and Wednesday at 10am.

More details on all the seminars are here. Register for any of the seminars here.

On Tuesday as part of the user track, there is a joint presentation with ARM from 12.30pm to 1.30pm in room 105 (on the exhibit floor). The topic is Practical Application of Model Checking – A Taxonomy of Methodologies.

The regular Teens Talk Tech pavilion panel is moderated by Kathryn Kranen, Jasper’s CEO. It is on Wednesday from 3.30-4.15pm. Watch the video (1 minute).

Jasper is in booth 830. Their DAC page is here.


Partitioning Pavilion Panel

Partitioning Pavilion Panel
by Paul McLellan on 05-28-2012 at 6:27 pm

I don’t think it can be a surprise to anyone reading this that designs have been getting larger. Someone called Moore said something about it decades ago, or so I heard. Designs are so large that they need to be partitioned into smaller parts. The two main motivations for this are that some design tools, especially place & route, cannot handle a whole modern design flat, and secondly, it makes sense to split up a design when different parts are being handled by different teams especially if they are geographically dispersed.

Doing the minimum amount of partitioning such that the design can still run through the design flow is one end of the scale. But it may be suboptimum. You may require very long runtimes on your largest servers and more partitioning would result in a faster iteration loop for the slow running steps. Plus the project management may be tricky if you have more design teams than partitions. On the other hand, partitioning down into tiny blocks, perhaps one block per designer, is suboptimal. You always lose something at the boundaries when you partition and so doing it excessively results in losing too much. There is a sense in which you want to run the design as flat as possible and the art comes into deciding just what ‘as flat as possible’ really means. It depends on details of tools, design teams, existing IP, future anticipated re-use, company culture and probably some more things that don’t come to mind right now.

There is a panel session at DAC called Divide and Conquer—Intelligent Partitioning from 1.30pm to 2.15pm on Wednesday June 6th. It is at the DAC Pavilion in the exhibit hall, which is also booth 310. I shall certainly be there.

Wait…I shall certainly be there since I’m the moderator. The panelists are Santosh Santosh of NVIDIA in Santa Clara, Jonathan DeMent from IBM in Austin and Hao Nham from eSilicon in Santa Clara. Their different backgrounds will make for an interesting discussion. IBM and NVIDIA tend to be working on one huge design at a time, whereas eSilicon does dozens a year since they are a fabless ASIC business. We had a conference call a couple of weeks ago and everyone was already off arguing and I had to shut them down so we could discuss the logistics and so that they didn’t use up all the good material before the audience arrived.

The DAC website page about the panel is here.


SpringSoft Update 2012!

SpringSoft Update 2012!
by Daniel Nenni on 05-28-2012 at 6:05 pm

Little known fact, SpringSoft, Inc. is the largest supplier of EDA software in Asia with headquarters in both Hsinchu, Taiwan, and in Silicon Valley, CA. You will be hard pressed to find a company that does not use SpringSoft products and being located right down the street from the top two foundries doesn’t hurt either.
Continue reading “SpringSoft Update 2012!”


Synopsys Update 2012!

Synopsys Update 2012!
by Daniel Nenni on 05-28-2012 at 10:22 am

Synopsys just delivered second quarter 2012 results with improved revenue on a year-over-year basis. Unfortunately operating expenses are said to be out of control. I’m not a stock guy so for more financial information and analysis try the Motley Fool article HERE.

The interesting thing to note is that Synopsys still has a pile of cash, some $800M, so expect more acquisitions in all areas of the business especially IP, in my opinion. The IP business is a clear differentiator for Synopsys and they are running away with it.

You can tell a lot about a company from their DAC plan. Synopsys has gone AMS mobile this year:

Synopsys at DAC 2012
In addition to special events, Synopsys will offer informative presentations and demonstrations of its comprehensive portfolio of integrated system-level, implementation, verification, IP, manufacturing and FPGA solutions. Visit Synopsys at Booth #1130 to learn about the newest solutions available to help enable the next 25 years of innovation. For more information on these special events and all Synopsys’ activities at DAC visit www.synopsys.com/DAC.

Synopsys DAC Events, Monday, June 4, 2012:

  • AMS Verification Luncheon: Boost Productivity Using Synopsys’ AMS Verification Solution

11:30 a.m. – 1:30 p.m., Marriott Hotel, Golden Gate Ballroom, Salon B
Industry leaders from AMD, ARM, GLOBALFOUNDRIES, Micron and NVIDIA share experiences using Synopsys’ AMS verification solutions in some of today’s most challenging designs.

  • IC Compiler Luncheon: Leading the Way to 20nm Design with Synopsys’ IC Compiler™ Software

11:30 a.m. – 1:30 p.m., Marriott Hotel, Golden Gate Ballroom, Salon A
Hear from experts in foundry, processor, wireless and consumer electronics companies, such as STMicroelectronics, GLOBALFOUNDRIES and Samsung, that have successfully met the 20nm design enablement challenge with IC Compiler.

  • Customer Insight Sessions: High-Performance, Gigahertz+ Success with Synopsys’ Galaxy™ Implementation Platform

2:00 p.m. with Samsung and 3:00 p.m. with NVIDIA, Moscone Convention Center East Mezzanine, Room 220
Technical experts will discuss the latest high-performance design trends, challenges and solutions. They’ll share best practices and innovations in high-performance technology that help address Gigascale, Gigahertz+, low power and advanced geometry design challenges.

  • Synopsys’ PrimeTime® Software Special Interest Group 2012 Dinner: Next-generation Hierarchical Timing Technology — HyperScale

6:00 p.m. – 8:30 p.m., Marriott Hotel, Golden Gate Balzlroom, Salon A
At this event, you will see Synopsys’ R&D team unveil the new underlying engines for its hierarchical timing technology, HyperScale. Industry experts will also share their experience with this innovative new technology, which demonstrated up to 10X faster and smaller full-chip timing analysis runs with signoff quality results matching flat analysis. Speakers include timing experts from LSI, NVIDIA, Samsung and Synopsys. The event will be moderated by Brian Bailey of EE Times. PrimeTime Ecosystem Partners will also be there, including ARM, Chip Estimate, eSilicon, Global UniChip Corp., Library Technologies, Nangate, Open-Silicon, Platform Computing, an IBM company, Runtime Design Automation, Samsung, SmartPlay, SpringSoft, Target Compiler Technologies, Univa and Z Circuit.


Synopsys DAC Events, Tuesday, June 5, 2012:

  • ARM, GLOBALFOUNDRIES, Samsung, Synopsys Partner Breakfast: Breaking through Barriers — High-Performance and Energy-Efficient ARM Powered SoCs at 32/28nm and 20nm

7:15 – 8:45 a.m., Marriott Hotel, Golden Gate Ballroom, Salon A
In this session, experts from ARM, GLOBALFOUNDRIES, Samsung and Synopsys will describe key design and manufacturing challenges facing designers at 32/28nm and 20nm and how through collaboration, the companies are addressing these challenges. The collaboration combines semiconductor manufacturing, EDA and IP enablement, shared cycles of learning and silicon proof-points to enable a complete silicon-proven design enablement and manufacturing-ready solution for optimized implementations of ARM Powered high-performance and energy-efficient SoCs.

  • Customer Insight Sessions: High-Performance, Gigahertz+ Success with Synopsys’ Galaxy™ Implementation Platform

10:00 a.m. with Cavium and 2:00 p.m. with Samsung, Moscone Convention Center East Mezzanine, Room 220
Technical experts will discuss the latest high-performance design trends, challenges and solutions. They’ll share best practices and innovations in high-performance technology that help address Gigascale, Gigahertz+, low power and advanced geometry design challenges.

  • Verification Luncheon: SoC Leaders Verify with Synopsys

11:45 a.m. – 1:45 p.m., Marriott Hotel, Golden Gate Ballroom, Salon A
Given the complexity of today’s SoC designs, incremental tool improvements will not be sufficient to deliver the required order-of-magnitude boost to verification productivity. At this luncheon, AMD, Broadcom, Cavium, Freescale, Qualcomm and ST-Ericsson will share their views on what’s driving SoC complexity and how their teams have achieved success. They’ll also discuss the latest developments in verification. The event will be moderated by John Chilton, senior vice president of marketing and strategic development at Synopsys.

  • IPL Alliance Luncheon: Reaping the Benefits of iPDKs

12:00 p.m. – 1:30 p.m., Marriott Hotel, Golden Gate Ballroom, Salon B
At the 6th Annual IPL Luncheon, presenters from multiple foundries will highlight the benefits of the Interoperable PDK (iPDK) standard and their experiences in developing and deploying foundry iPDKs. The IPL Alliance will also present an update on current and future IPL projects.

  • Customer Insight Session: Mixed-Signal SoC Design Success with the IC Compiler Custom Co-Design Solution

4:00 p.m. with STMicroelectronics and Proteus Biomedical, Moscone Convention Center East Mezzanine, Room 220
Attend an informative session on Synopsys’ mixed-signal SoC implementation solution and custom co-design methodology advancements. Learn how leading companies have successfully tackled difficult “big D/little A” mixed-signal physical design challenges using Synopsys’ unified cell-based and custom implementation solution with IC Compiler.


Milestones to Building a Successful Technology Software Company!

Milestones to Building a Successful Technology Software Company!
by Daniel Nenni on 05-27-2012 at 8:30 pm

If you are coming to San Francisco for DAC 2012 and want the best traditional Italian seafood meal visit Scomas. I was just there, the salmon is fresh from right outside the Golden Gate. Have them prepare it anyway you want, you can’t go wrong!

Milestones to Building a Successful Technology Software Company is the first in a series of conversations exploring concepts and best practices for emerging companies. This is a brilliant idea so congratulations to the person who thought of it, uh wait, that would be me. The semiconductor ecosystem desperately needs emerging companies to innovate and solve the many puzzle pieces that we call modern semiconductor design and manufacturing.

Paul McLellan blogged it here: EDAC Emerging Companies: Learn How to Emerge.

The abstract is here: Milestones to Building a Successful Technology Software Company.

Register for the event HERE (it’s free).

Date & Time:
Thursday, May 31[SUP]st[/SUP] 2012
6:00 PM Reception
7:00 PM Emerging Companies Conversation
8:00 PM Q&A

Location:
Silicon Valley Bank
3005 Tasman Drive
Santa Clara, California 95054
Complimentary Parking
(Map)
Ravi Subramanian, Berkeley Design Automation CEO, is one of the speakers. I have had the pleasure of working with Ravi and can tell you he is charming, intelligent, humble, a great communicator, and has the technology pulse of the top semiconductor companies around the world. Just like me, except the humble part.

Ravi has a unique background for EDA, most interestingly, I would bet he is the only EDA CEO who has climbed Mt. Fuji at night. He is certainly the only EDA CEO named to Rutberg & Co’s CTIA Wireless Influencers, a list of the most influential persons in the wireless industry (and he has been on this list since 2007). Ravi also has 17 AMS patents.

I just had lunch with Ravi, he will talk about his experience in building two successful private companies and some of the key lessons he has learned as an entrepreneur. He will cover topics that go from “code to company” as he calls it while citing lessons from his 3G wireless IC startup, Morphics Technology (which he started in 1998), and Berkeley Design Automation, the leader in nanometer mixed-signal IC verification.

Ravi will also cover leadership, product development (both IC and software), customer-focused innovation, hiring, raising capital, innovating in business models, going up against giants, and scaling a company (and scaling a team).

Ravi is not an armchair quarterback, he is in the game and headed for the IPO Bowl! This is a must attend event for all Silicon Valley Entrepreneurs, myself included.


Tanner EDA Update 2012

Tanner EDA Update 2012
by Daniel Nenni on 05-27-2012 at 4:15 pm

Rather than fly to Southern California this week I decided to drive. Airport parking and security, flying to Irvine and renting a car, driving to San Diego and back to Irvine, then flying home is just too much. Call it Porsche therapy, I would rather drive. On the way home I will take the scenic 101 and enjoy the ocean views.

First stop was Tanner EDA in beautiful downtown Monrovia, which reminded me of my hometown Danville. Tanner has a SemiWiki landing page so you can read all about them HERE. I had lunch with John Zuk, VP of Marketing and Greg Lebsack, President. We ate at a great Italian place right down the street where I had one of the best salmon stuffed cannellonis! YUM!

Dr. John Tanner has a very interesting legacy which I will go into with much more detail later but quickly, Tanner EDA first appeared at the 1988 DAC in Anaheim, which was the 25th DAC. John Zuk shared some DAC photos from the Tanner archive which were quite funny. DAC and Tanner EDA sure have changed! Since then the company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries. Wow!

You can tell a lot about an EDA company by their DAC plan. This is definitely the case with Tanner EDA. Tanner EDA will be exhibiting at booth 1126; offering the following Product Demonstrations, and Corporate & Technology Roadmap meetings to interested participants:

Product Demonstrations for Analog Designers:

HiPer Silicon: Tanner’s full-flow analog design suite covers Schematic capture, SPICE simulation, Layout, and Physical Verification. Now including Open Access!
Learn about the latest features and capabilities; including enhanced design collaboration and layout interoperability with Cadence Virtuoso 6 and other Open Access EDA tools.
Click here to make an appointment to attend this product demonstration

HiPer Simulation AFS: Tanner’s latest front-end Design & Simulation offering bolstered by BDA’s FastSPICE capability
See the latest T-Spice and Berkeley Design Automation FastSPICE tools in action; in a cohesive, integrated front-end tool flow.
Click here to make an appointment to attend this product demonstration

HiPer DevGen: A “silicon aware” analog layout acceleration tool that recognizes and generates common structures; an essential tool for high productivity and layout quality.
Learn about this game-changing add-on tool for L-Edit. HiPer DevGen automatically recognizes and generates common structures including:
Differential pairs, Current mirrors, Resistor dividers, and MOSFET arrays
Click here to make an appointment to attend this product demonstration

Product Demonstrations for Mixed-Signal Designers
HiPer Simulation A/MS: Tanner’s latest Analog/Mixed-Signal offering that bridges Analog and Digital Verification.
View a demonstration showing Verilog A and Verilog A/MS within T-Spice integrated with Aldec’s Riviera-PRO simulator.
Click here to make an appointment to attend this product demonstration

HiPer Silicon A/MS: A cohesive Analog/Mixed-Signal flow that bridges Analog and Digital Verification and adds Synthesis, Static Timing and Place & Route.
See Tanner’s latest full-flow mixed signal offering; a highly productive tool flow integrating HiPer Silicon with high performance tools from Aldec and Incentia.
Click here to make an appointment to attend this product demonstration

Product Demonstrations for MEMS Designers
L-Edit MEMS Designer: unsurpassed capabilities and productivity for microelectromechanical systems.
Learn how to reduce time-to-market; watch how L-Edit combines with high-performance add-ins that include curve tools, DXF import/export and design rule checking (DRC).
Click here to make an appointment to attend this product demonstration

MEMS 3D Solid Modeler – a powerful and easy-to-use 3D viewing tool.
Learn about this latest offering – powered by SoftMEMS – that creates a 3D view of a MEMS device from a selected layout area and fabrication process description.
Click here to make an appointment to attend this product demonstration

Corporate and Technology Roadmaps
Tanner EDA: 25 Years of Productivity, Price-Performance and Customer Care
Want to learn more about Tanner EDA business and Technology strategy? Find out about our history, learn about some of our customers’ success stories, and get an opportunity to see what’s in store for the future.
Click here to make an appointment to attend this session

PDKs: An Essential Element of Analog Design Success
Process Design Kits (PDKs) are a critical enabler for design enablement and productive workflow. Learn about Tanner’s latest PDK and design flow initiatives; including foundry-certified kits from Dongbu HiTek, TowerJazz, and X-Fab.
Click here to make an appointment to attend this session

Tanner EDA has a rich history and a very strong story for affordable AMS design. Read about the recent integration with Berkeley Design Automation Analog FastSpice and the Aldec Verilog A simulator. Lots of things going on so be sure and make the time to visit them at DAC 2012. Better yet, download their tools for a free 30 day test drive!


Chip in the Clouds – “Precipitation”

Chip in the Clouds – “Precipitation”
by Kalar Rajendiran on 05-27-2012 at 3:34 am

Since around the posting of my prior blog [Chip in the Clouds – “Gathering”] to now many events have taken place. Facebook announced its intent to acquire Instagram for $1B in cash and stock, completed its initial public offering, announced an Instagram competitive product by releasing “Facebook Camera” and has been busy addressing the question of whether it disclosed material information about its near term earnings selectively to certain institutional investors. What do these Facebook related events have anything to do with cloud-based chip design? At the surface it looks like nothing and therein lays a major issue.

Facebook or Google, Instagram or Facebook Camera, Google+ or for that matter any internet-based social-media offering cannot work without one important component and that is the semiconductor chip running the computers and server farms that power these social-media platforms and apps. A great majority of the population does not know and/or does not consciously think about this. What would happen if the semiconductor industry goes on strike for a month? This will not happen and neither am I suggesting it but just imagine the impact to the social-media world and the rest of the world if this were to happen. In spite of this key role, semiconductor companies do not receive anywhere close to the relative valuations that social-media companies are receiving. Instagram received a billion dollar valuation after taking in just millions of dollars over a 2-year period to produce an app that allows a user to add effects to photos. Compare that to the billions of dollars that go into the semiconductor industry and the little things that are output (I’m speaking figuratively about the micro sized chips that are produced and literally about the relatively tiny valuations semiconductor companies receive).

As newer complex chips are being designed and produced, the cost to develop these chips has increased multi-fold but the size of the average funding rounds has remained about the same as it was many years ago. Investing in semiconductor companies has become too risky even for VCs. VCs are now able to make smaller investment rounds in social-media companies and see success/failure in a shorter time interval compared to a semiconductor investment.

But that does not mean innovation in semiconductors will come to a halt. Nor does this mean that the semiconductor industry is facing death. But it is true that the industry is going through a serious ailment. Venture capital funding has slowed down to a trickle. In spite of this, as the famous phrase “Life will find a way,” from the movie Jurassic Park, the semiconductor industry will find a way out of this ailment. This is the industry that has been most innovative over its 60-year history in terms of technology as well as its cost-reduction delivery.

Innovative companies have been doing their part to help semiconductor companies deal with the ailment and continue to deliver great new products that benefit the world. The value chain producer model helped chip companies avoid a large portion of their fixed cost investment without sacrificing their ability to design and deliver cutting-edge innovative products. Marseille is utilizing a proprietary Virtual silicon design methodology/technology to rapidly prototype products before committing to silicon thus mitigating silicon respin risks and accelerating time to market for its customers. Marseille could help the industry by licensing this technology to other semiconductor companies who it does not compete with.

SiCAD
as a cloud-based silicon design company will allow its customers the ability to extend the EDA tools and IT budgets at the same time enhancing their ability to bring products to market faster. Customers don’t like feeling captive to any supplier. With the recent consolidations in the EDA world, the time is ripe for customers to demand a heterogeneous cloud-based silicon design platform. Chip in the clouds precipitation has begun. Expect the downpour to continue. Hear directly from customers and suppliers by attending the DAC 2012 panel “Is EDA in the Cloud Just Pie in the Sky?” hosted by Nitin Deo on June 6, 2012 at 1:30pm at the Moscone Convention Center.http://www.linkedin.com/in/kalarrajendiran