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100 USB 3.0 IP Design-In…Is PLDA rocketing SuperSpeed USB technology?

100 USB 3.0 IP Design-In…Is PLDA rocketing SuperSpeed USB technology?
by Eric Esteve on 11-29-2011 at 10:19 am
Categories: IP

Did we (the analyst) completely underestimate SuperSpeed USB take-off, or is the company tweaking the meaning of “USB 3.0 IP Design-In”? This PRfrom PLDA could be understood as a claiming from the IP vendor that they have achieved the 100[SUP]th[/SUP] design win for their USB 3.0 IP… Let’s try to understand how PLDA can make more design win than the Total Available Market for SuperSpeed IP.

In fact, as an analyst providing “USB 3.0 IP Market Forecast”, I feel very uncomfortable, as the cumulated forecast for 2009, 2010 and 2011 gives 12 + 20 + 59, or 91 ASIC design starts including USB 3.0 IP (sold by an IP vendor). IPNEST thinks we will see Smartphone and Media Tablet supporting USB 3.0 on the market as soon as next year, that USB 3.0 enabled external HDD and SSD are shipping now, and that there will be a second wave of consumer electronics devices to transition, namely the Digital TV, Set-Top-Box, Blue Ray Players to ship in 2012-2013. This means IP sales starting now and continuing in 2012 to allow for a minimum development time. In fact we have built a forecast for USB 3.0 IP sales based on a bottom-up analysis, looking at the different application in every market segment which could transition to USB 3.0, and even more important, we have tried to determine when the IP sales will happen, application by application. The result is a very complete 50 pages document, where you can find this type of information, like the design start evaluation (generating USB 3.0 IP sales) up to 2015:

The first point is that PLDA is not the only vendor selling this IP: Arasan, Evatronix, Faraday, Inventure, NEC (now Renesas), Synopsys and Snowbush are all active on this market. Even if the forecast is wrong by 10% (yes, this can happen!), it’s not possible to see a single company enjoying 100% market share. Especially when reminding that Synopsys has claimed a few weeks ago that they have made 40 USB 3.0 IP design wins, which is rather realistic. First outcome of this investigation; PLDA “design win” does not mean sales of a USB 3.0 IP linked with an ASIC design start. Looks like some design win are for potatoes, when some other are like counting tomatoes. Next question is; which is tomato, which is potato!

Going further in PLDA’ PR, you read that the company is marketing USB 3.0 IP under different form:

  • USB 3.0 Host and Device controller IP for implementation in ASIC,
  • USB 3.0 Device controller IP for implementation in FPGA,
  • USB 3.0 Development boards and kits based on Altera and Xilinx FPGA

Potatoes could be USB 3.0 IP for implementation in ASIC, and tomatoes for implementation in FPGA? Unfortunately not! SuperSpeed USB is a protocol addressing market segment like PC peripheral (External HDD or SSD…), Consumer Electronic (Video Camera…) or Wireless Handset (Smartphone), at least for the time being, until a wider pervasion of the protocol occurs in other segments. Considering the targeted production volumes (several million of units), none of these Application could afford the high ASP value for FPGA devices. We could imagine a scenario where the chip maker decide to validate the concept by targeting a FPGA implementation first, this strategy make sense and is used by chipmakers. But, in this case, they tend to use exactly the same IP than for the ASIC implementation. This would not generate 50 “tomato” design win, as it would mean that PLDA has made 50 “potato” (ASIC) design wins as well, which is very doubtful: how could the challenger in USB 3.0, who was not present on the USB IP market so far could do better than the historical leader? So, the answer is: neither potato, neither tomato! Next question is: what is the vegetable hidden in these 100 design wins?

SuperUSBV6-550 USB 3.0 Development Kit from PLDA

SuperUSBC3-55USB 3.0 Development Kit from PLDA

As I did not want to provide Semiwiki readers with corrupted information, based on my own guess, I simply have asked to PLDA. The vast majority of these 100 design wins have been made by selling FPGA based boards! Because PLDA ‘ Superspeed Controller IP was implemented into the FPGA, PLDA could claim that they have sold, not only the Xilinx or Altera based board, but also the USB 3.0 IP. Every board sale is counting as a design win for the IP! Which is true, when you consider that the customer buying the board could “play” with PLDA’s IP, and interconnect it with his own design. In that sense, PLDA is doing USB 3.0 evangelization. The drawback is that the revenue generated by one of these design wins is in the few $K, when the revenue generated by a SuperSpeed Controller source code IP is in the few $100K! So, it’s likely that these 100 design wins generate far less money than the 40 design wins from Synopsys… The comparison was between potatoes and tomatoes, but the latest was a USB 3.0 enabled FPGA board, not a USB 3.0 IP license for FPGA implementation, the potato still being a SuperSpeed USB IP license for ASIC implementation.

Eric Esteve from IPNEST – Table of Content for “USB 3.0 IP Forecast 2011-2015” available here

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Blitz, blazing fast layout

Blitz, blazing fast layout
by Paul McLellan on 11-29-2011 at 8:00 am
Categories: Uncategorized
1 Comment

One of the challenges with today’s SoCs is that chip-finishing, putting the final touches to the SoC working at the chip level, stresses layout editors to the limit. Either they run out of capacity to load the entire chip, or they can handle the entire chip but everything is like wading through molasses, it takes an awfully long time to get anything done.

As a result there are a number of chip viewer tools that focus just on being able to load the SoC and very fast to display. The problem with these is that editing capabilities are either non-existent, it is strictly a viewer, or extremely limited.

Laker’s Blitz is a tool that brings the best of both worlds. It can handle extremely large designs and is between 5 and 20 times faster than regular layout editors. However, it has most of the editing features that regular layout editors have since it is built on top of Laker Custom Layout. It has the same user-interface, same basic editing, same in-memory schema, same integration with DRC/LVS, and the same Tcl extensions.

Blitz is optimized for chip-level operations on very large chips, basically reading GDS, editing, and then writing the GDS back out again. The four big tasks it has been optimized for are:

  • Chip-finishing: chip-level review, editing, assembly and debugging
  • IP merging: replacing IP black-boxes with physical layout
  • SoC assembly and review: assemble IP blocks, trace critical nets, verify and fix boundary DRC errors
  • DRC review and repair: chip-level signoff DRC

Of course not every single thing that you can do in Laker Custom Layout is supported, otherwise it would make no sense to have two tools. In particular, Laker Blitz is 64-bit only, it cannot create or modify Pcells and so on. It is focused strictly on the typical tasks done at the chip level with today’s advanced technology node SoCs.


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Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?

Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?
by Ed McKernan on 11-29-2011 at 12:07 am
Categories: General

What if Amazon’s new Kindle Fire, priced at $199 and using a sub $10 TI processor, has effectively started the ball rolling towards forcing Intel and AMD to building a Very Low Cost (perhaps even <$10) x86 mobile processor? A recent article entitled “Amazon’s Risky Strategy” explores the ramifications of Amazon selling Kindle Fires at a loss in order to get eyeballs stuck on Amazon’s web pages for longer and thereby increasing sales. The article goes on to speculate that Amazon will sell a Smartphone in the future to further its strategy. Amazon’s sub $200 subsidized hardware model may be like a magnet pulling mobile PC’s into its price range which would have an impact on x86 CPU features, power and price.
Continue reading “Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?”

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A Review of an Analog Layout Tool called HiPer DevGen

A Review of an Analog Layout Tool called HiPer DevGen
by Daniel Payne on 11-28-2011 at 1:11 pm
Categories: EDA, Tanner EDA

My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I learned. This technology came from IC Mask, a Dublin-based services and training company.
Continue reading “A Review of an Analog Layout Tool called HiPer DevGen”

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GlobalFoundries Versus Samsung!

GlobalFoundries Versus Samsung!
by Daniel Nenni on 11-27-2011 at 7:00 pm
Categories: Foundries, GlobalFoundries, TSMC

Some call it co-opetition (collaborative competition), some call it keeping your enemies close. Others call it for what it is, unfair competition and/or other types of legally actionable behavior. GlobalFoundries calls it“Fab Syncing”, which in reality will SINK their FABS!

“With this new collaboration, we are making one of the industry’s strongest manufacturing partnerships even stronger, while giving customers another platform to drive innovation in mobile technology. Customers using this new offering will gain accelerated time to volume production and assurance of supply, and they will be able to leverage significant learning from the foundry industry’s first high-volume ramp of HKMG technology at 32nm in H1 2011,” said Jim Kupec, senior vice president of worldwide sales and marketing at Globalfoundries.

Unfortunately Jim Kupec no longer works for GlobalFoundries and Samsung may be one of the reasons why. In 2010 Globalfoundries and Samsung Electronics said they would synchronize global semiconductor fabrication facilities to produce chips based on a gate-first implementation of 28nm HKMG technology. They will do the same at 20nm switching to Gate-last HKMG. As a result, Globalfoundries and Samsung will be able to make 28nm and 20nm chips for the SAME customers?!?!?!? Putting aside the gritty technical details, what this means is that GFI will have to compete not only with superpower TSMC, but also their PARTNER Samsung. Samsung is not only the second largest semiconductor company, Samsung is also one of the most fiercely competitive companies in the world. Is that really a good idea?

As it turns out it was a very bad idea for a number of reasons. First and foremost is yield. Samsung is the only “Fab Syncing” partner yielding at 28nm Gate-First HKMG (IBM and GFI are not). Remember Samsung is the largest memory maker so they know how to ramp yield quickly at any node. Are they sharing that manufacturing expertise with GFI and other Common Platform members? Not now, not ever. Samsung is aggressively targeting TSMC and GFI 28nm top customers including AMD, Nvidia, Qualcomm, Broadcom, Marvell, and Xilinx.

Cost and delivery are the key components of a wafer manufacturing contract and Samsung is an expert in both areas. Especially since margins for the Samsung foundry business are not broken out so they could literally dump wafers to get market share. TSMC on the other hand has the biggest wafer margins in the industry which they could cut in half and still make money.

The Samsung cut throat culture is inside the company as well. Multiple Samsung groups compete for a given market. Samsung has phones and tablets based on Nvidia, Qualcomm, and TI processors as well as having their own ARM based processors. They compete in the same way with their largest customer Apple. Apple will purchase close to eightBILLION dollars in parts from Samsung for the iSeries of products this year alone, making Apple Samsung’s largest customer. Samsung is also Apple’s largest competitor and now they are engaged in a mega legal battle which will literally change the face of consumer electronics, believe it.

Even the marketing guys are mixing it up with Samsung firing the first shot:

I’m looking forward to Apple’s response and the Samsung response to that etc…

Let’s not forget the Samsung corruption scandalthat engulfed the government of South Korea. Let’s not forget the chip dumping probes. The book “Think Samsung” by ex-Samsung legal counsel accuses Samsung of being the most corrupt company in Asia.

This battle will be bloody entertaining to say the least! Not so much for GFI though, or the other second source foundries as they see already thinning margins get thinner. For us consumers however it means two things: Semiconductor manufacturing innovation and CHEAP CHIPS! w00t!

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Did Apple Influence AMD’s TSMC Foundry Switch?

Did Apple Influence AMD’s TSMC Foundry Switch?
by Ed McKernan on 11-27-2011 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC

During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3 due in 2012 highlight the extent to Apple’s involvement in design and investment to guarantee supply at a much reduced cost so that competitors are left gasping. Turning to the processor world, we know Apple has selected TSMC to Fab their 28nm A6 processor. Why not pull AMD into the Apple-TSMC supply chain ecosystem in order to outmaneuver the raft of Intel based Ultrabook PCs that are headed to the market in 2012?

Continue reading “Did Apple Influence AMD’s TSMC Foundry Switch?”

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December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 11-24-2011 at 9:57 am
Categories: EDA, Siemens EDA

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better than Cure: DRC/DFM Inside of P&R
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools

If you want some hands-on time with the Calibre tools then consider attending the December 1st workshop in Fremont, California.

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AMD’s Crossing of the Chasm

AMD’s Crossing of the Chasm
by Ed McKernan on 11-24-2011 at 6:00 am
Categories: General, Intel Foundry

When AMD announced its cutbacks recently many people were left wondering why they were so deep given the strong financial performance in Q3 and the guidance for an up Q4. It couldn’t have been related to the Thailand floods that could have been at most a one-quarter squeeze expected in Q1. Now it is apparent from reports that AMD’s cutbacks were based on the cancelling of its 28nm APUs at Global Foundries and the time required to move to TSMC. The change will significantly delay new APU (CPU+graphics) offerings to address the low cost and “ultrabook” markets. Many companies, especially startups, choose a path that leads to Crossing a Chasm in order to be successful. Since Dirk Meyer’s exit at the beginning of the year, market forces and trends for 2012 are requiring that AMD enter a startup mentality mode and thus have to Cross a Chasm not of its own volition.
Continue reading “AMD’s Crossing of the Chasm”

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What happens in Las Vegas Gets Blogged on SemiWiki!

What happens in Las Vegas Gets Blogged on SemiWiki!
by Daniel Nenni on 11-23-2011 at 7:00 pm
Categories: General

Interesting story, for my wife’s 50th birthday we went to Las Vegas to see Sir Elton John in concert. My wife is an Elton fan and this may be her last chance to see him live so off we went. I saw Elton and Billy Joel in a dueling piano concert a while back and it was simply amazing! The underlying purpose of the trip however was to earn “Perfect Husband Points” (PHP’s), which can then be traded in for sailing trips in Mexico etc… Right now I’m saving up for a trip to Spain to run with the bulls.

When we checked in ( Caesar’s Palace Las Vegas ) the desk lady asked us which part of the hotel we would like to stay in. We could be near the registration desk for convenience, or we could be near the topless pool, or be near the chapels. Without hesitation, I said near the chapels please (+1,000 PHP’s). Okay, I may have hesitated briefly, but come on, who knew there would be a topless pool!

After getting settled in our suite (500+ PHP’s) we took a walk around the hotel and stopped by the chapels to see what a wedding at Caesar’s is all about. There were three chapels one large, one medium, and one small, all very beautiful! The wedding coordinator told us that a marriage renewal costs $350.00 and included a quick service in the small chapel and a decorative certificate. So I got down on one knee and asked my wife to marry me again (+5000 PHPs) and luckily she said yes.

The wedding coordinator then told us that a deluxe wedding had just cancelled and if we could be ready at 6pm (1+ hour) we could have it for the $350.00 price we already agreed to! Such a deal! The large chapel, flowers, champagne, pictures, all inclusive, how could we pass that up! (+1000 PHP’s)

Strangely enough we were both nervous even after being together for 30+ years. Even stranger, she did not cry at our first wedding but she cried tears of joy at this one as the picture shows. I didn’t cry, probably because I was more focused on the honeymoon part. We even bought a new ring for me which I have not taken off since (+2000 PHP’s).

The Elton John “Million Dollar Piano” concert was outstanding, he is still quite the showman. His piano probably cost a million dollars, thus the name. The piano was four years in the making, is covered with 68 LED screens, and weighs 3,200 pounds! The piano lit up with color and imagery to reflect the theme of each song, it was amazing! Such technology! Brought to you by the semiconductor design and manufacturing ecosystem!

The other technology that was glaring in our faces were the smartphones that people held up to take pictures and video of the event. Of course we were constantly reminded that photos and video were NOT allowed but the majority of people did it anyway. Another example of smartphone inspired anarchy!

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How to use NoC to avoid routing congestion

How to use NoC to avoid routing congestion
by Eric Esteve on 11-23-2011 at 5:21 am
Categories: Arteris, EDA, IP

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a “public transportation” sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on “application-specific NoC topology synthesis”.

An interesting white paper from Arteris: “Routing Congestion: The Growing Cost of Wires in Systems-on-Chip” demonstrates how you can drastically reduce routing congestion by using a NoC. On this picture, you can see on the left part, the routing congestion areas, highlighted through a color code (purple= very strong congestion, red=strong congestion, yellow=medium, blue=no congestion), this will sounds familiar to anybody who has already used a floor planning tool. According with Jonah Probell: “…in the process of chip design, more can be done to improve P&R wire congestion by reducing the number of wires in the IP RTL before synthesis.”

For those like me who have used floor planning tools in the mid 90’s, to help customers to release to layout the RTL version of a chip with good chance to complete the lay out phase within a decent time period (say, a couple of weeks, as these chips were designed into a supercomputer, using the largest available BiCMOS base array, running at the highest possible internal frequency, which makes sense when you design a supercomputer…), it was common to spend weeks if not MONTHS to optimize the floor plan of the IC. I realize now that having the opportunity to use a NoC at that time would certainly help us to, either reduce the design cycle (thus the Time To Market for our customer, as well as the time spent by TI FAE team), either go higher in frequency, and help our customer to launch a more powerful product. I strongly encourage anybody involved (or interested) by on the edge SoC design techniques to download this paper from Arteris here.

Eric Esteve from IPNEST