SemiWiki – Page 987 – The Open Forum for Semiconductor Professionals

August 23, 2011June 14, 2019

Silicon One

Silicon One
by Paul McLellan on 08-23-2011 at 5:23 pm
Categories: Uncategorized

I have talked quite a bit over the last few years about how the trend towards small consumer devices with very fast ramp times. For example, pretty much any time Apple introduces a new product line (iPod, iPhone, iPad…) it becomes the fastest growing market in history. This has major implications for semiconductor design since the heart of these devices is semiconductors and software that runs inside them. The pace only keeps accelerating.

So what are the characteristics of this environment?

semiconductor manufacturers have been very successful at delivering more technology, more performance, faster time to market, resulting in products that do more and in demand for…well, more
lifestyles drive technology as customers want more connectivity, more performance, more integration
the future is a convergence of digital, analog, memory, 3D packaging and software. Pure digital SoCs are less and less common since the real world is analog. 3D packaging (package-in-package, TSV etc) are coming important
competitive markets with shorter and shorter product lifecycles
design tools get more powerful, more integrated, take account of higher-level aspects of designs to drive productivity, and lower level aspects of design to guarantee functionality and yield.

Magma’s Silicon One inititative is focused on making silicon profitable for their customers. It acknowledges that one EDA vendor cannot supply every tool required. Magma has five key technologies to address the main business challenges: time to market, product differentiation, cost, power and performance. Those five are Talus, Tekton, Titan, FineSim and Excalibur. These all work off a unified database for designing these complex chips that combine analog, digital, memory in a single chip.

Like the parable of the blind men and the elephant, each feeling a different part, people view Magma differently depending on their experience. Some view Magma as industry leaders in the classical RTL to GDSII flow. others view Magma as having one of the most sophisticated analog/mixed-signal (AMS) solutions.

Both these groups may be surprised that Magma holds a strong position in the design of memory devices such as Flash, SRAM, DRAM and image sensors (yes, these aren’t technically memory but they are treated as so due to their attributes). Magma tools are used by the top 5 memory companies.

Perhaps more surprising is that Magma is a major player in yield management with a large installed base in amost every fab on the planet, but this is known mainly to just the customers who use this solution.

The Magma white paper on Silicon One is here.

August 22, 2011June 14, 2019

Cadence Verification IP Technical Seminar!

Cadence Verification IP Technical Seminar!
by Daniel Nenni on 08-22-2011 at 11:43 am
Categories: Cadence, IP

According to trusted sources it costs upwards of $50M to design a 40nm SoC down to the GDS. Semiconductor IP is a fast growing part of that equation and functional verification of that IP is critical. Hardware complexity growth continues to follow Moore’s Law but verification complexity is even more challenging. In fact, IP verification is widely acknowledged as the major bottleneck in SoC design. Up to 70 percent of the design development time and resources are spent on functional verification. Even with such a significant amount of effort and resources being applied to verification, functional bugs are still the number one cause of multi million dollar silicon re-spins.

Cadence Verification IP Catalog Technical Seminar
Join us for an in-depth look at Cadence Verification IP Catalog. In this seminar we will hear case studies from experts in the field addressing your most challenging issues when it comes to verifying today’s most important interfaces such as AMBA4 ACE, PCIe Gen 3, USB 3.0, DDR4 and more.

Case studies will focus on real world scenarios and be interactive in nature. In this seminar you will also hear how Cadence with Denali offers the most comprehensive, flexible and open solution on the market for verifying and integrating IP.

August 25, 2011 – Cadence Design Systems (San Jose – Bldg 10 Auditorium), San Jose, CA
1:00 PM – 4:15 PM Pacific

Agenda

August 21, 2011June 14, 2019

WikiLeaks: Methodics vs IC Manage

WikiLeaks: Methodics vs IC Manage
by Daniel Nenni on 08-21-2011 at 4:00 pm
Categories: EDA

Human nature never ceases to amaze me. I understand the recent economic turmoil and looming National Debt has thrown us for a loop but please, let us all get some perspective here and in the words of Rodney King, “Can we all get along?”

A clever little scumbag recently registered the domain danielnenni.com and is now hawking event tickets in my name. I let the domain expire after moving my blogging to SemiWiki. Shame on me for being too cheap to protect my legal name. Daniel Nenni is not a trademark so this is a case of identity theft. Life is short so I will probably just let it go but still, not a good sign of the human condition.

Even worse is the dispute between Methodics and IC Manage. A discussion on SemiWiki started on June 30[SUP]th[/SUP] with the screen shot above. You can visit the thread HEREbut let me summarize. Apparently someone, who chose to hide their identity, registered the domain www.methodics.comand put up the message that the web page is no longer active, the company is no longer in business, and listed IC Manage as an alternative source. IC Manage and Methodics DA compete in the design data management business. The official Methodics response is HERE.

As a grand finale, last week I got this email from Mike Sottak. Mike is a long time EDA PR guy who I have worked with in the past. Mike has always proved to be a solid guy so I have no problem posting his email. I must also mention that SemiWiki works with another competitor to IC Manage and Methodics which is ClioSoft.

You may be aware of the recent shenanigans perpetrated against the design data management company Methodics. It seems the domain name www.methodics.com (which Methodics does not currently own) was set up to point visitors to the web site of their competitor IC Manage. The blatant attempt to confuse customers went so far at one point as to suggest Methodics was no longer in business. While there was little doubt that IC Manage was behind this, it wasn’t until Methodics initiated something called a Uniform Domain Name Dispute Resolution complaint with the World Intellectual Property Organization that the smoking gun was revealed. WIPO confirmed the previously-hidden registrant/owner of the domain is indeed the Vice President of ICManage.

Full disclosure: Methodics is a client of mine. But this incident strikes a personal chord with me as someone who has worked in the EDA industry for more than 20 years. They did not ask that I write to you on their behalf. I do so because I have not seen a more offensive act of malicious and unethical tactics in my career (and many of you will recall that I was at Cadence during the infamous Avanti trade secret theft case). We as an industry often get criticized for being immature and self-defeating. It’s not hard to understand why customers and other people on the periphery of EDA would think that given this type of behavior. The fact that Shiv Shikand has the arrogance to register the domain name that rightly belongs to his main competitor IN HIS OWN NAME sets a new standard for disregard of business ethics.

So why should you care? I believe that part of the role of any press or media outlet is to help police the areas they cover by holding people, companies and other institutions accountable for their actions. I therefore urge you as a key influencer of our industry to call IC Manage to the carpet on this one. I am certain that if a similar situation occurred between Synopsys, Mentor or Cadence, you would do the appropriate reporting and analysis.

I can assure you that Methodics is not interested in this purely as PR stunt, and in fact would prefer that the whole issue go away and the domain name be rightfully transferred to them. But they have been violated in no uncertain terms and have been unfairly been taken advantage of by an unscrupulous competitor. If you are in any way involved with EDA, I believe this type of behavior must be exposed for what it is. Or do we continue to look the other way and condone it through our silence, perpetuating the image of an industry that is immature and risky with which to do business?

Kind regards

Mike Sottak
Wired Island PR

Below is the report from WIPO:

<methodics.com>
Notice of Change in Registrant Information
Dear Complainant,

Further to our Acknowledgment of Receipt of Complaint, please be advised of
the following:

The registrant of the disputed domain name in the above referenced
proceeding has been identified by the concerned Registrar, Blue Razor
Domains, as being different to the entity named in the Complaint as
Respondent. The registrant information we have received from the Registrar
is as follows:

Registrant:
Shiv Sikand
15729 Los Gatos Blvd
Suite 100
Los Gatos, CA 95032
United States

Administrative Contact:
Sikand, Shiv shiv@icmanage.com
15729 Los Gatos Blvd
Suite 100
Los Gatos, CA 95032
United States
+1.4083588191

Technical Contact:
Sikand, Shiv shiv@icmanage.com
15729 Los Gatos Blvd
Suite 100
Los Gatos, CA 95032
United States
+1.4083588191

Setting the legalities of this situation aside, If this story is true, morally and ethically this is just WRONG!I have seen a lot of dirty deeds in my 25+ years in EDA but this absolutely takes the prize! Please voice your opinion in the comment section and I will make sure they get to IC Manage. If you have disputing data please send it to me and I will include it in this post.

Again, I’m biased. I had coffee with Shiv Sikand to try and smooth things over after he attacked SemiWiki on a LinkedIn group when we started working with his competitor ClioSoft. We ended up yelling at each other in a Peet’s Coffee, Shiv and his company IC Manage are still banned from SemiWiki.

*** Shiv had posted a response HERE but it has since been taken down. It was probably one of the worst apologies I have seen.

August 21, 2011June 14, 2019

Apple Will Nudge Prices Down in 2012: PC Market Will Collapse

Apple Will Nudge Prices Down in 2012: PC Market Will Collapse
by Ed McKernan on 08-21-2011 at 7:10 am
Categories: Foundries, Intel Foundry

Jack Welch, the former CEO of GE, had an edict that each business unit needed to be #1 or #2 in the market or else he sold it off. HP is #1 in PC market share but it is exiting a business that it no longer can control and soon will bleed a lot of cash. HP’s Operating margin is under 6% and falling while Apple’s is at 40% and growing. So the question I have been thinking about is: if Apple were to cut prices on iPADs $50 and MAC Air’s by $100 would the PC industry collapse?

The question goes to the heart of demand elasticity and consumer preference. We know that a large portion of the PC market has been required to remain windows due to legacy applications – just as the IBM mainframe continues to satisfy a portion of the Fortune 500 customer needs. But Apple at less than 6% of the worldwide PC market is in position to cause it to flip in 2012.

The firm NPD, which tracks PC sales through retail in the US has stated as of May 2011 that the iPAD is not cannibalizing the PC. But this may be because the iPAD had not ramped sufficiently. During the earnings call, HP’s CEO stated that the iPAD was having an effect on its consumer business. Perhaps there’s more.

The average notebook PC price in retail as of December 2010 was $453. NPD at the time remarked that the under $500 PC was growing while the $500 to $1000 PC was dropping. The over $1000 PC in retail was dominated by Apple with a 91% share.

So if Dell is at a 2.5% operating margin in its consumer business then it is making around $12 per notebook unit sold. Now if Apple lowers its iPAD and MAC Air by $449 and $899 respectively, will it cause Dell and HP to drop prices by $12 or more, effectively ending their consumer business. All appearances are the answer is yes. Or another way to think about it is that since Apple’s move with into retail with iPad and MAC Air, the PC market has lost elasticity.

But the problem must go beyond the consumer and into the corporate world for HP to exit the business. Dell reported that it has a 10-11% operating margin in the corporate world, which is still frightening. I presume HP’s is the same. So I think what the CEO of HP was communicating is that the corporate world is asking Dell and HP to sharpen their pencils for 2012 which will result in price cuts that put their whole PC business at risk of going in the red. Apple has entered the mix.

It is clear that Apple’s strategy has been to take over the consumer retail channel first and we have seen that the growth rates in this segment alone have taxed their ability to meet high demand. However, once this demand is satisfied and the brand is shown to be bullet proof, Apple can turn on the corporate world which is several times larger than retail.

For Apple to win corporate, I think it will require volume deals that are within $50 of the current iPAD price and a $100 from their current notebook price. The $100 discount will effectively cause Dell to go to 0% operating margin if you assume a $1,000 corporate notebook price. And Apple has a way of giving corporations a $100 price break without cutting margins. They will turn around to Intel and ask for a slightly slower processor at a $50 discount (so call it a 2.2GHz mobile i5 processor in place of the current 2.3GHz). A $50 CPU discount = $100 system price discount while effectively occurring at a 50% margin.

Intel faces a dilemma, because corporate is where they rule and giving into Apple will mean the loss of control they have over HP and Dell and their resulting pricing model. Long term though, they have to play the game because Apple is driving the bus and to not acquiesce to Apple is to give AMD an opportunity to respond. Also, on the up side, one of the benefits of Apple taking corporate is the elimination of the Microsoft Windows Corporate O/S tax that is over $100 per unit. Microsoft will be forced to respond to corporations request for price cuts in a significant way. So Apple’s corporate plan can have a significant, immediate impact on Microsoft.

The PC game, which used to be so staid, is getting very complex and master chess players are required to win this battle. Apple has the upper hand. Intel has to figure out how to maintain revenue growth as processor ASPs drop in the mobile space, though rise in the x86 servers building out the Cloud. Part of their plan is to feast off of the decline of AMD and nVidia – unless AMD and nVidia can merge (see Captain Ahab Calls Out for the Merger of nVidia and AMD).

The PC market, as we know it, is collapsing and it is in the hands of a company that until this year was not even #1 or #2. Sounds like its time for Jack Welch to write a new business book.

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August 19, 2011June 14, 2019

HP, Palm, tablets, PCs, smartphones

HP, Palm, tablets, PCs, smartphones
by Paul McLellan on 08-19-2011 at 2:54 pm
Categories: General

Hewlett-Packard purchased Palm last year for over a billion dollars primarily to get their hands on the WebOS operating system for powering its tablets and smartphones. It’s turned out to be much too little too late. Despite WebOS being a new operating system with many attractive features, HP’s tablet offering, the TouchPad, has been a major bust, selling in the hundreds and leaving major retailers complaining about their inventory and wanting HP to take it back. So HP announced yesterday that it was getting out of the tablet and smartphone business. WebOS may find a home (and the most likely would be someone who is currently betting on Android and worried that now that Google has to make real money on Android to justify its $6B acquisition of Motorola Mobile maybe they should hedge that bet; but it will be an expensive hedge). I don’t know why HP expected to be a big hit out of the gate with its WebOS strategy, and if it didn’t have the stomach for a lengthy race and thought it was a sprint, I don’t know why they bothered to get into the business in the first place.

HP, which is the largest PC manufacturer in the world, also announced that it may get out of PCs. Presumably, in the same way as IBM, by finding a home for the division in a company that is more geared up to producing consumer products.

They are also buying Autonomy, the largest software company in the UK, $10B, positioning themselves more in services and servers, competing head to head with IBM and Oracle. Of course Apotheker the CEO would probably prefer to buy his old company SAP but he can’t afford it since it is worth as much as HP.

Analysts didn’t like it and many downgraded HP, and as a result HP is down 20% (destroying $12B or so of market cap). So forget that SAP is worth as much as HP, it’s now worth $10B more.

So what a story! The big fight by Carly Fiorina (against Walter Packard, Bill’s son) to buy Compaq. Oh yes, and people’s phones being bugged. Out she goes. In comes Mark Hurd. Weird sexual shenanigans and out he goes (and pops up at Oracle). In comes Leo Apotheker (whose prior experience was all running software businesses such as SAP and for a time was hiding to avoid being subpoenaed in a lawsuit with Oracle). I wonder how long he’ll last.

August 19, 2011June 14, 2019

Top 5 Reasons for Wasting Power

Top 5 Reasons for Wasting Power
by Paul McLellan on 08-19-2011 at 2:27 pm
Categories: Ansys, Inc., EDA

Traditionally, David Letterman style, we should really have the top 10 reasons for wasting power in semiconductor design, but here are the five big ones.

Starting with reason #5: Lack of a power gating strategy
Leakage power is a huge proportion of total power and the only way to save leakage power (apart from low leakage cells when they can be used) is to turn off the power. Of course this doesn’t just save leakage power, it saves dynamic power too. Your cell-phone battery wouldn’t last very long if the transmit/receive logic was kept powered up all the time even when you weren’t making a call. This is not something that can easily be automated. The design needs to be partitioned into power regions and control signals created (usually under software control) to handle the power down and restore (and retain register values if necessary). CPF and UPF devote a lot of their specifications for making sure the boundaries of blocks like this are correctly handled.

Reason #4: Poor local register enable conditions
Synthesis tools will replace recirculating muxes with clock gates. But often a register can be gated much more frequently since either the value in the register will never be used or else it is clear from some other aspect of the design that the value in the register will not change. In both these cases power will be saved by gating the clock to the register. As always, the easiest way to waste power is to do work that is not required to be done.

Reason #3: Inefficient design architecture
It is widely known that tradeoffs made at the higher levels of abstraction can result in larger impacts on performance, power and area. Choosing the number of pipleline stages in a datapath, for example, can have a major impact on power. Having one part of the chip that forces the clock frequency higher than required for the rest of the block can waste a lot of power. Almost any aspect of memory organization (size, number, type) has a big impact on power.

Reason #2: Inefficient design implementation
This is a combination of user problems and tool problems. There are many suboptimal ways to implement things, such as having high-frequency nets longer than necessary (and thus with excess capacitance). Excessively tight timing constraints during synthesis can result in higher powered cells than necessary being selected. Almost always there is a tradeoff between performance and power and demanding unnecessarily high performance or specifying unnecessarily tight constraints can result in power being wasted.

And, drum roll please, the top reason for wasting power: Missed global clock gating opportunities
Local register-level clock gating has been automated in synthesis tools (replacing recirculating muxes with a clock gate). But there are more opportunties than this, although they required that you understand the design intent and thus know when clocks must run and when they can be stopped. For example, redundant memory reads and writes (reading the same address or writing the same data to the same address) are huge wastes of power.

See Will Ruby’s more extensive discussion of these issues here.

August 19, 2011June 14, 2019

Design Constraints

Design Constraints
by Paul McLellan on 08-19-2011 at 2:12 pm
Categories: Uncategorized

Design constraints, which express higher level design intent, are one of the pieces of ancillary data that are critical to the success or failure of a custom (in fact any) design. Design constraints aren’t usually contained within layout files or library information, but without these critical data, designs may not meet specifications.

Today, most custom design teams manage constraints in ad-hoc, manual fashions. This ad-hoc approach has become a significant limitation when it comes to automating the custom design process, which in turn can limit both design productivity and accuracy. Moving forward, the custom design community is starting to look to standards efforts to ease the burden of correlating and communicating design constraints throughout the design process.

Pulsic is committed to increasing interoperability in the EDA community and thus Pulsic contributed its recommendation on custom design constraints to the IPL Alliance (www.iplnow.com) in August 2010. Pulsic is a member of the working group within the IPL to create an industry standard for custom design constraints. Pulsic is making its recommendation available for review and comment here under a click through license agreement. Pulsic is proactively acting as a conduit for additional user feedback into the IPL standardization process. Please continue to check with the IPL Alliance on their website for availability of a published standard on custom design constraints.

The white paper on design constraints is here.

Pulsic’s constraint recommendation is here.

August 19, 2011June 14, 2019

Intel’s Back to the Future Buy of Micron

Intel’s Back to the Future Buy of Micron
by Ed McKernan on 08-19-2011 at 5:14 am
Categories: Arm, Foundries, Intel Foundry, IP

In an interview that Gordon Moore gave in early 2000, the former co-founder of Intel recounted how they abandoned the DRAM market in the early 1980s in order to exit the increasingly unprofitable business and focus on the promising, yet still young x86 processor market. Intel was also home to EEPROM and NOR Flash, two memory technologies that spirited their way into the embedded markets. Now, opportunity arises for Intel to jump back into memory with both feet by buying Micron. What would be the logic of Intel going Back to the Future?

I believe part of the answer can be found in the same interview with Moore. At one point the interviewer asked about the raging battle between CISC and RISC at the end of the 1980s and early 1990s. CISC stands for Complex Instruction Set Computing (i.e. Intel x86) while RISC stands for Reduced Instruction Set Computing (e.g. SPARC, MIPs, ARM). Moore says the reason RISC was widely embraced, as the architecture of the future is because memory speeds caught upand matched processor speeds. The net result was that with RISC you could do a lot of simple operations going to memory very rapidly vs. CISC that tried to do a lot of operations on the chip. CISC was bigger but given Intel’s high volume, it did not turn out to be a cost penalty. Also Intel thrived on the PC software ecosystem tied to x86.

Today Intel grapples with the opposite position where memory is much slower than the processors so they need to develop new ways to closely couple DRAM and Flash to their multi-core processors. Intel can generate extra value in the server space if they can demonstrate a total solution that improves the performance per watt. In the consumer space, Intel may look to new package technologies to shrink the footprint in the rapidly evolving tablet and ultrabook space.

All these possibilities are bolstered by the state of the semiconductor industry and the current way Wall St. values Intel. Intel is valued at a P/E less than 9 or like an early 1980s Detroit Auto Company not knowing if survival is possible. The difference is that they are investing nearly $11B in CapEx, buying back $10B of stock this year and issuing over $4B in dividends. It is gushing with cash flow that has to be put to good use. All attempts to win over Wall St. have failed because of the fear that the PC market will collapse overnight. HP spinning out its PC business adds to the climate of fear.

Weather PCs grow 10% or decline 10%, Intel has to continue moving forward with its Barbed Wire Fence Strategy (see Intel’s Barbed Wire Fence Strategy) in order to diminish competitors and increase its ownership of the platform $$$. This could be the final consolidation phase of a market that is similar to how IBM eliminated the 7 dwarfs in the 1970s and 1980s. Intel was able to increase its platform ASP the past 12 months with the integration of graphics and the shift to mobile from desktops. If the PC market turns down, then the pressure should be felt by nVidia and AMD first.

Assuming Intel goes ahead with the purchase of Micron, there has to be a manufacturing angle as well. A semiconductor industry analyst pointed out to me that he thought Samsung was in the lead to getting to 450mm with Intel right behind. Samsung’s first choice for 450mm is Flash memory in an attempt to separate themselves from Toshiba, Sandisk and Micron. Intel may view NAND as a strategic asset that can not be dominated by Samsung., otherwise it becomes a thorn in their platform side. With a Micron acquisition, they would have two drivers on 450mm: NAND flash and x86 processors.

The obvious conclusion to this is that Intel’s future PC and Server platforms will be comprised predominately of x86 and SSDs (DRAM and HDDs are minor commodity components) and Intel does not intend to split the platform $$$ with Samsung or ARM.

August 18, 2011

Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM

Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM
by Daniel Payne on 08-18-2011 at 10:30 am
Categories: EDA, Siemens EDA

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better than Cure: DRC/DFM Inside of P&R
Getting to the 32nm/28nm Common Platform node with Mentor IC Tools

If you want some hands-on time with the Calibre tools then consider attending the August 25th workshop in Fremont, CA.

August 17, 2011June 14, 2019

MUSIC in Bangalore

MUSIC in Bangalore
by Paul McLellan on 08-17-2011 at 7:18 pm
Categories: Uncategorized

When you think of Indian music you might think of ragas for the sitar. But when you think of Indian MUSIC, that is the Magma user group meeting (Magma Users Summit for Integrated Circuits) coming up on September 7th in Bangalore (note: the date has changed from when it was originally announced). It is at Vivanta by Taj on M G Road.

There is a guest keynote by Balajee Sowrirajan of Texas Instruments OMAP business unit on Trends and challenges in designinbg wireless application processor–what is the need of the day? at 9.30am.

The second keynotet is at 12.35pm, just before lunch, by Rajeev Madhavan, Magma’s CEO.

There are other presentations by TI, Qualcomm, ARM, Netlogic, Microchip and Silicon One.

More information, including the complete agenda, is here.

To register, go here.