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Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP

Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP
by Eric Esteve on 05-07-2012 at 3:17 am
Categories: IP, Synopsys

Synopsys is consolidating the company positioning on Verification IP. We have announced the launch of Discovery VIP in Semiwiki, in February this year, and we have commented about the acquisition of nSys and ExpertIO in January. This webinar, “Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP”, to be held on May, 8 at 10am PDT, will allow the audience to better understand Cache coherency management problematic. Traditionally, cache coherency management has largely been performed in software, adding to software complexity and development time. With AMBA 4 ACE, system level coherency is performed in hardware, providing better performance and power efficiency for complex SoC designs. However, this shifts much of the complexity of verify cache coherency to functional verification.

This webinar begins with a short overview of the challenges of verifying a coherent design and goes on to show how the features and architecture of Synopsys’ new Discovery Verification IP helps overcome these challenges to simplify the verification of ACE designs.

The ever growing design time spent in verification, we have recently read figures of 70% of the overall hardware design effort being associated with the verification, is creating a demand for most efficient EDA tools, and accurate Verification IP (dedicated to a specific protocol).

The next picture is useful to understand the cost breakdown associated with Verification. If you look at the middle left box, you see a 3X cost (or license count, or resources) increase for almost every task (except “Tool, Support and Service” with 20% only). So, offering a 3 to 6X run time improvement is welcome, to keep the design schedule and consequently the time to market within reasonable limits.

You can log to this webinar here

From Eric Esteve from IPnest

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TSMC 20nm Challenges!

TSMC 20nm Challenges!
by Daniel Nenni on 05-06-2012 at 7:00 pm
Categories: EDA, Foundries, TSMC
4 Comments

Now that the 28nm challenges are dead
It is time to look ahead
The tabloid pundits may not agree
But Moore’s law again you will see
The semiconductor ecosystem is humming
(2X gate density -20%+ performance-20%+ power savings)
The 20nm design starts are coming!

Okay, I’m really bad at poetry. Gambling however, I do pretty well. Las Vegas is my favorite destination, a mere 6 hour Porsche drive from Danville. It’s not just the math of gambling that’s intriguing, it’s also how you read a person, a play, or situation. I literally won all of my bets on 28nm and 20nm looks like another great gambling opportunity. I have two more kids to get through college so put your money where your mouth is.

Here is why the 20nm challenges will be vanquished in record time: GREED, simple as that! As I mentioned before, the semiconductor ecosystem consists of a very large crowd of very smart people with very big egos who really like making money (me for example). Whomever solves the 20nm design and manufacturing puzzles first not only gets fame, they also get fortune. Talk about motivation. And who doesn’t like solving puzzles?

20nm blogs-white papers-webinars are in play
20nm test chips arriving every day
40nm we learned how to yield
28nm we yearned for capacity
20nm will be an even bigger payday!

Better? Intel has done us all a really big favor. They are shooting their mouth off, motivating the masses, because who in their right mind would NOT want to prove Intel wrong? Especially if you can make money while doing it. Sign me up!

Here is the biggest bet: What will the TSMC 20nm ramp look like?

Remember, even though the tabloid press had 28nm “not yielding at all” and “shut down for weeks” in Q1 2012, the ramp thus far has beat expectations. The questions are:

[LIST=1]

  • Will 20nm be on par with 28nm?
  • When will the 20nm ramp officially start?
  • How far behind the Intel 22nm SoC mobile version will it be?


    According to the SemiWiki crowd, Apple will be at TSMC 20nm:

    Who will Apple partner with at 20nm?

    [LIST=1]

  • TSMC 38.04%
  • Intel 25.00%
  • Neither (stay at Samsung) 19.57%
  • Both 17.39%

    So you might want to factor that extra motivation into your gambling equation.

    My trip this week was off a bit due to the national Taiwan holiday on Tuesday so here I sit in the EVA Executive Lounge on a sunny Saturday afternoon.

    Don’t feel bad for me there’s an open bar
    Don’t feel bad for me I have a beautiful car
    Don’t feel bad for me this week I’m fishing afar

    • Posted on

    Formal Verification, there’s an App for that

    Formal Verification, there’s an App for that
    by Paul McLellan on 05-06-2012 at 6:00 pm
    Categories: EDA
    1 Comment

    The success of Apple’s AppStore has made people aware that software doesn’t have to be delivered in a big monolithic lump. Indeed, going back a bit earlier, Apple’s iTunes store made people aware that you didn’t have to buy a whole album if you only wanted a track or two.

    EDA applications in today’s server-farm world suffer from another problem: you might want to buy a lot of one capability of a tool, because you use it a lot, and a little (or none) of another capability that you rarely make use of. The monolithic approach lacks this flexibility.

    Jasper’s flagship JasperGold product has historically been delivered in a form that included all the capabilities, and at a price point that reflects that breadth. In some ways this works well for formal verification since different proof engines can work together: if you can’t prove something with engine A then maybe engine B can prove it. It only takes one engine to succeed. It’s a bit like solving differential equations. You just have to find some way to come up with an answer that differentiates back to the equation you started with, and it is hard to predict which approach might work.

    JasperGold is being restructured into a sort of backplane consisting of a common database and a common user-interface. Into this backplane you can plug one or more Apps.

    The initial Apps that are available are:

    • Formal Property Verification (FPV) App
    • Connectivity Verification App
    • X-propagation Verification App
    • RTL Development App
    • Architectural Modeling App
    • Control/Status Register (CSR) Verification App


    In the future additional Apps will be added. There are still a few products (Active Prop Property Synthesis, Post-Silicon Debug and the Intelligent Proof kits) which are still delivered as separate line-items outside of the App infrastructure.

    This App approach to delivering capability fits much better with the realities of how design is done today. Very large design teams, large server farms providing compute resource, internationally distributed development.

    This App approach (Approach?) makes it straightforward to run multiple applications on the same block, sharing the work product through the common database, and so reducing the total effort for the project. It is easy for a user to run multiple applications on the same block and launch parallel applications through the same user interface. Parallel jobs can be launched through the common interface with the results from all the parallel jobs being collected back into the common database. Overall, it allows for more flexible deployment of software licenses, and thus capabilities, than the monolithic approach.

    More details of JasperGold Apps are here.

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    Where to eat lunch or get a beer at DAC

    Where to eat lunch or get a beer at DAC
    by Paul McLellan on 05-04-2012 at 11:17 pm
    Categories: EDA, Events
    5 Comments

    You are going to DAC. And you don’t want to eat a Moscone Center rubber chicken Caesar salad for lunch. But you lack local knowledge. So here are some places within a 10 minute walk. These are just places I like. Nobody is paying me to recommend them.

    Places to eat
    The food court in the San Francisco Center on Market Street between 4th and 5th Street. This is to normal mall foodcourts the same way San Francisco Airport food is to normal airports. It’s actually good. There are two food courts, but far and away the best is the one at the 4th street end of the building. Go in the first entrance you come to walking along Market Street and go down the escalator. It has an amazing selection of ethnic food (Vietnamese, Korean, Thai, Japanese, Mexican, gourmet burgers, even Vegan Chinese…). There is another level with more expensive restaurants on the 4th floor (mostly not open for lunch). I like the Straits Cafe (Singaporean food) which does do lunch too.

    Indian: Chaat Cafe on the corner of 3rd Street and Folsom. The Tandoori mixed grill is a particularly good bargain if you have a crowd.

    Thai: Osha on another corner of 3rd Street and Folsom

    Mexican: Chevy’s on corner of 3rd Street and Howard Street

    Brew pub and tapas (yes, both): Thirsty Bear on Howard between 3rd and 2nd Streets

    Pizza: California Pizza Kitchen on 3rd between Mission and Market Streets

    Chinese: Henry’s Hunan on Natoma Street just off New Montgomery Street. Don’t miss Diana’s Special Meat Pie.

    Hawaiian: Roy’s on Mission between 2nd and 1st (pricey, take a salesperson to pay the bill!)

    Japanese: Ame in the St Regis Hotel on the corner of Mission and 3rd Street. Fabulous. Not open for lunch. But take a C-level executive to pay the bill.

    SFMOMA (see below)

    Bars
    The Pied Piper Bar in the Palace Hotel on the corner of Market Street and New Montgomery Street. Old fashioned bar with an amazing huge painting by Maxfield Parrish. My favorite bar in the area.

    The Upstairs bar in the W hotel on the corner of 3rd and Howard Streets (not the one on the first floor). Maybe too trendy…

    House of Shields on New Montgomery Street between Mission and Market. Live music for over 100 years, since the earthquake (the 1906 one).

    Top floor bar in the Marriott Hotel on the corner of 4th and Mission. Great place to view the whole city and watch the sunset. Find the right elevator and go to the 39th floor.

    The best wine bar in San Francisco is District on Townsend between 3rd and 4th. And the best brewpub is 21st Amendment on 2nd Street between Bryant and Brannan. Both are a little outside the 10 minute range, more like 15, and both have good food too.

    Place to spend a spare hour or two
    San Francisco Museum of Modern Art (SFMOMA) on 3rd Street between Howard and Mission. Closed on Wednesday. The food in the cafe is good too.

    Comment
    If you live in the city or know it well, then feel free to add your own recommendations in the comments.

    Map
    Everywhere is on this map (except District and 21st Amendment). That’s how close they are. You don’t have to have a crummy hamburger in one of the best foodie cities in the world.

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    GlobalFoundries 2012 Update!

    GlobalFoundries 2012 Update!
    by Daniel Nenni on 05-04-2012 at 8:55 pm
    Categories: Foundries, GlobalFoundries

    What’s new with Glofo? Quite a bit actually. It was interesting to see a Made in America: Global Companies Expand in U.S. Towns segment on semiconductors! Give it a look, I enjoyed it. It’s an election year, jobs are key to any election, so it did not surprise me to see President Obama making the rounds:
    Continue reading “GlobalFoundries 2012 Update!”

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    It is free after you pay for it and there is a one-time annual fee: The Case for FD-SOI

    It is free after you pay for it and there is a one-time annual fee: The Case for FD-SOI
    by Camille Kokozaki on 05-04-2012 at 7:09 am
    Categories: Global Semiconductor Alliance, Semiconductor Services
    3 Comments

    In one of Portlandia’s TV program sketches, there is a funny interchange between a carrier salesperson and Fred Armisen (of SNL fame) who was trying to buy a phone. One chuckle line was a statement by the seller that the phone was free after paying for it and that there was a one-time annual fee. With this anecdote as a mental backdrop, the question for making the case for a new technology is: Is there a free gain? How much effort is really needed? The technology topic here is FD-SOI. This SOI exposé attempts to highlight the merits of FD-SOI (fully depleted Silicon-On-Insulator, and/or UTB-SOI, defined further below) which is now being looked as a viable technology offering since bulk CMOS is showing limits with technology node scaling. SOI technology is certainly not new in terms of having attractive leakage characteristics when compared to bulk C-MOS. The SOI consortium has announced a joint collaboration by ARM, Global Foundries, IBM, STMicroelectronics, Soitec, CEA- Leti to promote the FD-SOI technology and its value in mobile communication applications. The benefits are stated to be that Power/Performance metrics are excellent specially at lower voltages, simpler manufacturing and lower leakage.

    Joël Hartmann (Corp VP or front-end manufacturing and process R&D at STMicroelectronics) made a compelling case for FD-SOI at the latest GSA Silicon Summit in April and he highlighted that this technology is a main contender now that the bulk C-MOS is reaching its feature size limits (beyond 20nm that is) where short channel effects make bulk unworkable. ST is counting on FD-SOI at least for its 28nm and 20nm road map and will have products this year using 28nm FD-SOI. The industry’s alternative choice for advanced nodes is FinFET and was discussed earlier by Paul McLellan. Beyond bulk, fully depleted devices will be needed for improved electrostatic control. FD-SOI can be further turbo-charged by adding ultra thin box back body bias (UTB-SOI) with added performance specially at lower voltages. In the same event, Dr Chenming Hu succinctly outlined the main differences between FinFET and UTB-SOI in that for FinFET the body thickness has to be less than the gate length Lg with larger Ion current and foundry investments, whereas the UTB-SOI requires thickness less than 1/3 the gate length, with a good back-bias option and SOI supplier investments. The arguments in favor of FD-SOI as stated by STMicroelectronics are:

      [*=1]the use of the same Back-end process,
      [*=1]only 20% of FD-Specific Front end process needs new development,
      [*=1]wafer costs (process and substrate) are similar,
      [*=1]10% better lead-time is achievable,
      [*=1]no added Capex are needed since the same equipment is used,
      [*=1]the process is portable through shrink and scalable to 14nm.

    In the future FinFETs can also be built on top of SOI. The STMicro charts below illustrate how much power and performance can be gained using the UTB-SOI technology. At 1.0V 28nm FD-SOI with back bias can achieve a 94% performance boost over 28LP and at 0.6V a remarkable 730% improvement can be seen. More impressively at low Vdd the energy efficiency in (DMIPS/mW) literally goes through the roof as evidenced in the upward tilt of the top left curve. These are compelling numbers that merit notice and explain the road map direction of STMicroelectronics.

    It does thus appear, in an interesting way that performance and energy efficiency gains can be free after developments paid for them and that there is a one-time development fee that needs to stay annual to keep the bits pumping in the ever shrinking geometries. Now you also know that I will stretch words to fit my anecdote in the hope that you realize I am just word playing here to get you to read, to be informed and freely entertained.

    References:
    GSA Silicon Summit April 26, 2012 Mountain View, CA (The source for most of the graphics and data)
    SOI technology for the GHz era – by G. G. Shahidi
    Evaluation of a fully-depleted SOI for next generation Mobile Chips – by Horacio Mendez Executive Director, SOI Industry Consortium

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    28nm Layout Needs Signoff Quality at Design Time

    28nm Layout Needs Signoff Quality at Design Time
    by Pawan Fangaria on 05-03-2012 at 8:30 pm
    Categories: Cadence, EDA

    We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.

    Having worked at Cadence and knowing that it is a leader in layout design tools, I wanted to explore what kind of solution Cadence is providing for these issues. After talking to Dr. Tianhao Zhang, Sr. Product Marketing Manager at Cadence, I was impressed to know that the Cadence product, Virtuoso Integrated Physical Verification System (Virtuoso IPVS), provides a production-proven signoff quality solution to these problems in layout at the design stage.

    Virtuoso IPVS integrates foundry-qualified PVS DRC technology into the Virtuoso Layout Suite (available in all tiers L, XL and GXL) in real-time mode to prevent inadvertently created errors, verifies and fixes DRC errors incrementally. The whole system dynamically works on the OpenAccess database, eliminating translations to other formats like Stream, thereby increasing designer productivity multi fold. Furthermore, the PVS in-memory integration works hand-in-hand with the design; the designer doesn’t even need to save the design in order to verify it.

    Along with productivity, Virtuoso IPVS provides signoff-level accuracy by using a signoff-quality engine and rule deck. While it employs DRD (Design Rule Driven) editing, preventing errors during layout editing, it provides signoff-level verification of the edits along with surrounding areas on-the-fly. Also, there is in-memory, on-demand verification available for the design as required, hence optimizing design and verification time. As a result, the designer can stay within the Virtuoso Layout System, doing design implementation, verification and signoff, uninterrupted until the design is ready for tapeout.

    The Virtuoso IPVS can be used at any node including 20nm where double patterning technology (DPT) takes place. It can detect color loop in real-time based on foundry rules. In addition, Virtuoso IPVS with the Virtuoso unique dynamic colorization feature provides a comprehensive solution at 20nm.

    Virtuoso IPVS is being used in production supported by major foundries at advanced nodes. It was pleasing to know from OA database that designers at Cortina Systems, Inc. are using Virtuoso IPVS on 28nm and are seeing great productivity and quality of results with this tool. CDNLive! is a great forum for Cadence customers to present their best stories and experiences in working with Cadence. It was heartening to see the presentation titled “Signoff Quality Verification Earlier in Design Flow with Virtuoso IPVS” at CDNLive! Silicon Valley 2012, presented by Malcolm Stevens, Distinguished Engineer at Cortina Systems. In these slides he discussed the challenges at lower nodes and how the flow with Virtuoso IPVS helps in those difficult situations. More details can be obtained from Dr. Tianhao.

    By Pawan Kumar Fangaria
    EDA/Semiconductor professional and Business consultant
    Email:Pawan_fangaria@yahoo.com

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    The Biggest EDA Company You’ve Never Heard Of

    The Biggest EDA Company You’ve Never Heard Of
    by Paul McLellan on 05-02-2012 at 8:30 pm
    Categories: EDA
    4 Comments

    There’s this EDA company. They have over 100 tapeouts. They have a $28M in funding. They have 250 people. And you’ve never heard of them. Or at least I hadn’t.

    They are ICScape. They started in 2005 with an investment from Acorn Campus Ventures and delivered their first product, ClockExplorer, in 2007 and their second, TimingExplorer in 2009. They then have gone on to develop a complete openAccess-based place and route system including placement, clock-tree-synthesis, routing, static timing analysis, parasitic extraction and…

    In 2008-2010 during the technology downturn they survived purely on product revenue. They turned their attentions to China, which was one area that was still buoyant. Also in China is a 20 year old EDA company called Huada Empyrean Software (HES) who have an openAccess-based analog environment. HES is a subsidiary of China Electronics Corporation, China’s largest electronics conglomerate (and an SOE). HES want to expand outside of China and become a global player, so it was spun out of CEC and merged with ICScape and provided with $28M in funding. They have one engineering organization. HES sells the whole product line in China and Taiwan. ICScape everywhere else (the US, Korea and Japan today, and Europe soon).

    They have big plans to become a big global EDA player. I have no idea how good their technology is but they claim that over 100 chips have been taped out, including some at the 28nm technology node, so it should be pretty solid. Customers include Marvell, Huawei, ZTE, NHK and more.

    The SoC product line is based around accelerating design closure by reducing the number of iterations by 50%. It consists of four tools:

    • TimingExplorer, a physically aware multi-corner, multi-mode timing ECO tool
    • ClockExplorer, which can reduce clock insertion delay by up to 50% and clock-tree power by 40%
    • Skipper, a high-performance and ultra-large capacity chip finishing solution
    • FlashLVL, a high-speed layout comparison tool

    The analog product line is now in its 6th generation. It is focused on big-A small-D designs with lots of analog and limited amounts of digital. It contains:

    • interconnect-aware layout editing
    • high-capacity parallel circuit simulation
    • hierarchical parallel physical verification
    • mixed-mode, multi-corner parasitic extraction and analysis

    Going forward the plan is to bring all the technologies together, which is not such a daunting task as it might be since both product lines are native OA-based. At the same time expand their channel to have complete coverage everywhere.

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    Use a SpyGlass to Look for Faults

    Use a SpyGlass to Look for Faults
    by Paul McLellan on 05-02-2012 at 5:24 pm
    Categories: EDA
    1 Comment

    There is a famous quote (probably attributed to Mark Twain who gets them all by default) “When looking for faults use a mirror not a spyglass.” Of course if you have RTL of your IP or your design then using a SpyGlass is clearly the better way to go. But it is getting even better since there is a new enhanced release, SpyGlass 4.7.

    Of course there are enhancements to speed and capacity to keep up with the increase in design sizes. Some users have been running 280 million gate designs through flat overnight. There is some bottom-up hierarchical design support (and more coming in the future).

    But the biggest changes are in the power area. There are some detailed improvements in UPF support, and how clock-domain-crossing analysis interacts with it.

    The RTL power reduction capability has improved by a factor of two compared to the previous release. It seems to achieve around 12% power reduction typically, nearly 25% at times (and, of course, there are some designs where there just are not any gains to be had). The sequential equivalence checking engine has also been improved to do a better job of verification of RTL that has been modified to reduce power, both when this is done by hand or automatically.

    Another new capability is that SpyGlass can now estimate design complexity using cyclomatic metrics, which is a measure based on branching analysis (usually in software but adapted to RTL). This is a good predictor for the time and effort that will be required to create a verification test bench for complete functional verification.

    There are also improvements to SpyGlass Physical, in particular there is improved estimation of routing congestion and an early estimation of area, both of which give early and so actionable feedback about likely problems that will occur later with physical design.