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It is free after you pay for it and there is a one-time annual fee: The Case for FD-SOI

It is free after you pay for it and there is a one-time annual fee: The Case for FD-SOI
by Camille Kokozaki on 05-04-2012 at 7:09 am
Categories: Global Semiconductor Alliance, Semiconductor Services
3 Comments

In one of Portlandia’s TV program sketches, there is a funny interchange between a carrier salesperson and Fred Armisen (of SNL fame) who was trying to buy a phone. One chuckle line was a statement by the seller that the phone was free after paying for it and that there was a one-time annual fee. With this anecdote as a mental backdrop, the question for making the case for a new technology is: Is there a free gain? How much effort is really needed? The technology topic here is FD-SOI. This SOI exposé attempts to highlight the merits of FD-SOI (fully depleted Silicon-On-Insulator, and/or UTB-SOI, defined further below) which is now being looked as a viable technology offering since bulk CMOS is showing limits with technology node scaling. SOI technology is certainly not new in terms of having attractive leakage characteristics when compared to bulk C-MOS. The SOI consortium has announced a joint collaboration by ARM, Global Foundries, IBM, STMicroelectronics, Soitec, CEA- Leti to promote the FD-SOI technology and its value in mobile communication applications. The benefits are stated to be that Power/Performance metrics are excellent specially at lower voltages, simpler manufacturing and lower leakage.

Joël Hartmann (Corp VP or front-end manufacturing and process R&D at STMicroelectronics) made a compelling case for FD-SOI at the latest GSA Silicon Summit in April and he highlighted that this technology is a main contender now that the bulk C-MOS is reaching its feature size limits (beyond 20nm that is) where short channel effects make bulk unworkable. ST is counting on FD-SOI at least for its 28nm and 20nm road map and will have products this year using 28nm FD-SOI. The industry’s alternative choice for advanced nodes is FinFET and was discussed earlier by Paul McLellan. Beyond bulk, fully depleted devices will be needed for improved electrostatic control. FD-SOI can be further turbo-charged by adding ultra thin box back body bias (UTB-SOI) with added performance specially at lower voltages. In the same event, Dr Chenming Hu succinctly outlined the main differences between FinFET and UTB-SOI in that for FinFET the body thickness has to be less than the gate length Lg with larger Ion current and foundry investments, whereas the UTB-SOI requires thickness less than 1/3 the gate length, with a good back-bias option and SOI supplier investments. The arguments in favor of FD-SOI as stated by STMicroelectronics are:

    [*=1]the use of the same Back-end process,
    [*=1]only 20% of FD-Specific Front end process needs new development,
    [*=1]wafer costs (process and substrate) are similar,
    [*=1]10% better lead-time is achievable,
    [*=1]no added Capex are needed since the same equipment is used,
    [*=1]the process is portable through shrink and scalable to 14nm.

In the future FinFETs can also be built on top of SOI. The STMicro charts below illustrate how much power and performance can be gained using the UTB-SOI technology. At 1.0V 28nm FD-SOI with back bias can achieve a 94% performance boost over 28LP and at 0.6V a remarkable 730% improvement can be seen. More impressively at low Vdd the energy efficiency in (DMIPS/mW) literally goes through the roof as evidenced in the upward tilt of the top left curve. These are compelling numbers that merit notice and explain the road map direction of STMicroelectronics.

It does thus appear, in an interesting way that performance and energy efficiency gains can be free after developments paid for them and that there is a one-time development fee that needs to stay annual to keep the bits pumping in the ever shrinking geometries. Now you also know that I will stretch words to fit my anecdote in the hope that you realize I am just word playing here to get you to read, to be informed and freely entertained.

References:
GSA Silicon Summit April 26, 2012 Mountain View, CA (The source for most of the graphics and data)
SOI technology for the GHz era – by G. G. Shahidi
Evaluation of a fully-depleted SOI for next generation Mobile Chips – by Horacio Mendez Executive Director, SOI Industry Consortium

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28nm Layout Needs Signoff Quality at Design Time

28nm Layout Needs Signoff Quality at Design Time
by Pawan Fangaria on 05-03-2012 at 8:30 pm
Categories: Cadence, EDA

We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.

Having worked at Cadence and knowing that it is a leader in layout design tools, I wanted to explore what kind of solution Cadence is providing for these issues. After talking to Dr. Tianhao Zhang, Sr. Product Marketing Manager at Cadence, I was impressed to know that the Cadence product, Virtuoso Integrated Physical Verification System (Virtuoso IPVS), provides a production-proven signoff quality solution to these problems in layout at the design stage.

Virtuoso IPVS integrates foundry-qualified PVS DRC technology into the Virtuoso Layout Suite (available in all tiers L, XL and GXL) in real-time mode to prevent inadvertently created errors, verifies and fixes DRC errors incrementally. The whole system dynamically works on the OpenAccess database, eliminating translations to other formats like Stream, thereby increasing designer productivity multi fold. Furthermore, the PVS in-memory integration works hand-in-hand with the design; the designer doesn’t even need to save the design in order to verify it.

Along with productivity, Virtuoso IPVS provides signoff-level accuracy by using a signoff-quality engine and rule deck. While it employs DRD (Design Rule Driven) editing, preventing errors during layout editing, it provides signoff-level verification of the edits along with surrounding areas on-the-fly. Also, there is in-memory, on-demand verification available for the design as required, hence optimizing design and verification time. As a result, the designer can stay within the Virtuoso Layout System, doing design implementation, verification and signoff, uninterrupted until the design is ready for tapeout.

The Virtuoso IPVS can be used at any node including 20nm where double patterning technology (DPT) takes place. It can detect color loop in real-time based on foundry rules. In addition, Virtuoso IPVS with the Virtuoso unique dynamic colorization feature provides a comprehensive solution at 20nm.

Virtuoso IPVS is being used in production supported by major foundries at advanced nodes. It was pleasing to know from OA database that designers at Cortina Systems, Inc. are using Virtuoso IPVS on 28nm and are seeing great productivity and quality of results with this tool. CDNLive! is a great forum for Cadence customers to present their best stories and experiences in working with Cadence. It was heartening to see the presentation titled “Signoff Quality Verification Earlier in Design Flow with Virtuoso IPVS” at CDNLive! Silicon Valley 2012, presented by Malcolm Stevens, Distinguished Engineer at Cortina Systems. In these slides he discussed the challenges at lower nodes and how the flow with Virtuoso IPVS helps in those difficult situations. More details can be obtained from Dr. Tianhao.

By Pawan Kumar Fangaria
EDA/Semiconductor professional and Business consultant
Email:Pawan_fangaria@yahoo.com

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The Biggest EDA Company You’ve Never Heard Of

The Biggest EDA Company You’ve Never Heard Of
by Paul McLellan on 05-02-2012 at 8:30 pm
Categories: EDA
4 Comments

There’s this EDA company. They have over 100 tapeouts. They have a $28M in funding. They have 250 people. And you’ve never heard of them. Or at least I hadn’t.

They are ICScape. They started in 2005 with an investment from Acorn Campus Ventures and delivered their first product, ClockExplorer, in 2007 and their second, TimingExplorer in 2009. They then have gone on to develop a complete openAccess-based place and route system including placement, clock-tree-synthesis, routing, static timing analysis, parasitic extraction and…

In 2008-2010 during the technology downturn they survived purely on product revenue. They turned their attentions to China, which was one area that was still buoyant. Also in China is a 20 year old EDA company called Huada Empyrean Software (HES) who have an openAccess-based analog environment. HES is a subsidiary of China Electronics Corporation, China’s largest electronics conglomerate (and an SOE). HES want to expand outside of China and become a global player, so it was spun out of CEC and merged with ICScape and provided with $28M in funding. They have one engineering organization. HES sells the whole product line in China and Taiwan. ICScape everywhere else (the US, Korea and Japan today, and Europe soon).

They have big plans to become a big global EDA player. I have no idea how good their technology is but they claim that over 100 chips have been taped out, including some at the 28nm technology node, so it should be pretty solid. Customers include Marvell, Huawei, ZTE, NHK and more.

The SoC product line is based around accelerating design closure by reducing the number of iterations by 50%. It consists of four tools:

  • TimingExplorer, a physically aware multi-corner, multi-mode timing ECO tool
  • ClockExplorer, which can reduce clock insertion delay by up to 50% and clock-tree power by 40%
  • Skipper, a high-performance and ultra-large capacity chip finishing solution
  • FlashLVL, a high-speed layout comparison tool

The analog product line is now in its 6th generation. It is focused on big-A small-D designs with lots of analog and limited amounts of digital. It contains:

  • interconnect-aware layout editing
  • high-capacity parallel circuit simulation
  • hierarchical parallel physical verification
  • mixed-mode, multi-corner parasitic extraction and analysis

Going forward the plan is to bring all the technologies together, which is not such a daunting task as it might be since both product lines are native OA-based. At the same time expand their channel to have complete coverage everywhere.

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Use a SpyGlass to Look for Faults

Use a SpyGlass to Look for Faults
by Paul McLellan on 05-02-2012 at 5:24 pm
Categories: EDA
1 Comment

There is a famous quote (probably attributed to Mark Twain who gets them all by default) “When looking for faults use a mirror not a spyglass.” Of course if you have RTL of your IP or your design then using a SpyGlass is clearly the better way to go. But it is getting even better since there is a new enhanced release, SpyGlass 4.7.

Of course there are enhancements to speed and capacity to keep up with the increase in design sizes. Some users have been running 280 million gate designs through flat overnight. There is some bottom-up hierarchical design support (and more coming in the future).

But the biggest changes are in the power area. There are some detailed improvements in UPF support, and how clock-domain-crossing analysis interacts with it.

The RTL power reduction capability has improved by a factor of two compared to the previous release. It seems to achieve around 12% power reduction typically, nearly 25% at times (and, of course, there are some designs where there just are not any gains to be had). The sequential equivalence checking engine has also been improved to do a better job of verification of RTL that has been modified to reduce power, both when this is done by hand or automatically.

Another new capability is that SpyGlass can now estimate design complexity using cyclomatic metrics, which is a measure based on branching analysis (usually in software but adapted to RTL). This is a good predictor for the time and effort that will be required to create a verification test bench for complete functional verification.

There are also improvements to SpyGlass Physical, in particular there is improved estimation of routing congestion and an early estimation of area, both of which give early and so actionable feedback about likely problems that will occur later with physical design.

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Carl Icahn Blinks in Bid for Mentor Graphics

Carl Icahn Blinks in Bid for Mentor Graphics
by Daniel Payne on 05-02-2012 at 3:42 pm
Categories: EDA
10 Comments

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One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:

  • Have their annual shareholder meeting on May 30th
  • Two of Icahn’s board members are not on the roster for renewal
  • Mr. Icahn has no new board members to offer up

Read the complete proxy here.

To me this spells defeat for Carl Icahn in taking over Mentor Graphics because he is not offering up any new replacements on the board of directors. Had he been able to get just 5 out of 8 board members to agree with him, then he could’ve controlled the company. Now it appears that Carl’s three board members will be reduced to just 1, a very noticeable minority.

Mentor has a strong poison pill provision in place and only 1 Icahn board member will probably remain after the votes are tallied on May 30th.


Carl Icahn, AP Photo

Mr. Icahn does still own 14.6 percent of MENT shares, which he acquired at prices between $8 and $9 per share, so the present share price of $14.45 gives him a paper profit of over 50%, not too shabby.


If history is any indicator, then buy MENT in August, sell in April

I’ll attend the May 30th annual shareholder meeting at Mentor Graphics and let you know if there is any more drama left in this story, so hopefully we can all turn our attention to creating value for customers through EDA tools that enable the SOC revolution.

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IC design at 20nm with TSMC and Synopsys

IC design at 20nm with TSMC and Synopsys
by Daniel Payne on 05-02-2012 at 10:25 am
Categories: EDA, Foundries, Synopsys, TSMC

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While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.
Continue reading “IC design at 20nm with TSMC and Synopsys”

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ARM Models: Carbon Inside

ARM Models: Carbon Inside
by Paul McLellan on 05-01-2012 at 10:00 pm
Categories: Arm, EDA, IP

ARM used to build their own models. By hand. They had an instruction-set simulator (ISS) called ARMulator that was largely intended for software development, and cycle-accurate models that were intended to run within digital simulators for development of the hardware of ARM-based systems.

There were two problems with this approach. Firstly, ARMulator was built using interpretive technology and consumed approximately 1000 host instructions to simulate each ARM instruction so ran at a few MIPS. Modern virtual platform models use Just-In-Time (JIT) compilation, cross-compiling the ARM code into host instructions and so avoiding any interpreter overhead (the compiler creates overhead but that is minimal for instruction sequences executed many times). They thus run hundreds of times faster, fast enough to boot operating systems and debug industrial-sized loads of embedded software.

ARMulator was reasonably cheap to maintain since it simulated the instruction set which didn’t change much, apart from its half-hearted attempt at cycle-counting. The same could not be said for the cycle accurate models. These were expensive to develop and had to be re-implemented for each separate ARM processor. Verification, in particular, was a huge challenge. It is comparatively easy to get the basic model to work, but handling all the corner cases (pipeline interlock, delayed writeback, branch prediction, bus contention etc) is a real challenge.

In 2004, ARM acquired Axys Design in an attempt to leverage their models more as true virtual platforms. They renamed it SoC Designer. At the time I was working for VaST (so competing with Axys) and predicted that this would fail. And it was nothing to do with the technology, which was perfectly fine.

I had watched at VLSI Technology as customers balked at using our design tools since they didn’t want to get locked into VLSI-only solutions and I felt ARM customers wouldn’t want to get locked into ARM-only solutions. If you were using, say, a CEVA (then still DSP Group I think) Teak DSP then how are you going to get that into the platform. And what sort of support will you get from ARM if there are problems.

In 2008 ARM gave up, and sold SoC Designer to Carbon. This fixed the ARM-only issue since Carbon is an independent company. Further, at the same time, they gave up trying to hand-build their own cycle accurate models. Instead, Carbon used existing technology to build the models automatically from ARM’s RTL. ARM shifted their modeling focus to concentrate on their own JIT technology which they introduced as ARM Fast Models. These TLM models don’t attempt to model cycle accuracy and therefore execute much faster.

Since then Carbon has moved from being an RTL acceleration company to a true virtual platform company, with a complete set of ARM models (and later MIPS, Imagination and others) and some powerful technology for both bringing in transactional level models such as ARM’s Fast Models, where they exist, or creating models automatically from RTL where they do not. In some cases where both models exist, such as with ARM’s Cortex A processors, Carbon has even introduced dynamic swap technology to enable a virtual platform to start running with TLM models (to do the operating system boot, for example) and then switch to accurate models at a point of interest.

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RedHawk: On to the Future

RedHawk: On to the Future
by Paul McLellan on 05-01-2012 at 6:00 am
Categories: Ansys, Inc., EDA

For many, maybe most, big designs, Apache’s RedHawk is the signoff tool for analyzing issues around power: electromigration, power supply droop, noise, transients and so on. But the latest designs have some issues: they are enormous (so you can’t just analyze them naively any more than you can run a Spice simulation on them) and increasingly there are 3D designs with a whole new set of electrical and thermal effects that result from stacking very thin die very close on top of each other.

Apache has announced the latest version of RedHawk called RedHawk 3DX (the previous versions were SD for static-dynamic, EV for enhanced version, NX for next version and now 3DX for 3D extensions — Apache didn’t spend a lot on branding consultants!). This attacks some of the big issues connected with 3D, in particular the thermal problem (how much heat is there and what happens when you don’t get it all out) and issues concerned with how you can analyze designs which are too large to analyze the old way.

There are 3 main changes:

  • in keeping with its name, RedHawk 3DX is indeed ready for 3D and 2.5D ICs
  • there is a gate-level engine in RedHawk now, enabling the RTL based analysis of PowerArtist to be pushed further
  • there are changes in capacity and performance to keep up with Moore’s law and take RedHawk down to 20nm designs

In 3D there are two big problems (apart from the sheer capacity issue of analyzing multiple die at once). The first is die-to-die power and die-to-die thermal coupling, and the other is modeling TSVs and interposers (which obviously you don’t have unless you are doing 3D).

With a multi-pane GUI you can now look at the different die and the interposer and see the thermal effects. TSVs are obviously an electrical connection between adjacent die but they are (often) made of copper and are a good thermal connection too. This can be good (the next die is a sort of heatsink) or bad (DRAM doesn’t like to get hot). You can look at voltage drop issues to make sure you don’t have power supply integrity problems, and also at current and thermal.



The second big change is that the RTL analysis approach of PowerArtist is pushed into RedHawk. PowerArtist does RTL analysis and prunes the simulation vectors down to perhaps a few hundred critical ones where power transitions occur or where power is very high (for example, inrush current when a powered down block is re-activated). These few vectors need more detailed analysis down at the level RedHawk operates. There is also a vectorless mode. You can see in the pictures below how well the RTL level analysis matches the gate-level analysis, both in the numbers which differ by a few percent and just visually looking at the voltage drop color maps.

Of course on a large chip you want the capability to analyze different blocks at different levels, some at gate, some at RTL, some vectorless, and you can do that.

The third aspect of the new generation of RedHawk is keeping up with design size. There is a new sub-20nm electromigration signoff engine which is current direction aware, metal topology aware and temperature aware (all things that affect EM).


Plus, adding an extraction reuse view enables a reduced model of part of the power delivery network. This enables up to (actually occasionally more) 50% reduction in the simulation node-count without reducing accuracy. This enables full-chip simulation including the package impact, with blocks of interest analyzed in detail and other blocks reduced using the ERV approach.