There is a famous quote (probably attributed to Mark Twain who gets them all by default) “When looking for faults use a mirror not a spyglass.” Of course if you have RTL of your IP or your design then using a SpyGlass is clearly the better way to go. But it is getting even better since there is a new enhanced release, SpyGlass 4.7.
Of course there are enhancements to speed and capacity to keep up with the increase in design sizes. Some users have been running 280 million gate designs through flat overnight. There is some bottom-up hierarchical design support (and more coming in the future).
But the biggest changes are in the power area. There are some detailed improvements in UPF support, and how clock-domain-crossing analysis interacts with it.
The RTL power reduction capability has improved by a factor of two compared to the previous release. It seems to achieve around 12% power reduction typically, nearly 25% at times (and, of course, there are some designs where there just are not any gains to be had). The sequential equivalence checking engine has also been improved to do a better job of verification of RTL that has been modified to reduce power, both when this is done by hand or automatically.
Another new capability is that SpyGlass can now estimate design complexity using cyclomatic metrics, which is a measure based on branching analysis (usually in software but adapted to RTL). This is a good predictor for the time and effort that will be required to create a verification test bench for complete functional verification.
There are also improvements to SpyGlass Physical, in particular there is improved estimation of routing congestion and an early estimation of area, both of which give early and so actionable feedback about likely problems that will occur later with physical design.