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Intel Foundry All Hat No Cattle?

Intel Foundry All Hat No Cattle?
by Daniel Nenni on 05-12-2012 at 12:19 am
Categories: Arm, EDA, Events, Intel Foundry, IP, TSMC
1 Comment

If you look real close at the #49 DAC floor plan you will see the tiny Intel booth dwarfed by those of TSMC, GlobalFoundries, Samsung, and ARM. The number one semiconductor company in the world does not have the budget for the cornerstone conference of the semiconductor ecosystem? Oh my…… Intel has a big foundry hat and no cattle this year.

Now in its 49th year (this will be my 29[SUP]th[/SUP]), the Design Automation Conference features a wide array of technical presentations, tutorials, and workshops, as well as more than 200 of the leading semiconductor ecosystem partners in a colorful, well-attended trade show that attracts thousands of semiconductor professionals from around the world.

This year, industry luminaries from ARM, Inc., IBM Corp., Intel Corp. and the National Tsing Hua University will give the three keynote addresses. DAC 2012 will be held at my absolute favorite venue, other than Las Vegas, the Moscone Center in San Francisco, California, from June 3-7, 2012.


“In assembling the 49th DAC series of distinguished keynotes speakers, I am excited to announce that DAC is covering all bases, providing refreshing viewpoints for systems designers, IC designers and EDA software professionals,” said Patrick Groeneveld, General Chair of the 49th DAC.

“Tuesday kicks off with ARM’s Mike Muller, who will share his vision for a future of embedded computing systems. Given that ARM’s processors power most smartphones, this will show the way for computing in the future.”

“On Wednesday, Joshua Friedrich and Brad Heaney will outline the design practices for high-performance microprocessors. This unique dual-keynote provides a look in the kitchen of leading microprocessor companies designing the world’s most advanced chips,” Patrick enthusiastically continued.

“Finally, the Thursday keynote by Kaufman Award winner Dave Liu addresses the algorithmic revolution behind EDA. Prof. Liu’s contributions and insights have enabled the remarkable design automation revolution that actually powers today’s trillion-transistor devices.”

Keynote Schedule:
All keynotes will be held in rooms 102/103.

Tuesday, June 5, 2012 from 8:30am to 9:30am
Scaling for 2020 solutions
Mike Muller, CTO, ARM Inc., Cambridge, U.K.

Comparing the original ARM design of 1985 to those of today’s latest microprocessors, Mike will look at how far design has come and what EDA has contributed to enabling these advances in systems, hardware, operating systems, and applications as well as how business models have evolved over 25 years. He will then speculate on the needs for scaling designs into solutions for 2020 from tiny embedded sensors through to cloud-based servers that together enable the “Internet of things.” Mike will look at the major challenges that need to be addressed to design and manufacture these systems and propose some solutions.

Wednesday, June 6, 2012 from 10:45am to 11:45am
Designing High Performance Systems-on-Chip
Joshua Friedrich, Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group. Brad Heaney, Intel Architecture Group Project Manager, Intel Corp., Folsom, CA.

Experience state-of-the art design through the eyes of these two experts. Joshua Friedrich will talk about POWER processor design and methodology directions and Brad Heaney will discuss designing the latest Intel architecture multi-CPU and GPU. In this unique dual-keynote, the speakers will cover key challenges, engineering decisions and design methodologies to achieve top performance and turn-around time. The presentations describe where EDA meets practice under the most advanced nodes.

Thursday, June 7, 2012 from 11:00am to 12:00pm
My First Design Automation Conference – 1982
C. L. (Dave) Liu of Tsing Hua University and also the recipient of the 2012 Phil Kaufman award.

Dave tells us: “It was June 1982 that I had my first technical paper in the EDA area presented at the 19th Design Automation Conference. It was exactly 20 years after I completed my doctoral study and exactly 30 years ago from today. I would like to share with the audience how my prior educational experience prepared me to enter the EDA field and how my EDA experience prepared me for the other aspects of my professional life.”

I hope to see you all there!

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Hardware Configuration Management at DAC 2012

Hardware Configuration Management at DAC 2012
by Daniel Payne on 05-11-2012 at 4:54 pm
Categories: Cliosoft, EDA

Next month at DAC I plan to visit the ClioSoft booth to get an update on what’s new with hardware configuration management (HCM). Last year I met with Srinath Anantharaman to get an introduction to their company and how their tools are used by both front-end engineers and back-end IC layout designers.

Srinath Anantharaman, ClioSoft CEO

A new product last year called Visual Design Diff proved useful to teams that needed to answer the question, “What Just Changed on my Transistor-Level Schematic?”

This year you can use Visual Design Diff to look at the entire design hierarchy of your chip, quite a leap from just one cell at a time comparisons available last year. Hierarchy is used on every chip design, so I’m eager to see this capability in the tool at DAC.

Many IC design teams use the Cadence Virtuoso schematic capture and layout tools, so ClioSoft has integrated into both the latest OA based tool using Virtuoso 6.x and the previous release of Virtuoso 5.x using CDBA.

Don’t feel left out if you don’t use Cadence tools, because ClioSoft has integrated their HCM tool called SOS with the most popular IC tools like:

  • Cadence Virtuoso
  • Mentor ICstudio
  • Springsoft Laker
  • Synopsys Custom Designer

The product demos that I’ve seen show that you access the HCM features by simply clicking a drop-down menu choice for Check-In or Check-Out. Users that I’ve interviewed tell me that their designers come up to speed on using the SOS tool on the same day that it is installed, while the CAD manager responsible for setting it up takes maybe a week to learn it.

Other features to look for in a HCM tool are:

  • Version Control
    • Files and directories
  • Composite Objects
  • Concurrent checkout, branch and merge
  • Tagging
  • Snapshots
  • Work area release management
    • Copy work area
    • Linked work area
    • Isolated or shared
    • Revision search order
    • Rollback changes
    • Hierarchical reference and reuse
  • Architecture Choices
    • client-server architecture
    • Remote cache server
    • Smart cache technology
    • Push and pull updates
    • Repository
  • User Experience
    • GUI
    • Command line interface
    • Non intrusive
    • Production tested
  • Communication and collaboration
    • Collaboration icons
    • Triggers
    • Audit trail
    • Attributes and metrics
    • Integration with bug tracking

Summary
It’s time to add ClioSoft to your list of DAC companies, especially if your team does transistor-level design. There’s a page at the ClioSoft site where you can sign up for a meeting to get your questions answered and learn in more detail.

Other HCM companies at DAC this year are Methodics and IC Manage. As a side note, on Google if you search for “ClioSoft configuration management” you see a paid ad for IC Manage:

We’ve blogged before here at SemiWiki on how IC Manage competes with other companies on the web using competitor names.

Also Read

IC Layout Design at Qualcomm

More Growth in EDA

What Changed On My Transistor-Level Schematic?

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♫ If you are going to San Francisco, be sure to….

♫ If you are going to San Francisco, be sure to….
by Paul McLellan on 05-10-2012 at 8:00 pm
Categories: Uncategorized

Well, you can wear flowers in your hair if you like, but it is a bit sixties. However, here are some things that I do recommend that you be sure to do.

Some of these recommendations require you to find a given numbered pier. The Ferry Building at the end of Market Street is effectively pier 0. Odd numbers go north (including pier 1½ ). Even numbered piers go south (although many are missing). I used to live near pier 40 and would regularly meet people trying to find pier 39 which is a couple of miles away.

See the Golden Gate Bridge. The best way is not to drive there or get a taxi, but to rent a bicycle (lots of places on that side of the city, try Googling “blazing saddles”) and cycle across the bridge. You can then go down the hill into Sausalito. There is a regular ferry back from Sausalito to San Francisco and you can take your bike on it. Or you can keep going to Tiburon and get the ferry back from there.

Take a Tour of the Bay but ignore the official tours of the bay. Just take the ferry to Sausalito (from the Ferry Building or from pier 41), have a drink or a bite to eat, and get the ferry back. Cheapest bay tour available and voted the #2 most exciting ferry ride in the world by the Association of American Travel Writers (Kowloon to Hong Kong is #1 so rather a long way to go).

Ride a Cable Car. But don’t wait in line for 40 minutes at Union Square or Fisherman’s Wharf. Instead, go to the cable car barn on the corner of Washington and Mason. This where the whole system is driven from and you can watch the engines hauling the miles of cable under the streets. Also a museum of everything cable car. And then when you have finished, you can just get on a cable car without needing to stand in line, and go back downtown. The best ride is not to sit but to stand on the outside and hang on.

Don’t go to Fisherman’s WharfandPier 39. Everybody who lives here will tell you it’s not worth it. OK, so you are going to go anyway. Then at least go and see the Musée Méchanique on Pier 45. It is a huge selection of coin-operated antique arcade machines. It is free although you’ll presumably spend at least a few quarters in the machines.

Go to Golden Gate Park. The most interesting things are the Conservatory of Flowers, the de Young Museum (closed on Mondays) and the Japanese Gardens and tea room. If you are a literary buff there is a garden containing every plant mentioned in Shakespeare. The California Academy of Sciences is also there but at $30 entry per adult it is very pricey. But if you are around on Thursday evening, it is open for only $12 with bars and music and without the place being overrun by school groups since it is adults only.

See Chinatown. Here’s the best way to do it. Go to Union Square. Go shopping if that’s your thing. Then leave Union Square on Stockton Street and walk through the Stockton Street Tunnel. When you come out at the other end you are in the back of Chinatown and it is like you have landed in another country. Stockton Street is the non-touristy part of Chinatown, full of food shops and the like. Go down the hill one block to Grant Street if you feel the need to buy the sort of things tourists like to buy in Chinatown.

Go to Alcatraz. Warning: you must book a few days in advance. You will not get tickets if you just show up. Really. Much the best is to take the night tour, which leaves around 6 and gets back around 9. There are fewer people on the island and you get to watch the sun set through the Golden Gate. The ferry leaves from pier 33. You can buy tickets online.

The Exploratorium is the original hands-on science museum. Next year it moves to piers 13 and 15 but it is currently still at the Palace of Fine Arts, 3601 Lyon Street. Obviously it is a great place to take kids but anyone will find it interesting.

Finally a few shops with some history:

  • City Lights Books founded in 1953 and closely associated with Allen Ginsburg and the other beat poets. A publisher as well as a bookstore, and now an official historic landmark. 261 Columbus at Broadway. Website.
  • 826 Valencia, the Pirate Store. It is actually a place for helping kids 6-18 with their writing skills, but they were in a space zoned for retail so they had to be a store too. They decided to be a pirate supply store. And they are. The story is told in this TED video. They have websites: Writing, Pirates.
  • Good Vibrations, female friendly sex-shop since 1977. One block from Moscone, 899 Mission Street at 5[SUP]th[/SUP] and 2 other places. And a website.
  • The Wok Shop. If you want a wok or any Asian-cooking-related tool, for over 35 years there has been nowhere else. 718 Grant Street between Sacramento and Clay. Website.
  • Rainbow Grocery. Food co-op since 1975. Totally San Francisco sustainable, local, organic. vegetarian. 1745 Folsom Street. Worth going just to see it, even if you are unlikely to be doing your food shopping there as you are a tourist. Don’t forget to take the bus. Website.
  • Ferry Building Farmers’ Market. On Saturday morning. The quality and range of the produce is extraordinary but you won’t save any money, even compared to Whole Foods. Go early if you want to have fun trying to spot celebrity chefs. In the parking lots around the Ferry Building where Market Street ends at the bay.


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DAC: Chevy Volt Teardown

DAC: Chevy Volt Teardown
by Paul McLellan on 05-10-2012 at 7:03 pm
Categories: EDA, Events

One DAC panel session that I am looking forward to attending is the Chevy Volt Teardown. This takes place at 1.30-2.30pm on Tuesday June 5th at the DAC pavilion (aka booth 310). Al Speier will be talking about a teardown that they did at Munro Associates where he is a senior associate. Unfortunately they won’t actually be tearing down a Chevy Volt on the show floor. That would be a clever trick in an hour for a start. But you can see Al do it in just 4 minutes on a time-lapse video.

The battery is huge, 435lbs, shaped in a big T under the rear seat and under the tunnel between the front seats (who knew a front-wheel drive car would have a tunnel for the non-existent prop-shaft!). It has its own cooling system. I have read that it produces 360V and has a capacity of 16kWhr (although it only has 10kWhr available for use since it never completely discharges or completely charges the battery). A horse-power is roughly a kW (actually 1HP=0.75kW) this means around 20 horse-power for an hour. But a normal car’s petrol engine has around 80-250 horsepower, admittedly at the tacho redline. According to Wikipediathe peak power of the electrical motor is 111kW, which is in that range, at which rate it would exhaust the battery in less than 10 minutes. Hmm. I guess when just cruising along the power demands must be an order of magnitude less. The all electric range is apparently 25-50 miles so less than an hour at freeway speeds which would fit. For reference, a gallon of gas contains around 36kWhr so three times the usable capacity of the battery. Gas really is incredibly energy-dense.

Apparently 40% of the value of the vehicle is in electronics with over 100 electronic control units (ECUs) of one sort or another. That’s a lot of compute power.

The Volt charges the battery like any hybrid through regenerative braking. And, as you probably know, it can be charged from a 110V outlet or a special 220V charging station. Plus, it has a regular gasoline engine that also can charge the battery. Unlike a hybrid, only the electric motors drive the wheels, the gasoline engine only drives a generator to drive the wheels and recharge the battery.

Munro’s website is here.

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RTDA at DAC: Scale to Millions of Jobs

RTDA at DAC: Scale to Millions of Jobs
by Paul McLellan on 05-10-2012 at 7:00 pm
Categories: EDA

RTDA is all about enterprise level scalability. Their three main products all scale to be able to handle the most demanding needs of large companies with large farms of servers. Of course there are some new refinements too.

LicenseMonitor can scale to 70,000 simultaneous checkouts with 1 billion checkout records in the database. There are new reports and support for postgres.

NetworkComputer scales to millions of jobs in the queue, thousands of cores being managed, hundreds of license features. Come and find out about license overbooking. Many jobs, such as simulation, don’t use their licenses 100% of the time. Just as statistical multiplexing means that, say, 20 phone calls can fit in 18 channels (there is always someone not talking), NetworkComputer can start additional jobs that statistically will be able to get licenses most of the time when they need them (otherwise they have to wait). And so 20 simulation jobs can run with only 18 licenses.

FlowTracer can scale to hundreds of thousands of files and jobs with speed improvements in some cases of over 10X compared to the alternatives. There are improved interfaces to makeFiles.

So if you have demanding needs for keeping all those EDA licenses and all those servers humming along and working on the right stuff with the right priorities, then come by the RunTime Design Automation booth. Hey, you could win a Kindle Fire too.

RTDA is at booth 1508. To schedule a demo send email to info@rtda.com.

And talking of NetworkComputer, over here on LinkedIn there is an interesting discussion comparing NetworkComputer to IBM’s LSF product, the “500 pound gorilla” in the space. I don’t know how representative the people replying to the thread are, but the general consensus seems to be the NetworkComputer works better than LSF (increased license utilization), is cheaper than LSF (which is 3 times the price), and RTDA’s support is exemplary. If you are a NetworkComputer user who also has LSF experience then go and add your 2¢.

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Only slight growth in 2012 semiconductor market

Only slight growth in 2012 semiconductor market
by Bill Jewell on 05-09-2012 at 11:24 pm
Categories: Semiconductor Intelligence, Semiconductor Services
1 Comment

The world semiconductor market declined 2.2% in 1Q 2012 from 4Q 2011, according to WSTS. The market ended 2011 on a down slide, with 4Q 2011 down 7.7% from 3Q 2011. The year 2011 semiconductor market was up only 0.4%.

Three major events contributed to the weakness in 2011:

[LIST=1]

  • March 2011 earthquake and tsunami in Japan disrupted electronics and semiconductor production.
  • Floods in Thailand in 3Q and 4Q 2011 severely impacted electronics production, especially hard disk drives (HDD).
  • The European financial crisis resulted in weak demand in 4Q 2011.

    2012 will not likely see significantly different growth than 2011. Of the three major crises in 2011, Japan and Thailand have mostly recovered. However the European financial crisis continues. The affected nations have adopted a plan to overcome debt problems, but the austerity measures put in place will result in weakness in the European economy through at least 2012.

    The table below shows the available revenue guidance from the top semiconductor suppliers for 2Q 2012 versus 1Q 2012. The guidance is generally strong, with the top end of guidance for Intel, TI, ST and Broadcom around 10%. Qualcomm expects a decline, in line with its typical seasonal trends. Samsung expects a recovery in PC DRAM and increased demand for embedded flash memory. Our forecast at Semiconductor Intelligence is for 2Q 2012 semiconductor market growth of 6% over 1Q 2012.

    Semiconductor Intelligence’s forecast for the year 2012 is2% growth. Our prior forecast in February was a 1% decline, however 1Q 2012 was not as weak as we expected. Growth of 6% in 2Q 2012 followed by growth averaging6% in 3Q and 4Q drives the 2% forecast for the year. The chart below shows forecasts from the last two months. Most industry analyst firms see growth in the 4% to 7% range. Mike Cowan’s model based on historical WSTS data predicts a1.7% decline.

    Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers,foundries, suppliers, users or investors. Please contact me if you would like further information.

    Sincerely,

    Bill Jewell
    Semiconductor Intelligence, LLC
    billjewell@semiconductorintelligence.com

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    Apple Games Qualcomm’s 28nm Supply for Labor Day iPhone 5 Launch

    Apple Games Qualcomm’s 28nm Supply for Labor Day iPhone 5 Launch
    by Ed McKernan on 05-09-2012 at 11:17 pm
    Categories: Foundries, General

    You can see a lot just by looking – as Yogi Berra was quoted as saying. The past two weeks we have seen quite a bit that adds intrigue to the true nature of Qualcomm’s 28nm product shortage and how the effects will ripple through the mobile industry for the second half of 2012. Samsung’s bold announcement of their Galaxy S III smartphones was a message to the world that they intended to leap frog Apple in terms of products so they could attain market domination later this year. However, when one maps the delivery of the 4G LTE Galaxy (which is said to be July in the US) against Qualcomm’s ramp of 28nm products and the likely rollout of Apple’s product line, you will get the sense that Apple has an upper hand in the battle for dominance. Make no mistake, Qualcomm is sitting in a very strong position vis-à-vis other ARM vendors, however Apple has a call on most of its output into Q4 2012.

    When Qualcomm held its last quarterly earnings call, it revealed to analysts that it faced a severe shortage of 28nm supply for the next two quarters and into the December quarter, the height of the Smartphone selling season. As analyst peeled away the mystery with question after question, Qualcomm admitted the shortfall in this quarter was minor and that they would exit the September Quarter with 1/3 of their volume based on 28nm. There are two key products that Qualcomm is building for the mobile market. One of them is a 4G LTE baseband chip (MDM9615) and the other is the highly integrated Snapdragon S4 that includes a dual core ARM with graphics and 4G LTE baseband. Qualcomm stated they would need to bring on additional capacity at other foundries, which involve tapeouts. Apple is believed to be building its iPhone 5 with its own ARM (presumably A6) processor and the MDM9615. Samsung and it turns out HTC is signed up to use the Snapdragon S4. And this is where it gets interesting.

    Prior to Samsung’s Galaxy SIII announcement, they introduced their newest, low power quad core 32nm ARM chip for mobiles. It is slated for all of the Galaxy models but the one coming to the US. In other words to get 4G LTE, Qualcomm made them take the Snapdragon part. The assumption here was that the decision was made in March for a July launch, which impacted the 28nm supply situation.

    When Qualcomm announced their 28nm shortage, most analysts and myself included believed it was across the board and would as a result delay Apple’s iPhone 5 launch well into October and as a result effect Apple’s revenue in September and December quarters. The stock took an immediate hit. With the Samsung and HTC announcements, I am now more convinced that what happened is much more complex and reveals an underlying Apple strategy.

    The announcement of the new iPAD in early March with 4G LTE sent a signal that the entire Apple product line was going to include 4G LTE over the course of this year. So we should expect a June launch of Mac Books and Mac Airs with 4G LTE in at least the high end SKUs in combination with Intel’s Ivy Bridge ULV processor. I believe part of the reason for Intel’s delayed launch of the ULV version of Ivy Bridge was to get the marketing bang of the combination of 4G LTE with Ivy Bridge and no AMD or nVidia in sight. Be sure that Intel has communicated to Dell, HP and Lenovo that they need to upgrade their Ultrabooks with 4G LTE as well. So the frantic phone calls to Qualcomm for supply have been made. The line just grew.

    The biggest mistake that Tim Cook has made as a CEO occurred just two months into his reign when the launch of the iPhone 4S was pushed into early October. Because the event is tracked very closely and Wall St spies comb the supplier networks daily it is hard to keep the launch secret in the weeks leading up to it. Word spreads to the general public and customers hold off buying. And so the September 2011 quarter sales came in lighter than expected. Fear spread through Wall St. and Apple was in the dog house until the January blow out earnings.

    This year will be different. The iPhone 5 launch will occur right after Labor Day (September 3[SUP]rd[/SUP]) so that Apple can capture iPhone 5 revenue for the last 3 weeks of the quarter and smooth the revenue ramp between September and December quarters. Looking back, it was estimated that if Apple had pulled in their iPhone 4S ramp by two weeks last year they would have well exceeded analyst expectations for both September and December quarters.

    What does this have to do with Apple gaming Qualcomm. Apple’s product roadmaps are set at least a year ahead of time. I believe that they communicated their production ramp with Qualcomm in time for them to get enough wafers in the line to support the MacBook, MacAir and iPhone 5 ramps. Remember Qualcomm exits the September quarter with 1/3 of their units based on 28nm. That says the iPhone 5 phones are streaming out of the Apple stores in September in time for parents to outfit their kids headed off to school (it’s another form of the no child left behind program).

    In every supplier agreement, there are upside clauses or call options. They can be very dramatic to the point it could be 50% more volume in a matter of a few weeks times. I believe Apple got wind of Samsung and HTC’s 4G LTE launch plans for July and decided to exercise the call option for more product sometime in March or early April. This would mean Qualcomm diverted TSMC 28nm wafers to the production of MDM9615 baseband chips and not the S4 Snapdragon that is slated for Samsung and HTC. This meant that Qualcomm had to seek additional capacity outside of TSMC.

    If Apple dominates the 4G LTE markets for Smartphones, Tablets and mobile PCs then the playing field gets dramatically reduced going into Q1 2013. Qualcomm is a winner but they would rather have more customers in order to gain leverage in their long term pricing and supply model. For the rest of the mobile ARM camp, its going to be a long rest of 2012.

    FULL DISCLOSURE: I am long INTC, AAPL, QCOM, ALTR

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    Atrenta at DAC: Fast Lint, IP Kit and More

    Atrenta at DAC: Fast Lint, IP Kit and More
    by Paul McLellan on 05-09-2012 at 7:03 pm
    Categories: EDA

    Atrenta will have a new look this year at DAC. I’m not quite sure what that means but we’ll all just have to go along and find out.

    They have three users talking about their use of Atrenta’s tools. All 3 of these presentations are in the user-track poster session on Tuesday June 5th 12.30-1.30pm in room 105 (which is on the exhibit floor).

    • Udupi Harisharan of Cisco will talk about SoC power budgeting and optimization using RTL-spreadsheet power estimation of ASICs.
    • Cyril Vartanian of STMicroelectronics will talk about RTL restructuring with Atrenta Gensys.
    • Ramesh Rejogopalan of Cisco will talk about Prevention of data loss in physical implementation of FIFOs and datapath synchronizers.

    Atrenta’s CEO, Ajoy Bose, will discuss trade-offs and choices for emerging SoCs at the DAC management day. Tuesday June 5th from 2-4pm in room 309.

    Atrenta Fellow Ravi Varadarajan will participate in a discussion on standards for the 3D world during the Si2 Roundup. Monday June 4th 3.15-4.30pm in room 301.

    Of course Atrenta will be presenting their own tools in their booth, 2230. For details and to register go here.

    Finally, come and celebrate with Atrenta and TSMC on Monday evening from 6-7pm in room 303 in the Moscone Center and on the outdoor terrace. The TSMC Soft-IP Alliance has already certified IP from ten providers as SpyGlass Clean. So grab a clean non-Spy glass and fill it with beer or wine.

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    Customers Talk About Reliability, Low-Power and 3D

    Customers Talk About Reliability, Low-Power and 3D
    by Paul McLellan on 05-09-2012 at 1:13 pm
    Categories: Ansys, Inc., EDA

    At DAC in San Francisco this year, Apache once again have a mixture of presentations by customers on their use of Apache tools and presentations by Apache themselves on their products. Most of the customer presentations are given just once, but the product presentations are given multiple times over the three days.

    I think one of the hot topics at DAC this year will be 3D-ICs (TSVs etc). One on of the first places that 3D chips are being used is building stacks of memory die, so the Samsung experience looks especially interesting.

    Here is a list of all the customer presentations. The product presentations are interspersed between the customer presentations.

    • Samsung-DRAM: System-level Power Noise Analysis and Optimization with Measurement Correlation Results for Multiple DRAMs with TSV
    • UC San Diego: Considerations for Designing and Simulating Memory Interfaces for 3D/Stacked-die Designs
    • Renasas: Enabling Accurate and Efficient RTL Power Analysis and Optimization Methodology for Low Power Designs
    • LSI: Power Noise and Other Simulation Considerations for Energy-efficient SoCs
    • Samsung-SSI: A Chip-Package Simulation Methodology for Ultra-Large Low-Power Mobile ICs
    • Ciena: Power Noise Analysis with Silicon Correlation Results for Complex 32nm ASIC Designs
    • NXP: Full-chip Substrate Noise Coupling Analysis and Noise Isolation Structure Design Experiments
    • Aptina: Evaluating Design Options and Trade-offs through Full-chip Substrate and Metal Layer Noise Analysis for a Commercial Image Sensor Chip
    • AMD: Electrostatic Discharge (ESD) Simulation and Sign-off Considerations for Complex GPU and APU Designs
    • nVidia: A Dynamic Simulation Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events
    • ST-Ericsson: Simultaneous SI and PI Analysis for High-speed IO Designs for Mobile Applications

    Full details, including the presentations times and a short summary of each presentation are here. If you are interested, then you can register to attend on the same page.

    One other event is at the pavilion panel (booth 310) at 10.30 on Monday where Aveek Sarkar of Apache is one of the panelists on a panel called Power to the People, along with Clive Bittlestone of TI and Robert Patti of Terrazon Semiconductor.