Roaming around the hall at ARM TechCon 2012 left me with eight things of note, but one of the larger ideas showing up everywhere is the Xilinx Zynq. Designers are enthralled with the idea of a dual-core ARM Cortex-A9 closely coupled with programmable logic.
Continue reading “Zynq out of the box, in FPGA-based prototyping”
There is obviously a lot going on in 3D IC these days. And I don’t mean at the micro level of FinFETs which is also a way of going vertical. I mean through-silicon-via (TSV) based approaches for either stacking die or putting them on an interposer. Increasingly the question is no longer if this technology will be viable (there are already production designs) but when it will go mainstream.
The most informative conference I’ve attended on this is held in December. This year it is in Sofitel in Redwood City (down near the Oracle towers) from December 12-14th at the end of this week. If you are interested in this area at all then you should be attending. I was planning on attending myself (they gave me a press pass) but I’m actually going to be out of town.
This meeting is not focused on EDA, although it does cover that. It covers the entire ecosystem and all sorts of issues around who does what on the supply chain, how you keep wafers from breaking once you’ve thinned them (glue them onto something else) and so on. It gives the best overview of all the issues of anything I’ve been to.
I won’t try and summarize the whole agenda, you can look at it for yourself here (pdf). But the first morning is all keynotes, all the time, from 8-10.30:
Online registration still seems to be open here.
You can’t have failed to notice that 20nm is coming. There are a huge number of things that are different about 20nm from 28nm, but far and away the biggest is the need for double patterning. You probably know what this is by now, but just in case, here is a quick summary.
Lithography is done using 193nm light. Today we use immersion lithography (so instead of the gap between the wafer and the last lens being an air gap it is water). Amazingly, when you think of what you learned in high-school physics (young’s slits, diffraction gratings, never mind anything you might have learned about quantum mechanics) this worked down to 28nm and we could print the features needed with light with 6 times the wavelength. But at 20nm it doesn’t work any more.
Double patterning requires two masks. There are variations on the approach but for 20nm (probably not true for future generations) we split the polygons on the mask into two sets (this is known as coloring since that is what graph-theorists call this sort of thing). Each mask goes through a lithography cycle and we end up with photoresist that has been exposed to both masks. The reason we can just use one mask is that diffraction effects on that one mask would mean the exposure wouldn’t work. It is a light problem, not a problem of manufacturing what gets exposed.
So the new step is separating the polygons on the masks into two groups that are all double the minimum pitch. If you think of a bus just running parallel signals across the chip, then the odd ones go on one mask and the even on the other. But in more complex cases this may not work. It is simple to think up cases where A has to be on a different mask from B (because they are too close) and B has to be on a different mask from C, but that polygon C also goes close to A so it has to be on a different mask from A. Impossible (or we use triple patterning but that is not economic although we will get there if EUV doesn’t work effectively).
But there is another problem. The two masks are not self-aligning (there are self-aligning approaches which will be needed in the future, but for now it looks like most double patterning will be the simpler, aka cheaper, approach). So sidewall capacitance between two adjacent polygons will be much more variable than before depending on whether the masks are at the maximum allowed misalignment in one direction, versus the other direction, versus ‘typical’ meaning perfectly aligned. So a verification methodology that is color aware is needed to get useful parasitic information that can be used to close the design (timing, power, signal integrity, reliability and so on are all affected by this variability).
Synopsys has been working with TSMC and there was webinar presented by both companies to go into the details. The presenters are Anderson Chiu of TSMC and Beifang Qiu from Synopsys. Anderson is the program owner of the TSMC 20nm reference flow (I bet he gets lots of calls from EDA marketing folks). Beifang is the senior R&D manager for StarRC extraction.
Since both presenters are Chinese the webinar was presented not only in English but also in traditional and simplified Mandarin (the difference is in the slides not the language). I’m assuming that all 3 versions of the webinar will be online soon. The Synopsys home page for the webinar still links back to the registration. And if you are interested in that kind of thing, Synopsys and TSMC have a joint press release about the methodology here.
HP buys Autonomy for $11B then does an $8.8B writedown?!?!?! Was HP swindled by Autonomy? As a long time HP customer I’m outraged by this behavior. Not just the over priced acquisition but the behavior of HP on a whole! Even today 4 of the 6 laptops in my house are HP as are my printers. How am I supposed to buy HP products with a straight face after this?
Having friends at Oracle, HP, and Autonomy, this virtual reality show interests me and is a continuing humorous email thread amongst friends. Humorous, as in we can’t believe this is happening!
The cast of characters all have one thing in common, they all should have known better:
Raymond J. Lane Executive Chairman since 2011
Mr. Lane has served as HP’s Executive Chairman since September 2011. Previously, Mr. Lane served as HP’s non-executive Chairman from November 2010 to September 2011. Mr. Lane has served as Managing Partner of Kleiner Perkins Caufield & Byers, a private equity firm, since 2000. Prior to joining Kleiner Perkins, Mr. Lane was President and Chief Operating Officer and a director of Oracle Corporation, a software company. Before joining Oracle in 1992, Mr. Lane was a senior partner of Booz Allen Hamilton, a consulting company. Prior to Booz Allen Hamilton, Mr. Lane served as a division vice president with Electronic Data Systems Corporation, an IT services company that HP acquired in August 2008. Mr. Lane also is a director of Quest Software, Inc. and several private companies.
Given Ray’s depth of experience how does he get duped into acquiring Autonomy for an inflated price? The same could be said for the entire HP board who in my opinion should be held accountable for this $11B debacle.
The most interesting character is Frank Quattrone who represented Autonomy in this deal. I have written about him before, Frank handled the Synopsys acquisition of Magma.
Investment banker Frank Quattrone, formerly of Credit Suisse First Boston (CSFB), took dozens of technology companies public including Netscape, Cisco, Amazon.com, and coincidentally Magma Design Automation. Unfortunately CSFB got on the wrong side of the SEC by using supposedly neutral CSFB equity research analysts to promote technology stocks in concert with the CSFB Technology Group headed by Frank Quattrone. Frank was also prosecuted personally for interfering with a government probe.
To make a long story short: Frank Quattrone went to trial twice: the first ended in a hung jury in 2003 and the second resulted in a conviction for obstruction of justice and witness tampering in 2004. Frank was sentenced to 1.5 years in prison before an appeals court reversed the conviction. Prosecutors agreed to drop the complaint a year later. Frank didn’t pay a fine, serve time in prison, nor did he admit wrongdoing! Talk about a clean getaway! Quattrone is now head of the merchant banking firm Qatalyst Partners which is staffed with cronies and former CSFB people.
Another interesting note, Quattrone took Netscape public, Marc Andreessen co-founded Netscape, and Marc Andreessen is on the board of HP. The plot thickens!
Here’s a two sentence version of what happened based on what I have read and heard:
Simply stated, Autonomy over reported their product revenues by including services revenue as product sales at the time of the sale rather than at the time of the service. For example, if you sell a 5 year service agreement you are supposed to recognize that revenue over the five year period versus all 5 years up front. Revenue recognition 101, this really is the oldest trick in the M&A book.
Shame on Autonomy CEO Dr. Mike Lynch for allowing it, double shame on the auditors hired by HP for not catching it, but for me the blame sits squarely on the HP board of directors for not doing their jobs and protecting the stakeholders of HP. Just my opinion of course!
The internet is a funny place where rumors are true and truths are rumors. The latest one has Apple using Intel as a foundry. This is fuel for the rivalry between SemiWiki blogger Ed McKernan and me. Ed says Apple will use Intel, I say Apple will use TSMC, we have a very expensive dinner riding on this one.
TSMC falls on possible competition from Intel
Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest made-to-order chip-maker, fell yesterday on reports it may compete with Intel for Apple orders...
Yes, TSM stock took a hit based on a rumor so we have motive (Apple consumes more than 200,000 12-inch wafers per year). The Intel rumors started last year with Intel saying they would “like” to manufacture the Apple A4 and A5 SoCs. Clearly that did not happen nor will it. Moving an SoC amongst foundries is serious business, serious technical and political business.
Samsung and Intel manufacturing processes could not be farther from compatible. I work with Sagantec, the leading process migration company, and can tell you a migration between Intel and Samsung is not technically feasible. It would be a complete re-design. Apple uses Samsung IP. Apple uses commercial EDA tools certified by Samsung. The ROI is not there for Apple to move the Apple Ax SoC between fabs.
Let’s not forget how Apple became a fabless semiconductor company. They first started with Samsung as an ASIC customer. Apple did the initial RTL design and tossed it over the wall to Samsung for IP integration and physical implementation. Apple then acquired P.A. Semi (Palo Alto Semiconductor) for $278M in 2008 which brought serious SoC design experience in-house. Do a quick search on LinkedIn and you will see quite a few PA Semi people are still at Apple. Apple has also made other acquisitions and investments in the fabless semiconductor ecosystem.
Politically it is a problem as well. Apple’s experience with Samsung, where a vendor (Samsung) directly competes with their largest foundry customer (Apple), will definitely change the way we all do business. Qualcomm is in the same boat with Samsung. Samsung was the largest Snapdragon SoCcustomer and now the Samsung Exynos SoC is replacing Snapdragon. I was at ISSCC when Samsung first presented a paper on Exynos and saw the question line queue up quickly with competing SoC engineers from QCOM, BCOM, TI, Apple, etc. Few if any questions were directly answered as is the Samsung way.
For the record, I have no problem with Samsung competing with customers by providing low cost alternatives. It is good for consumers. It is good for the consumer electronics industry. It is good for the semiconductor ecosystem. It will force Apple and Qualcomm to innovate and differentiate at the different pricing levels. I also have no problem with the resulting legal actions as it will force Samsung to innovate and differentiate rather than replicate. It’s all about the customer experience, better products at affordable price points, that is what business is all about.
Back to the Apple “TSMC versus Intel” debate:
Can Intel be successful in the foundry business? Of course they can but it will not happen anytime soon. It took Samsung 10+ years to get to the number 4 spot. Today Intel Foundry uses the ASIC business model like Samsung did in the early days. Customers throw RTL designs over the Intel wall for physical implementation. This helps Intel learn the SoC foundry business and it protects Intel process secrets. Moving forward Intel will have to develop a fabless semiconductor ecosystem (exposing process secrets) and forge EDA and IP partnerships with the likes of ARM.
Intel will also have to avoid the competing with customers conundrum. The Intel UltraBooks are a blatant copy of Macbooks. The Intel Atom will someday compete with ARM and don’t be surprised if Intel comes out with an SoC of their own. Sounds a bit like Samsung right? Deja vu all over again. TSMC on the other hand is a pure play foundry and does not compete with customers.
My bet is: moving forward Apple will use Samsung for 28nm (iPhone 5s) and TSMC for 20nm (iPhone 6). Intel certainly has a shot at 14nm and 10nm but never ever count out TSMC. If you want to bet a lunch on Apple manufacturing at Samsung or Intel for 20nm post it in the comment section. I will cover all lunch bets against TSMC.
Full disclosure: I can eat my weight in sushi!
Tim Cook’s strategy to disengage from Samsung as a supplier of LCDs, memory and processors while simultaneously creating a worldwide supply chain from the remnants of former leaders like Sharp, Elpida, Toshiba and soon Intel is remarkable in its scope and breadth. By 2014, Apple should have in place a supply chain for 500M iOS devices (iPhones, iPADs, iTVs and iPODs). Add in the near term foundry relationship with TSMC and it spells not just freedom but a true Vertical Operations independent from its number 1 competitor. Add to this the fact that Apple may soon be lower in cost, an inconceivable thought to most observers. How can Apple have lower cost than Samsung? This is the story of 2013-2014 as Tim Cook is attempting to put the last pieces in place to build affordable $200 iPhones and $250 iPAD Minis for the other half of the world that is currently unaddressed today (eg China Mobile and India).
A recent article in digitimes questions whether TSMC will have enough capacity to support Apple’s projected demand of 200MU while also servicing its other major customers like Qualcomm, Broadcom, nVidia and the rest of the leading edge silicon buyers. Will TSMC make the investment to capture all of mobile while Intel sits on three empty 14nm fabs? Not likely, unless Apple and Qualcomm write checks to guarantee the demand. Six months ago Qualcomm started down the path of diversification when demand skyrocketed and TSMC could not turn on a dime to fulfill. Tim Cook knows Jony Ive will continue to pump out great products at a more rapid pace in the coming quarters and try to deny Samsung and Microsoft an opening like in the past during summer lulls when yearly refreshes were still waiting in the wings. All that is holding Apple back is the global supply chain that is larger and lower cost than what Samsung has today.
Many in the press have spent the past 6 months talking about the transition taking place from Samsung to TSMC. They have overlooked how Apple is leveraging its Japan infrastructure to build LCDs, DRAM and NAND Flash at a time when the Yen is about to collapse. From the mid 1980s to today the Yen has appreciated by 300% relative to the dollar. Moore’s Law is a hugely deflationary force that requires a country to offset its Creative Destruction by inflating away its currency. So the US and half the world linked to the Dollar (including China) have prospered while the Japanese economy has contracted during these past 25 years. If the Yen drops dramatically from 80 to 120 or 150, as is necessary to restart their economy, then Apple will have the beginnings to its low cost strategy to outflank Samsung. A robust, high volume processor and baseband chip supply chain is all that remains.
When the Intel earnings call comes in January, I anticipate a number of analysts will demand a full accounting of the projected fab loadings for 22 and 14nm for 2013 and 2014. The timing of recent leaks on Intel and Apple negotiating a Fab deal is not unexpected. On the table are three 14nm Fabs that require no Apple capital investment to satisfy the demand beyond the 200MU that TSMC and Samsung can supply. Quite likely Apple has the opportunity to support more than 500MU additional units with Intel at current die sizes. But wait, Apple will get an extra shrink and significantly lower power in a move to Intel’s 14nm process. Therefore the Intel Fab option is really the one road available that catapult Apple beyond Samsung in their battle for market share leadership in Smartphones and Tablets. It is also the one option that is unavailable to Samsung.
Analyst Doug Freedman recently speculated that Intel and Apple are considering a Foundry partnership where the former agrees to build ARM chips for the iPhone while the latter will convert the iPAD to x86. It’s possible, but in the end I believe that three empty Fabs running 14nm Finfet is a much stronger religion than x86 architected chips. Intel would be happy with anything Apple wants built because there are tremendous sunk costs in place with the new fabs. This is where TSMC has to be cautious.
While Stacy Smith, Intel’s CFO, repeated at a conference last week that they don’t see PC volume falling again in 2013, there are hints that Ivy Bridge pricing has already been reduced to move the ultrabook price points down to sub $500. Smith also noted that 22nm Fab equipment is now being transitioned into 14nm fabs. The Ireland Fab may be on hold now, but in reality it is like an Aircraft Carrier waiting to be outfitted with Fighters. Six large Fabs are what await the combined x86 and Apple demand. Of the six, less than three are currently needed to support 350M PCs and 20M-x86 based Servers. Any slide in x86 demand just opens up more space for Apple and at lower prices.
At some point the operating margins building the A7 for Apple will cross above those of an Atom chip. Just to be clear, I am saying that an A7 will deliver more profit than an Atom chip when Sales, Marketing and Engineering costs are factored in for the latter. If Intel can sell Apple on its 4G LTE baseband, then the low cost, dual sourced processor and baseband supply chain will be complete.
Scenarios such as those above are only possible when markets are going through huge transitions. I am still intrigued by Intel’s decision to double its fab footprint back in 2010. What were the reasons for the boldness and is that view today still held internally. I can only speculate that they truly believed that they alone would get to 14nm while the rest of the industry faded.
Full Disclosure: I am Long AAPL, INTC, ALTR, QCOM
This is the second part of my discussion with Paul Traynar, Apache’s PowerArtist guru. The first part discussed sequential reduction capabilities. Part I was here.
There are two big challenges with doing power analysis at the RTL level. Firstly, how do you get an accurate enough model of what the design will dissipate given that you only have RTL and not gates or anything even more accurate. And secondly, what vectors do you use since you probably just have a lot of functional verification vectors and not a carefully hand-crafted set of a few vectors that exercise the design just right.
The reason that this is important is that underdesigning the power grid or choosing a package that cannot cope with the power will lead to reliability issues. On the other hand, overdesigning the power grid or choosing an unnecessarily expensive package affects the competitiveness of chip or the final system.
PowerArtist contains two approaches that address these issues.
The first is PowerArtist Calibration and Estimator or PACE. This analyzes similar designs and looks as factors such as net capacitance, which library cells are used, how the clock-tree is implemented. There is a bit of a chicken and egg problem the first time through with a new process or a new design style, although usually data from earlier nodes can be used with some judicious scaling.
PACE turns out to be surprisingly accurate, with an accuracy at RTL within about 15% of post-gate physical design with parasitics.
The second approach in PowerArtist is the RTL Power Model or RPM. This is a reduction of the design to the critical factors that can then be used in a tool like RedHawk to analyze the power grid, package selection and perhaps even PCB noise issues. The challenge is to get vectors that represent realistic worst-case scenarios. This has to be done by using information in the RTL to identify power critical situations.
RPM is generated using whatever vectors exist. By examining how the vectors interact with the design it is possible to reduce the number of vectors to just a few critical ones that get the circuit into a critical state. For example, analyzing peak power in the presence of high average power (which tends to drain the decaps) or finding vectors that have very high changes in current when, for example, large parts of the design come out of clock-gating and start to toggle. The RPM captures how the circuit behaves during these critical periods which can then be used to stress other parts of the design and ensure reliability.
While Paul was over from UK he also recorded an educast on Power Budgeting Using RTL Power Models.
MIPS is one of the most prolific, longest-living industry-standard processor architectures, existing in numerous incarnations over nearly three decades.
MIPS has powered products including game systems from Nintendo and Sony; DVRs from Dish Network, EchoStar and TiVo; set-top boxes from Cisco and Motorola; DTVs from Samsung and LG; routers from Cisco, NetGear and Linksys; automobiles from Toyota, Volvo, Lexus and Cadillac; printers from HP, Brother and Ricoh; digital cameras from Canon, Samsung, FujiFilm, Sony, Kodak, Nikon, Pentax and Olympus; and countless others.
At the heart of MIPS is its RISC (reduced instruction set computing) instruction set, which was an entirely new concept for computer architecture at the time of its inception in the early 1980s.
The basic idea of RISC is that using simple instructions, which enable easier pipelining and larger caches, can dramatically boost performance. The emergence of high-level programming languages and compilers in the early 1980s enhanced this value proposition, making it possible for programmers to compile code into simple instructions that would execute extremely quickly.
Around that time, several other industry trends converged, creating an ideal environment for a disruptive company to bring RISC technology to market. These included the advent of the fabless semiconductor model, introduction of UNIX as an open, portable operating system, and proliferation of VLSI design in research labs, enabling increased experimentation with new ideas and technologies such as RISC. You can read more about these trends in a transcript of a 2011 Computer History Museum panel, MIPS Oral History Panel Session 1: Founding the Company.
In 1981, Dr. John Hennessy at Stanford University led a team of researchers in building a new microprocessor using RISC principles – this was the MIPS project.
Technologists John Moussouris, Edward “Skip” Stritter and others then joined Hennessy in 1984 to commercialize the MIPS project, through the creation of MIPS Computer Systems, a fabless semiconductor company that was the first to produce a commercially available RISC microprocessor.
MIPS’ value proposition was in providing high performance at low cost. In retrospect, the benefits of RISC may sound obvious, but at the time, RISC represented a fundamental philosophical shift. The MIPS team not only had to develop and sell a new product, but they also had to evangelize a new design philosophy.
The company’s first chip design, the R2000, was released in 1985, based on the MIPS I Instruction Set Architecture (ISA), and the next design, the R3000, was released in 1988. It was used primarily in SGI’s workstations, and later in workstations and servers from DEC. Based on its growing traction, in 1989, MIPS Computer Systems went public. The R6000 was then introduced based on the MIPS II ISA. In 1991, MIPS released the world’s first 64-bit microprocessor, the R4000. This design was extremely important to MIPS’ biggest customer, SGI, and as such, SGI bought MIPS in 1992. SGI subsequently incorporated MIPS as a wholly owned subsidiary, MIPS Technologies, Inc. It was during this time that SGI introduced its IRIS Crimson product, the first 64-bit workstation, which was featured in the movie Jurassic Park. More about this on Wikipedia here and here.
Over the next several years, MIPS introduced the R8000, R10000 and other processor variants. With each generation, more functionality was added to the MIPS architecture. During this time, MIPS began licensing its processor designs to other companies. By the late 1990s, the MIPS architecture continued to proliferate, and in 1997, the company shipped a record-breaking 48 million units. Riding on this momentum, SGI spun MIPS out as an IP company, with a business model based on licensing its architecture and microprocessor core designs. MIPS Technologies, Inc. subsequently held an IPO in 1998. You can get more in-depth information on the history of MIPS from Wikipedia here.
Around this time, MIPS introduced the 32-bit MIPS32® ISA and the 64-bit MIPS64® ISA – compatible architectures that leveraged the previous MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V releases. With this move, the privilege resource architecture (PRA) and ISAs were standardized, laying the foundation for future innovation.
Since then, the MIPS architecture has continued to evolve, adding numerous innovations including a 64-bit floating point unit for 32-bit CPUs, multi-threading, DSP support, microcontroller-specific extensions, the microMIPS™ code compression ISA, enhanced virtual addressing (EVA) and much more. With Release 5 of the MIPS architecture, the company is rolling out hardware virtualization and SIMD support.
Of course it’s not all about the elegance or capabilities of the ISA. Today, ecosystem is everything. Over the nearly three decades of its life, a large infrastructure of supporting development tools, operating systems, applications, middleware, device drivers and more have grown around MIPS. Support continues to grow, including initiatives such as Linux, Android, Java, JavaScript, HTML5, WebGL, GNU and LLVM toolchains, apps, games and more.
MIPS licensees have shipped more than 3 billion units since 2000. The ever-evolving MIPS architecture is inside of a large range of products, including the majority of DTVs, set-top boxes and WiFi routers shipping today. With the advent of the open, portable Android OS, MIPS is also now shipping inside of mobile devices. As intelligence is increasingly designed into just about every product from thermostats to high-end consumer products, the embedded microprocessor market is thriving, and the MIPS architecture continues to evolve to meet the needs of new generations of products while maintaining its simple, elegant RISC roots. For more info: www.mips.com.
I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the panel even more efficient, the audience was great, with Joachim Kunkel from Synopsys and Philippe Quiniot, STM Group VP, IP Sourcing & Strategy, or Marc Miller, VP Marketing for Tabula, to name a few very active participants.
There are many ways to introduce such a question; I propose to start with my first slide, just to position the problem. Subsystem IP is a great idea, I am sure everybody will agree with the concept, but could it be another one of this great story which end up falling, like Transputer, Gate Array integrating FPGA or Structured ASIC IP Platform? If you prefer to position the problem in a positive way: how should the industry proceed (I mean, vendors AND customers) in order to keep this Subsystem IP alive and growing?
Hal Barbour and Bill finch from CAST have decided to be specific, and to talk about “Platform” instead of Subsystem IP, and have taken a “CPU Subsystem” as an example. I am not sure that I agree with the “Platform” concept, but I must say that some of the Subsystem IP are CPU based, like for example the “ARC based sound system IP” from Synopsys. Why do I am not convinced by Platform for an IP vendor? Just platform sounds to me like a frozen system, and this probably means a lack of flexibility, and something which is “over-designed” if to be used by a variety of customers. Some of these customers will pay for extra gates that they don’t use…
To immediately answer to my objection, I am sharing with you a slide presented by Philippe Quiniot during the morning keynotes, and this picture clearly shows that STM think they should go toward Unified Platform development! Nevertheless, you should notice that these platforms will be developed by STM, for STM internal product group needs… In other words, STM does not expect any IP vendor to provide such a complex, and complete, platform…
Sonics has proposed a view of Subsystem IP which is more Application Specific, showing the Integration trends for Smartphones and Tablets, extracted from a Gartner report. This picture could be representative of the roadmap of the various chip makers addressing this market segment (it’s a bit early to know if integration will effectively happen this way, right?), but it can be used to raise one of the next big question which has been debated during the panel, differentiation.
Imagine that you are an IP vendor who decides to trust Gartner and build various Subsystem IP according with this roadmap, then go to sell these products to the chip makers active in Smartphone and Tablets segments… you may be successful with the companies developing me-too products. But the leaders, the Qualcomm, Nvidia, STM, will tell you that what they expect, above right performance and good deliverables, supposed to be their basic needs, is differentiation.
As mentioned by Peter Hirt “It’s all about differentiation”, and “Subsystems developed by IP vendors are available to everybody”. And conclude the slide by saying that “…Customer may select subset of Subsystem…” The important word here is “subset”! That means that an IP vendor may decide to develop a complete subsystem, to prove being a competence center for a given area, but may end-up selling only a subset.
We should link this comment with the very interesting assertion made by Martin Lund (made during the morning keynotes, and again during the panel): IP reuse is an Oxymoron and Fallacious!
That Martin did say is that Cadence has never sold exactly the same version of an IP function to two different customers, and this was, by the way, confirmed by other IP vendors. Why? Because customers need to differentiate, and to do it, they will always need highly configurable IP. Does that mean that Subsystem IP concept is dead? Not at all, but be sure it will be configurable enough to allow differentiation!
Finally, I will end up with my last slide (above), trying to remind some of the basics if you want to build a Subsystem IP business case. About the reasons why great ideas like Transputer or ASIC integrating FPGA blocs have failed in the past: Moore’s Law for Transputer, as it was possible to build very complexes CPU a few years later, and over-cost for the second great idea. So we could add “Lack of Differentiation” for Subsystem IP, if IP vendors forget to insert high configurability to allow for differentiation…
When I told you that this was a great panel, you can trust me, or read this extract from an Email of Hal Barbour, who has organized the panel, “I received numerous compliments from audience members of how great the panel discussion was. And I spoke to Gabriele this morning and she also told me that use had heard favorable comments too. It was clear that we had a group of people that were experts in this subject matter…”
Eric Esteve from IPNEST
Sign up for a free webinar on December 11 on Accelerating Yield and Failure Analysis with Diagnosis.
The one hour presentation will be delivered via webcast by Geir Eide, Mentor’s foremost expert in yield learning. He will cover scan diagnosis, a software-based technique, that effectively identifies defects in digital logic and scan chains. as well as recent advancements in diagnosis technology and industrial case studies. There is time after the presentation for Q&A and further discussion.
Topics to be covered include:
Who should attend:
