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Engineer to Engineer, Embedded Instrumentation

Engineer to Engineer, Embedded Instrumentation
by Daniel Payne on 01-03-2013 at 10:28 pm
Categories: EDA

Last month the folks at Tektronix did something very useful, they invited 30 engineers to talk directly with their chief engineer of embedded instrumentation as part of “Meet the Experts” in Santa Clara, CA.

Brad Quinton, Chief Architect created a new and efficient approach of embedding instrumentation in your ASIC design when doing an FPGA prototype. His start-up company was called Veridae and they were acquired by Tektronix in 2011.

Don Dingee and I have been blogging about this new technology for a few months now:


Most EDA companies today will buffer their development team from the actual end-users in hopes that the marketing folks can keep everyone happy and productive. Only the start-up companies allow their developers to directly meet and interact with the engineers that could use the technology, and the rewards are great:

  • Deeper understanding of what the technology can and cannot do.
  • Tips on how to best use the software.
  • Frank discussion on the philosophy behind the software and the approach used.
  • Confidence in the expertise level of the developer.

At the December 11th event there were engineers from several companies leanring about Tek’s new software called Certus 2.0:

  • Infinera
  • Cisco
  • Avago
  • Qualcomm
  • LumaSense Technologies
  • Simutest
  • Broadcom
  • Sandisk
  • A popular microprocessor company
  • Marvell
  • MicroSemi
  • Apple

If you’d be interested in attending the next “Meet the Experts” then leave a comment below and I’ll let you know when and where it will be held.

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Apple’s Next Threat

Apple’s Next Threat
by Randy Smith on 01-03-2013 at 9:30 pm
Categories: General

It seems only appropriate that at the beginning of the year we should look at who is going to be the next significant threat to Apple’s profitability machine. During Apple’s meteoric rise over the past 9 years (APPL share price: Jan-2004 @ $11 vs. Jan-2013 @ $550) different companies have been put up as Apple’s next significant threat or competitor. At various times we have heard that next impediment to Apple’s success is IBM, Samsung, Google, Sony, Intel, HP, Nokia, Microsoft, etc. The list is long, yet none of them makes much of a dent in Apple’s profitability or market cap. In fact, Apple’s market cap is more than twice any of those listed here and traded on Nasdaq.

One factor is that Apple gets its revenue from many sources – smart phones, laptop computers, desktop computers, tablets, media content, licensing, software, services, handhelds players (iPod), and peripherals. As of July 2012, about 73% of Apple’s revenue was coming from iPhone and iPad. None of these competitors above is in all of these markets. Apple leverages its broad base of revenue to target competitors in certain segments. Also keep in mind that margins vary by segment.


Figure 1. Apple Changing Revenue Mix

There has been tremendous concentration on Google as a threat to Apple. This comes from the fact that the ‘mobile internet’ is viewed as a fast growing and highly valued market. For Google, this is also a ‘special’ advertising conduit. The last similar market was probably the desktop operating system market in which Microsoft was a runaway winner. Many people predict that the mobile internet will also be primarily a winner-take-all-market. Microsoft failed at its first offerings in this segment and is hoping its latest offering will succeed – I doubt it based on what I have seen so far. The current war has multiple OS fronts – smart phone, tablets, home set tops, etc. But Google’s revenue comes primarily from advertising – wouldn’t that make Facebook a more significant competitor to Google? It doesn’t matter, Apple is taking all of the profits from the segment.

What I see is that these devices have moved well beyond being a smart phone. iPods are becoming less important for Apple since the same function is in the iPhone – plus the iPhone has a camera, movie player, eBook reader, etc. To top it off, all age groups seem to be adopting these new apps and devices. What do they have in common – media content. The iTunes store generates nearly as much revenue for Apple as Desktops and iPods combined, has better margins, and it is growing. There is no such uniform offering on Google. Google Music has been virtually ignored by the market. To compete with Apple you need some content. Google’s margins per phone are quite small and Apple users are not shying away from paying Apple’s higher prices. People have become accustomed to getting content from the Apple Store(s), both online and in the retail stores.

So, who has access to a lot of content? Who has entered or is entering the big markets of smart phones and tablets? The next threat to Apple is Amazon. They are working on a phone and they already have Kindle for the tablet space. Amazon’s phone is not out yet, but the rumors have been flying about Foxconn manufacturing them. Amazon’s LAB126 is working on an SOC. And Kindle Fire has been doing pretty well. Also extremely important is the growing area of cloud computing were Amazon has a huge presence and is way ahead in cloud apps and infrastructure. Apple’s cloud offering so far is small, at least in terms of features. Both of them have retail and distribution as well, which Google does not.

There are certainly a list of obstacles Amazon would need to overcome to compete well against Apple. The Kindle Fire is missing many of the apps people use on their smart phones. But in many ways, Amazon is ahead of Apple. If Amazon can build, borrow, and buy pieces to pull it together, Amazon could be bringing us their dominant electronic retail marketplace more integrated with our everyday lives. In doing so, they would build a more sticky following than the Android users who never seem quite happy.

Full disclosure: I am a happy iPhone, iPad, iPod, and Windows 7 user.

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Are you good at identifying languages? Win an iPad Mini

Are you good at identifying languages? Win an iPad Mini
by Paul McLellan on 01-03-2013 at 8:12 pm
Categories: EDA

Did you watch Atrenta’s holiday video (it’s only one minute)? Various Atrenta employees from all over the world wished you happy holidays in their own languages. Now Atrenta are having a competition. If you identify all the languages in the video then you can win an iPad Mini.

To enter the competition, or to view the video, go to this page. You have to enter by 11th and there are some other rules (like you can’t be an Atrenta employee).

Oh, and I turned off comments to this post just in case some of you decided to crowd-source the answer that way. No cheating, you have to do it on your own.

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HiFi Mini, Always Listening

HiFi Mini, Always Listening
by Paul McLellan on 01-03-2013 at 10:28 am
Categories: Uncategorized

Next week it is the Consumer Electronics Show (CES) in Las Vegas and so there are announcements around the areas where consumer overlaps with semiconductor, which these days is primarily mobile. Then in February in Barcelona is Mobile World Congress, which is even more focused on mobile. Expect more announcementst there.

Currently voice recognition like Apple’s Siri requires some additional activation such as pressing a button on the phone. Ideally voice recognition would be on all the time and so we could just talk. However, the power consumption required to do that with current processors is too high.

Today Tensilica introduced the HiFi Mini DSPcore targeted at “always listening” voice trigger and speech command. It is optimized specifically for the smallest area and lowest power in smartphones, tablets, appliances, and automotive applications. The HiFi Mini core enables a hands-free experience. Tensilica is working with Sensory and other software partners that will provide the voice-activation, speech command recognition, voice pre-processing and noise reduction products optimized on the HiFi Mini DSP.

Power is the single most important factor in enabling always-on listening capability in mobile devices. HiFi Mini is able to achieve just 400 uW running Sensory’s Truly HandsFree voice control technology. I think that we can expect more and more voice control over time as it migrates into all sorts of areas such as automotive and consumer appliances. Some of this is driven by the software side of things, but under the hood there is always the need for a very low power DSP to run the software since it is always listening.

If you are attending CES then Tensilica Tensilica will demonstrate Sensory’s Truly HandsFree voice trigger and speech command products on HiFi Mini at in booth MP25060.


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Integrating your SoC into the analog world

Integrating your SoC into the analog world
by Don Dingee on 01-02-2013 at 7:00 pm
Categories: EDA, Synopsys

Our world is decidedly analog, made up of stimuli for our five basic senses of sight, touch, hearing, taste, and smell, and more advanced senses like balance and acceleration. To be effective on the Internet of Things, digital devices must integrate with the analog world, interfacing with sensors and control elements.

Continue reading “Integrating your SoC into the analog world”

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The Semiconductor Landscape – II

The Semiconductor Landscape – II
by Pawan Fangaria on 01-01-2013 at 9:15 pm
Categories: EDA, GlobalFoundries, Synopsys

It has been a year since my article Semiconductor Landscape in Jan 2012 I wanted to look back into the major events over the year and then anticipate what’s in store going forward. What has happened over the year is much more than what I could foresee. Major consolidation in EDA space – Synopsys acquired Magma, SpringSoft, Ciranova, Eve; consolidation in semiconductor space – IBM acquired Texas Memory System, GlobalFoundries became independent of AMD, Micron is set to acquire Elpida and there were others. The point is that these consolidations are along the expected lines. One thing we have not seen yet is any indication of Qualcomm or Apple having their own foundries, although they could afford one profitably, if not for others’ designs, at least for their own needs. We may need to wait more to hear on that.

My tacit understanding in that article and still is that more consolidation will happen in coming years. Main reasons of consolidations are macroeconomic situation, business leadership, technology leadership and IP leadership. Let’s examine the scenarios from each of these perspectives and decipher from there what’s expected to happen –

Macroeconomics – In 2012, there is 3% decline in Semiconductor revenue, $298B from $307B in 2011, published by Gartner. And considering the unforeseen catastrophe of Fiscal Cliff, EU crisis and slowdown in BRICS, I am not hopeful of any real growth in economy in a few years from now, rather contraction is possible. The future is uncertain. If some corporate in US, baring a few like Qualcomm and Apple, are well capitalized, that is due to government and Fed pumping money into the system. In such a situation weaker hands will get hold of the stronger hands and thereby consolidation will happen. Another aspect is of meagre operating profit margins which, in order to improve the bottom line, will eventually force artificial robots to do routine work. Management tools will evolve for general book keeping of man power to reduce management overhead. Jobs will be measured by tools and paid accordingly, automatically.

Business Leadership – Here I would like to take a few examples. First comes to my mind is memory business which is faltering; low profit, high volume. We have seen the fate of Elpida. Micron, a strong leader in this space is coming for its rescue. Second, Freescale Semiconductor is not doing well and can be acquired, either in parts or in whole. Although it is narrowing down its losses, challenging future may initiate it to sell some of its lucrative portfolio in RF products and micro controllers which Qualcomm and TI would like to happily adopt. Another indication in business leadership we can see is that while majority of semiconductor vendors (e.g. Samsung, Toshiba, TI) had decline in their revenue Qualcomm and Broadcom had increase in their revenue. That’s a clear indication that while strong ones will emerge stronger, weaker ones will be subdued.

Technology Leadership – This is an interesting area where technology leaders are always in dilemma on what kind of services to be outsourced. When the technology becomes too complex as in the case of sub 20nm process, close collaboration between technology leaders (Foundry, EDA, Design) become necessary. Clear evidence is about Apple starting its own chip design team. That is also related to protecting IP but technology is the driver for better
efficiency. Eventually technology drives business and hence small and mid-size and weak players will either close or coalesce with strong technology leaders.

IP Leadership – This is a niche space where an IP owner can stay as long as it wishes or can survive. That’s the reason it has a separate unique space. ARM has established itself as a large IP leader and will continue. New IP leaders will keep on emerging and merging with other IP or technology leaders at their will.

By Pawan Kumar Fangaria
EDA/Semiconductor professional and Business consultant
Email:Pawan_fangaria@yahoo.com

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Wafer Costs: Out of Control or Not?

Wafer Costs: Out of Control or Not?
by Paul McLellan on 01-01-2013 at 8:30 pm
Categories: Events, Foundries, Intel Foundry, TSMC

I didn’t attend the International Electronic Device Meeting (IEDM) earlier this month, but there have been a lot of reports on the inter webs especially about 20nm and 14nm processes. Some of this is really geeky stuff but I think that perhaps the most interesting thing I’ve read about is summarized in this chart:

This shows the wafer costs (12″, 30cm wafers) for 28nm, 20nm and then 14nm with multiple patterning and, in purple, 14nm with EUV lithography. The chart comes from Luc van den Hove, chief executive of IMEC in Belgium.

These are raw wafer costs and thus haven’t been adjusted for the increase in transistor (and perhaps interconnect) density. Typically when we transition from one process node to the next, the wafer costs go up a little bit but that is completely dominated by the increase in how much we can put on a given sized die, and so the cost per transistor drops substantially. This is the economic driver of Moore’s law and is what makes it possible to have a $500 iPhone deliver more computer power than a 1980s mainframe that cost millions of dollars.

But these costs are going up dramatically. The Y-axis scale doesn’t start at zero so the picture is a bit misleading, 14nm costs are not three times 28nm. But they are nearly twice. If the process truly scaled everything then the density of transistors at 14nm would be four times that of 28nm so cost per transistor would still be falling fast. But increasingly the transistor length is only the headline number for the process and the interconnect is shrinking much more slowly, if at all. When you look at the pitches for various layers in a modern process it is impossible to see anything close to 2X the headline number.

So the key question is whether 14nm will have an economic driver or just a technology driver for those few designs that can truly take advantage of the increased density and decreased power, even though there may even be a cost penalty. For Apple’s iPhone and Samsung’s Android phones probably. For those $50 smartphones for developing countries that won’t work.

Despite the purple bar looking optimistic, the received wisdom is that EUV is now too late for 14nm and so we will have to have a lot of double and triple patterning instead (which is one of the things that drives the cost up so much). EUV works in the sense that you can flash some wafers but the current state-of-the-art seems to be about 20 wafers/hour versus the 100 or 200/hour that is required to make the approach viable. The intensity of the light source (droplets of tin zapped with a huge laser) is too low, the mirrors (which aren’t really mirrors in the usual sense) absorb too much of the light, and there are too many reflections required between the source and the photoresist. Not much energy makes it to the resist to make the exposure.

On a more optimistic note, Intel claimed that their costs per transistor were falling with each process node. Apparently they also don’t use double patterning at 20nm and there are two reasons for this. Firstly, they can have as restrictive design rules as they like, since they are the ultimate IDM with a limited product range. Secondly, most of the pitches at 20nm are not much different from 28nm. As I said above, only the FinFET transistor is 20nm or 22nm long.

Anyway, 2013 will be the year we find out what 20nm and 14nm really can deliver as these processes start to ramp up. As Yogi Berra said, “the future ain’t what it used to be.” (although you have to be careful with Yogi Berra quotes. As he also (maybe) said, “I didn’t say all the things I said.”)

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Happy New Year from SemiWiki!

Happy New Year from SemiWiki!
by Daniel Nenni on 01-01-2013 at 7:05 pm
Categories: General

It was an amazing year for SemiWiki and I would like to sincerely thank all who participated. SemiWiki traffic doubled again which is amazing in itself. SemiWiki membership more than tripled as we continue to add vertical markets (EDA, IP, Services, Foundry). More people are blogging on SemiWiki and the Forums and Wikis are coming to life. With millions of page views I can comfortably say that social media is now an integral part of the fabless semiconductor ecosystem.

What’s in store for SemiWiki in the new year? We will continue to grow with more original content, another vertical market (FPGA), and increased exposure through new partnerships with mainstream news carriers. Today more than 450,000 people read SemiWiki, in 2013 that number will exceed 1,000,000 people, believe it.

A significant challenge we continue to face as an industry, and I do not see this changing anytime soon, is the lack of understanding of what social media is really capable of. Seriously, most of the people in our industry simply do not get it. Admittedly, I probably would not get social media either if not for my four children as they have pushed me along. As a result I have spent a considerable amount of time on SemiWiki, LinkedIn, Twitter, FaceBook, and Google+ looking at the analytics and calculating the return on investment (ROI) for different activities.

As a career salesperson I can tell you social media is all about ROI. The most limiting factor of the sales equation is time spent educating customers on your technology and the resulting value proposition. If you call on an account that has never heard of your product or company the sales cycle can be very expensive. Back in the day we made cold calls and calculated the ROI. For example, you would have to call on 100 people to get 5 qualified meetings which today is an added expense that we as an industry cannot afford.

On the other hand, when a potential customer initiates contact (out of the blue) we call that a Bluebird, as in a sale just flew in the window which is a rare occurrence. Bottom line, social media is all about creating Bluebirds and compacting the sales cycle as much as possible.

White papers are a staple in our industry with webinars and live seminars being a close second and third. They are cost effective customer communication channels, invitations to collaborate, but also very important sales tools.

SemiWiki bloggers are industry professionals with 25+ years of experience. By day we work inside the fabless semiconductor ecosystem, by night we blog our opinions, observations, and experiences. In doing so, we drive qualified traffic to your whitepapers, webinars and seminars. This is a collaborative real time feedback loop and the ROI is easily documented. Work with us and Bluebirds will fly through your windows, absolutely.

Happy New Year and best of luck to you in 2013! It would be a pleasure to work with you, just fly through our window and we will take care of the rest.

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Cadence 3D Methodology

Cadence 3D Methodology
by Paul McLellan on 12-28-2012 at 8:20 pm
Categories: Cadence, EDA

A couple of weeks ago was the 3D Architectures for Semiconductor Integration and Packagingconference in Redwood City. Cadence presented the changes that they have been making to their tool flow to enabled 2.5D (interposer-based) and true 3D TSV-based designs. You know what TSV stands for by now right? Through-silicon-via, a (usually) copper plug that carries signal, power or clock from the front-side of the chip, through the thinned wafer, to the back where it can contact micro-balls on the die or interposer below.


The first people to do 3D designs managed to do it with tools that were unchanged, adding scripts and other modifications to fool the 2D tools into doing their bidding. After all, each die is a 2D design and can, in some sense, be done independently.

One of the biggest changes comes at the front of the design. Even assuming the partition between the different die has already been done (often because they are using different processes, memory or analog on one die, logic on another) there is still a lot that can be done to optimize the 3D structure. Many of the TSVs will end up being used to distribute clock or power with decap capacitors on the interposer. Having too many TSVs drives up the cost (and wastes area) and too few risks reliability failures or intermittent errors.


Since each die is largely designed independently of the others once these decisions have been made, the other big area that needs additional capability is verification. In particular, making sure that all the TSVs on the various die and interposers involved all line up, carry the correct signals and so forth. Not to mention verifying the power delivery network and the clock network behave as planned.


The final big area of difference is manufacturing test. Once the entire design is packaged up there is only access to the pins on the package. These only go to the interposer (in a 2.5D design) or the lowest die (in a 3D design). There is no direct access to the die above. So additional TSVs are required to build a test “elevator” that gets the scan patterns in through the pins and up to the level where they are used. Wafer sort, the forgotten child of manufacturing test, is also much more important in a 3D design due to the “known good die” problem. If a faulty die slips through wafer sort and gets packaged, not only is that die discarded (and it was bad anyway) but other die and interposers (which are most likely good) also get discarded. The cost of a bad die is that much higher than in a normal 2D design.

Of course there are many other issues in 3D other than EDA. It requires a whole new ecosystem and the details of who does what haven’t even all been ironed out yet. TSVs need to be created, wafers need to be thinned, microballs need to be placed, die need to be bonded together, packaged, bonded out, tested. And when all this is done, it needs to be economic to do it for volume production, not just an elegant price-is-no-object technical solution.