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Podcast EP208: A Conversation with This Year’s Kaufman Award Recipient, Dr. Lawrence Pileggi

Podcast EP208: A Conversation with This Year’s Kaufman Award Recipient, Dr. Lawrence Pileggi
by Daniel Nenni on 02-16-2024 at 10:00 am

Dan is joined by Dr. Lawrence Pileggi, Professor in the Department of Electrical & Computer Engineering at Carnegie Mellon University. Larry is the 2023 Phil Kaufman Award recipient for distinguished contributions to Electronic System Design. His pioneering contributions include circuit simulation and optimization that have enabled the industry to address the challenge of interconnect delay dominated designs, and for his innovations in Electrical & Computer Engineering education.

Dan explores Larry’s experiences and contributions over his storied career. His contributions to the industry are discussed, along with his views of the current state of EDA innovation and an assessment of the impact the next generation of researchers will have. Larry talks about the industry leaders he considers his mentors and also discusses how his academic career prepared him to play poker on a professional level.

Larry will be honored at the upcoming Kaufman Award ceremony and banquet on February 22 in San Jose, CA. You can register for the event here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

February 16, 2024February 20, 2024

Strong End to 2023 Drives Healthy 2024

Strong End to 2023 Drives Healthy 2024
by Bill Jewell on 02-16-2024 at 6:00 am
Categories: Semiconductor Intelligence, Semiconductor Services
2 Comments

The global semiconductor market grew 8.4% in 4Q 2023 from 3Q 2023, according to WSTS. The 8.4% gain was the highest quarter-to-quarter growth since 9.1% in 2Q 2021. This was also the highest 3Q to 4Q increase in 20 years, since an 11% rise in 4Q 2003. 4Q 2023 was up 11.6% from a year ago, following five quarters of negative year-to-year change.

The robust 4Q 2023 gain was primarily driven by memory. The major memory companies all reported healthy revenue growth in 4Q 2023 from 3Q 2023. In U.S. dollars, Samsung’s memory business was up 49%, SK Hynix was up 24.1%, and Micron Technology was up 17.9%. The weighted-average revenue growth in U.S. dollars of these three businesses was 33%. The weighted-average revenue growth of the twelve largest non-memory companies was 4% in 4Q 2023 from 3Q 2023. The highest increases of the non-memory companies were 17.7% from MediaTek, 14.2% from Qualcomm, and 10.4% from Nvidia. Seven of these non-memory companies had decreased 4Q 2023 revenue, with the largest declines being 10.2% from Infineon Technologies, 10.0% from Texas Instruments, and 8.0% from Analog Devices.

The outlook for 1Q 2024 revenue change from 4Q 2023 is mostly negative, except for the memory companies. Micron expects 12.1% growth. Samsung and SK Hynix did not provide specific guidance, but both indicated continuing strong memory demand. The nine non-memory companies providing revenue guidance projected 1Q 2024 declines ranging from 2.8% from Infineon to 17.6% from Intel. The expected decreases were blamed on seasonality, excess inventories, and weakness in the industrial sector.

The 2024 projections for key drivers of the semiconductor market help explain the divergent projections. Smartphone unit shipments were down 3.2% in 2023 but IDC expects them to rebound to a 3.8% increase in 2024. Smartphones drive revenue growth for the memory companies and for Qualcomm and MediaTek. PC unit shipments dropped a dramatic 14% in 2023. IDC projects PC growth of 3.4% in 2024. The PC rebound benefits the memory companies and the processor companies (Intel, Nvidia, and AMD).

The automotive and industrial markets have been major revenue drivers for several companies as other end markets have been weak. However, automotive production increases appear to be ending in 2024. S&P Global Mobility forecasts a 0.4% decline in production of light vehicles in 2024 following strong 9% growth in 2023. S&P says vehicle production and inventory restocking have satisfied post-pandemic demand and now exceed current customer demand. Global manufacturing (industrial production) is expected to moderate from 2.0% growth in 2023 to 0.3% growth in 2024 according to Interact Analysis. This indicates slower demand from the industrial sector. The slowdown in the automotive and industrial sectors primarily impacts STMicroelectronics, Texas Instruments, Infineon Technologies, NXP Semiconductors, Analog Devices and Renesas Electronics.

Global GDP is projected to rise 3.1% in 2024, the same as in 2023, according to the International Monetary Fund (IMF). Thus, the overall economy is not expected to show any significant acceleration or deceleration. However, some countries are showing weakness. The United Kingdom slipped into a recession with contracting GDP in the last two quarters of 2023. Japan also entered a recession after two quarters of GDP declines.

Gains in the 2024 semiconductor market will be driven by memory. WSTS forecast 44.8% growth for memory and 6.5% growth for non-memory, resulting in total market growth of 13.1% in 2024. Gartner assumed a 66% increase in memory in its forecast of a 16.8% increase in the total market. Memory will be driven by recoveries in the PC and smartphone markets. These two sectors will also aid the non-memory market, but other non-memory market drivers such as automotive and industrial will be weaker in 2024.

Against this backdrop, what is the outlook for the overall semiconductor market in 2024? Most forecasters expect robust growth, with IDC the highest at “above 20%.” Objective Analysis projects “below 5%” growth as they expect the memory boom will not be sustainable. Our latest forecast from Semiconductor Intelligence is an 18% increase. Other projections range from 10.5% to 17%.

Forecast contest winner

The final WSTS data for 2023 showed the semiconductor market declined 8.2% for the year. Going into 2023, the semiconductor market was certain to decline after each quarter of 2022 showed a quarter-to-quarter decline. Each year we at Semiconductor Intelligence award a virtual prize for the most accurate forecast made from November of the prior year through February of the forecast year (before the first WSTS data for January is released). 2023 forecasts released in November 2022 through February 2023 ranged from minus 3.6% to minus 22%. The winner for 2023 is Bill McClean of IC Insights (now part of TechInsights) with a forecast of minus 6%. Congratulations to Bill who retired at the end of 2022 after 42 years of following the semiconductor Industry.

Also Read:

Strong End to 2023 Drives Healthy 2024

CES 2024

CHIPS Act and U.S. Fabs

Semiconductors Headed Toward Strong 2024

February 15, 2024January 6, 2025

2024 Outlook with Laura Long of Axiomise

2024 Outlook with Laura Long of Axiomise
by Daniel Nenni on 02-15-2024 at 10:00 am
Categories: Axiomise, IP, RISC-V, Semiconductor Services

Axiomise pioneered the adoption of formal verification in the semiconductor industry since 2017. Led by visionary CEO, Dr. Ashish Darbari, who has 63 patents in formal verification, and Neil Dunlop an industry veteran with 40 years of experience, Axiomise has helped twenty customers over the last six years by providing them access to bleeding-edge formal verification methodology via its training programs, consulting & services and vendor-neutral formal verification app for end-to-end verification of RISC-V processors.

Tell us a little bit about yourself and your company.
Axiomise provides consulting & services, training and application-specific apps for RISC-V verification such as formalISA for deploying formal methods on complex SoCs. Through our abstraction-driven methodologies and six-dimensional coverage solutions that can be used with any commercial formal verification tool, our experts can tackle the most challenging formal verification problems on a wide variety of designs including RISC-V, Arm, or x86 processors, GPUs or video blocks, networking blocks including Wi-Fi, 5G, and AI/ML.

I am the Business Development Director of the firm and joined the team in February last year.

What was the most exciting high point of 2023 for your company?
One of the main highlights from last year was to work in super complex projects for some of the big names from Silicon Valley. A notable mention was from AMD.

We are proud to have achieved 100% conversions in designs with over billion gates, and to have worked with amazingly talented teams from different parts of the world.

We made a great contribution to our clients’ projects with some of the brightest design and people that we have hired in our team. Moreover, we were able to educate our clients’ teams through bespoke training programs that again are not only unique in industry but also widely regarded as the best. We also contributed directly through our formal methods applied in their designs on the power of formal, particularly when establishing “exhaustive proofs of bug absence” working all through the early design to the sign-off their projects.

On a different note, over the course of the last 18 months our headcount increased from 1 to 15 and our team prides to be hyper diverse and with a 50/50 male/female ratio. We strongly believe that diversity promotes creativity within any team and with the community around it!

What was the biggest challenge your company faced in 2023?
The story around validation & verification is not inspiring with the industry struggling to show improvements in best practice adoption as per Harry Foster’s Wilson Research Report revealing an ever-increasing number of simulation cycles and the astronomical growth of UVM is unable to prevent the ASIC/IC re-spin which is at a staggering 76% while 66% of IC/ASIC projects continue to miss schedules.

Our broad industry experience tells us that the best way of improving these statistics is to shift-left and this can be done by adopting formal methods early in the DV flow by understanding its true potential. While the use of formal apps has certainly increased over the last decade, the application of formal is still very much on the extremities. We find this to be the most formidable challenge.

Even considering that last year we grew our team by more than 50% and our clientele by a larger percentage, the biggest challenge for us was to keep patient with the industry’s pace for adoption of formal and with the time is taking many firms to understand the best practices to deploy formal efficiently and effectively!

How is your company’s work addressing this biggest challenge?
We aim to make the semiconductor community understand that formal verification is a necessity, not just a nice to have; and that UVM and simulation are complementary to formal methods in several areas of many silicon designs. We are doing this of course through hands-on project work on customer designs as well as deploying our formalISA app and training programmes.

What do you think the biggest growth area for 2024 will be, and why?
Everything from networking (5G/6G), RISC-V and accelerator chips for AI/ML would need rigorous verification that only formal methods rooted in great methodology can provide. This is where we see the most opportunities for growth.

How is your company’s work addressing this growth?
We are providing custom formal verification services to the industry by leveraging our expertise rooted in over 60+ years of combined formal verification experience in Axiomise lead by our CEO and CTO. The speed at which we can innovate live on a project to come up with expansive abstraction-driven methodologies has no parallel in the industry. It is something we are getting to hear more and more from our customers. We can crack the hardest problems that are not possible for everyone.

What conferences did you attend in 2023 and how was the traffic?
As our team Axiomise participated and sponsored some of the top-level international conferences and summits.

We had an intense fruitful year whilst attending and networking in the following industry events: ChipEx, the first run RISC-V Summit Europe in Barcelona, DVCon India, RISC-V North America and DVCon Europe.

The traffic and engagement of attendees and organisers was great! We enjoyed meeting and learning from many professionals working in the semiconductor industry from all over the world!

Will you attend conferences in 2024? Same or more?
We will be attending and sponsoring more conferences this year.

We are a confirmed sponsor of DVCon US on 4 – 6 March 2024 and look forward to connecting the semiconductor industry in California next month.

Also Read:

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®

A Five-Year Formal Celebration at Axiomise

Axiomise at #59DAC, Formal Update

February 15, 2024December 2, 2024

Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems

Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
by Mike Gianfagna on 02-15-2024 at 6:00 am
Categories: Alchip, Chiplet, Events, Semiconductor Services

Multi-die system design is clearly gaining momentum. Part of this momentum focuses on chiplets and a chiplet ecosystem. A “building block” approach for design will work better if there is a way to get verified, quality building blocks in the form of chiplets. The recent Chiplet Summit became an epicenter for this topic. The conference grew about 2X from last year’s event. Chiplets are a hot topic. IO and memory chiplets are foundational elements for any system and a presentation on this topic by two companies making significant investments in this area caught my eye. Read on to see how Synopsys and Alchip accelerate IO & memory chiplet design for multi-die systems.

Who Presented

Erez Shaizaf

Presenting from Alchip was Erez Shaizaf, the company’s Chief Technology Officer. He is an industry veteran who focuses on system technology solutions based on 25-years of experience in VLSI, hardware, and system engineering. He has performed numerous successful silicon reticle tapeouts on advanced technology nodes and high-speed interfaces.

Manmeet Walia

Presenting for Synopsys was Manmeet Walia, Product Director for Mixed-Signal PHY IP. I know Manmeet from my time at Synopsys. He has been managing mixed signal Interface IPs for HPC/Networking SoCs for over 14 years at Synopsys. Before that, he held marketing and system engineering leadership roles at AMCC, Exar, and Toshiba. Manmeet is quite knowledgeable and articulate.

This is a winning presentation team. Let’s see what topics were discussed.

About Multi-Die and Chiplets

There is a series of decisions to make regarding when it makes sense to move to multi-die design and what technology approach to take. The traditional approach of monolithic chip design will run into issues across a few areas. As the size of the die approaches the reticle limit, yield begins to suffer and the cost per die can become prohibitive. Now that multi-die integration strategies are becoming more available, splitting the design into multiple, smaller chips can be more cost-effective.

Beyond cost considerations are design flexibility and process optimization. The digital processing portion of a system may work best at the latest process node, but other parts of the system (memory or analog for example) will work best at different process nodes. Add to this the opportunity to acquire silicon-proven functions in chiplet form and design productivity and predictability can improve significantly. The figure below was presented to illustrate the continuum of choices.

The path to multi die

The presenters outlined the decisions across performance and cost to create an ROI for the various approaches. Several designs across monolithic, 2.5D and 3D were then examined. It turns out there are quite a few choices to be made in each case and the ROI can vary quite a bit. This part of the presentation was eye-opening regarding the depth of decision-making required to examine all options.

Moving to either a 2.5 or 3D approach does have challenges. Some of those discussed include:

Floor planning (TSV blockage)
Clock delivery & timing signoff
Power delivery
Physical verification
Thermal escape

In the area of chiplets, the following aspects were summarized:

Benefits

Performance
ROI
Reusability
TTM

Challenges

Complex package
NRE
Die-to-die limited bandwidth
Die-to-die power/latency

The conclusion was that there is no “one size fits all” solution. For each design, one must maximize the cost-performance ratio, which requires a custom-driven and not off-the-shelf approach. And there is a clear need for collaboration across EDA, IP, front-end, back-end, and package design.

Addressing the Design and IP Challenges

Both Alchip and Synopsys bring substantial capabilities to open a path to multi-die design. The approach for collaboration to help achieve multi-die system success from architecture partitioning, system design, IP integration, verification to high-volume manufacturing was explored in detail. The graphic at the top of this post is a good summary of how Synopsys and Alchip accelerate IO & memory chiplet design for multi-die systems. Here are some more relevant details for each company:

Regarding IO and memory chiplets, the value proposition was summarized this way:

Soft chiplet concept

Reference design completed ahead of customer inquiry
- I/O and memory chiplets
- RTL data base including verification suite as subsystem
- Software drivers
- Debug tools
Hardened for specified process node and package upon request
Configurations, die size and aspect ratio changeable

Value proposition

Splits monolithic SoC into chiplets
- Across multiple process nodes
- Across various packaging options
Fast time-to-market
Customers concentrate on core ASIC development
Synopsys tier 1 IP with proven Alchip implementation
Low risk – proven design and implementation

Alchip presented a new design platform called Chiptopia. The figure below summarizes the components of the platform.

Chiptopia design platform components

The framework is summarized this way:

Alchip, along with its customers, utilize the platform to collaboratively share design databases and workflows
Enterprise and cloud-based installation
RTL-to-GDS design automation
Supports 2D, 2.5D and 3D design flow
Use cases
- Augmented COT
- Resources augmentation

The main features include:

Process node selection
Application dependent
Design library comparison
P/G topology setups
Clock strategy testing

And the key value statements include:

Improved TTM
Risk & cost reduction

The conclusion of the talk touched on the fact that one size does not fit all for package type, aspect ratio, and functionality. The focus needs to be on maximizing the cost-performance ratio. And this requires a custom-driven approach, NOT and off the shelf strategy. The collaboration between Alchip and Synopsys was described in detail, including EDA, IP, front-end, back-end, and package design.

A soft chiplet platform was described that supports hardening per customer application and selected package with shortened time-to-market, development, and volume.

SoC chiplets and the package go together with this strategy. And that’s how Synopsys and Alchip accelerate IO & memory chiplet design for multi-die systems.

February 14, 2024January 20, 2025

2024 Outlook with Coby Hanoch of Weebit Nano

2024 Outlook with Coby Hanoch of Weebit Nano
by Daniel Nenni on 02-14-2024 at 10:00 am
Categories: IP, Weebit Nano

Weebit Nano is an Israeli semiconductor company that specializes in the development and commercialization of silicon oxide-based ReRAM (Resistive Random Access Memory) technology. ReRAM is a type of non-volatile memory that holds great promise for future computing and storage applications due to its potential for high density, low power consumption, and fast operation. I have known Coby for many years and it is a pleasure to work with Weebit, absolutely.

Tell us a little bit about yourself and your company
I started off as an engineer and spent my first 17 years on the engineering side, mostly in functional verification roles. I was part of the founding team of Verisity, where I made the switch to the business side, and have been in VP Sales and CEO roles for the past 27 years. I joined Weebit over six years ago, when it was still a small company with only two engineers. I am very proud of the progress we’ve made towards making Weebit a key player in the ReRAM space, with over 30 engineers and many supporting contractors.

Weebit is developing a new Non-Volatile Memory (NVM) technology called ReRAM, which is recognized today as the leading contender to replace flash technology in the future. Our ReRAM has a long list of advantages over flash, in terms of speed, power consumption, endurance, simplicity to manufacture, and most importantly cost to manufacture. Weebit ReRAM can scale down to advanced geometries, and is now fully qualified at 85⁰C and 125⁰C. We’re continuing to qualify our embedded ReRAM at higher endurance and temperature levels, broadening target applications as well as demonstrating the maturity of our technology.

We’ve already licensed our ReRAM technology to DB HiTek and SkyWater, and we are in ongoing evaluations and negotiations with other major foundries and IDMs. We’re also scaling our ReRAM down to more advanced geometries and are thoroughly testing the first 22nm chips embedded with our ReRAM and manufactured by GlobalFoundries.

What was the most exciting high point of 2023 for your company?
We achieved several major milestones in 2023. Qualifying our ReRAM at 125⁰C – the temperature required for automotive grade-1 and some industrial applications – was important since it demonstrates the suitability of Weebit ReRAM for high-temperature applications with lifespans of at least a decade. But perhaps the biggest highlight was the progress we made with major foundries/IDMs, culminating in the recent licensing agreement with DB HiTek, one of the top-10 foundries in the world. This is setting the stage for additional agreements in 2024.

What was the biggest challenge your company faced in 2023?
While it may sound counterintuitive, one of our biggest challenges in 2023 was our rapid growth. Over the past two years, the market began to realize that ReRAM is no longer a “future memory” – it is now a reality. In parallel, we qualified the technology and started signing licensing agreements. This presented challenges in needing to scale our workforce to meet prospect/customer expectations, including running multiple concurrent projects and evaluations at different process nodes and wafer sizes.

How is your company’s work addressing this biggest challenge?
We’ve been scaling the company in multiple ways, not just adding more people but also aligning teams together, forming new workgroups, and collecting/analyzing data for effective IP reuse and product alignment. One of the great things about Weebit is that we are strong across all the key disciplines needed to create a leading memory company. We have world-class talent across the four key ReRAM disciplines – device physics, process and materials, analog and digital design and algorithms, and test and characterization. I believe we have broader expertise than any other standalone ReRAM provider. This is all supported by our extremely experienced Board of Directors, including Dadi Perlmutter who led development of the Pentium while at Intel, Atiq Raza who helped push AMD to its leading position, and Yoav Nissan-Cohen who co-founded Tower Semiconductor, among others.

What do you think the biggest growth area for 2024 will be, and why?
I believe 2024 will be the year of ReRAM. There is a huge vacuum in the market which needs to be filled. Now that people know ReRAM is available and realize its great potential, practically all the world’s foundries and IDMs are looking for a ReRAM solution.

At Weebit, we are providing a licensable embedded ReRAM solution that foundries can easily add to their IP portfolios and semiconductor companies can easily embed in their SoCs. We’re seeing a great deal of interest in areas such as power management ICs, wearable medical devices, aerospace and defense, edge AI and automotive solutions.

How is your company’s work addressing this growth?
To address the growing demand for ReRAM across a broad range of applications, we are setting up a strong sales organization which will work with these foundries/IDMs and expand to others. We are already engaged in evaluations, negotiations and other activities with the majority of the top foundries and IDMs. At Weebit, the quality of our team and our singular focus on ReRAM ensures we are well placed to become the leader in the burgeoning ReRAM domain.

What conferences did you attend in 2023 and how was the traffic?
In 2023 we attended shows including Embedded World in Germany, the Design Automation Conference (DAC) in San Francisco and CSIA – ICCAD in China. These conferences were successful for us, generated many good leads, and enabled discussions with partners. While floor traffic was not always strong, the fact that we arranged many meetings in advance, along with the strong interest we are seeing in ReRAM, created a situation where the booth was full at almost all times.

Will you attend conferences in 2024? Same or more?
In 2024, we will once again attend Embedded World in Germany, and we will extend our activities to include exhibiting at the first Embedded World North America, which will be held this autumn in Austin. The interest we are seeing in ReRAM is worldwide, and the United States is no exception, so we look forward to meeting with many potential customers and partners at that show. Some of our team also attended CES in Las Vegas, and we plan to expand this activity next year.

Additional questions or final comments?
Thank you, Dan, for continuing to share industry developments through SemiWiki. It’s good to catch up with you.

Also Read:

ReRAM Integration in BCD Process Revolutionizes Power Management Semiconductor Design

A preview of Weebit Nano at DAC – with commentary from ChatGPT

How an Embedded Non-Volatile Memory Can Be a Differentiator

February 14, 2024February 25, 2024

Moderating Our Open Chiplet Enthusiasm. A NoC Perspective

Moderating Our Open Chiplet Enthusiasm. A NoC Perspective
by Bernard Murphy on 02-14-2024 at 6:00 am
Categories: Arteris, Chiplet, IP

I recently talked with Frank Schirrmeister (Solutions & Business Development, Arteris) on the state of progress to the open chiplet ideal. You know – where a multi-die system in package can be assembled with UCIe (or other) connections seamlessly connecting data flows between dies. If artificial general intelligence and industrial-scale quantum computing are right around the corner, surely any remaining issues in open chiplet design should be a snap to resolve? According to Frank, the answer is yes and no. For a couple of privileged groups, anything is possible and is being put into practice today. For larger open markets, not so much, at least not in the near term.

Courtesy of Arteris

Multi-die systems and proprietary solutions

Multi-die systems address the never-ending demand to build bigger and more complex systems (for LLM processing as one example) when constrained by a number of semiconductor limitations: you can only fit so much logic on one die; some functions like analog and DRAM work best in processes which are not optimal for logic; and even if you could somehow fit more onto a single die, yield would plummet and costs would soar.

Within the last year or so, Intel, AMD, and Nvidia all released processor products based on chiplet architectures. What is unique to these products in this context is that these companies each built all their own chiplets, together with the infrastructure and connectivity assembling them into a full multi-die system. They have no dependency on external chiplet providers or external chiplet-to-chiplet communication IP providers. By controlling everything internally, and guiding their suppliers accordingly, they can tune and validate the systems they built in-house against their own extensive suites of tests. Some other very large vertically integrated companies may also fall in this class. I am told that Meta may now be one of these, and I would be surprised if Apple was not also handling all their own multi-die design.

For anyone else wanting to build a multi-die system, this is all interesting but still amounts to a proof of concept. Works very well for Intel, AMD, and Nvidia but more is needed for systems builders who don’t have that level of control. While UCIe (among other options) should, in principle, take care of die-to-die communication, reality suggests the challenge is not yet conquered.

By the way, there is also a parallel trend; Printed Circuit Boards (PCBs) are getting smaller. Here the industry has seen many different types of packaging approaches, and users are used to integrate multiple dies on substrates for designs that don’t challenge the reticle limit mentioned above. Both trends converge on chiplets, albeit with different design methodology approaches – miniaturized PCBs vs. co-designed or interoperable bare pieces of silicon.

Open chiplets and interoperable communications interfaces

In theory, using standards like UCIe for inter-die communication should resolve communication problems between die, essential to enable a true open chiplet ecosystem. If this works as advertised, then chiplets should be able to communicate even if they come from different chiplet vendors, are built in different foundries, etc. Unfortunately, compliance with the standard is proving a necessary but insufficient condition to ensure interoperability between two sides of (say) a UCIe link. While the PHYs can be checked via eye-diagrams, there is still variability in ways to pack data from protocols like AXI and CHI to streaming interfaces like CXS and from there to FDI, UCIe’s streaming interface.

This is not a revelation. In the PC world, wired and wireless communications and other domains, standards compliance is step 1. Plugfests to prove real-world interoperability between vendors is a next step. For cellular communications, network operators require detailed interoperability testing against their requirements. It seems a similar infrastructure is needed for chiplet communications, although that may be a little more challenging because you can’t plug a connector into a chiplet. Frank tells me he hears plans are in the works but are not expected to become mainstream any time soon (it took PCIe a while too). The industry has announced early cases of just UCIe interoperability, between Intel and Synopsys for instance.

One class of systems builders has a simple answer to this problem. They are powerful enough to force their suppliers into converging compliance on their design. If something isn’t working in their use cases, the potentially guilty parties dig down and must come up with a resolution. Some big automotive OEMs are in this class, also some big HPC enterprises. Problems found here are likely to be small differences in expectations for margins, buffering, and other parameters not fully nailed down by the standard. Or just bugs not covered in chiplet/IP vendor use-case testing. Whatever the problem, the suppliers must sort it out. It’s good to be king when you want to build a chiplet-based design.

For everyone else

Getting to interoperability today depends on where each of your inter-die connections falls in the big and constantly evolving matrix of proven/covered communication pairs considering IP/PHY sources, specification differences, and use-case differences (coherent versus non-coherent links). Symmetric pairs (everything the same on both sides) should (?) be fine, but asymmetric pairs are a gamble unless proven in production. According to Frank, this challenge is especially visible from the NoC world. He says customers ask if the Arteris NoC works with a particular UCIe Controller IP. Reasonable question you would think.

But the NoC talks to a protocol to stream converter, which then talks to a PHY. That communicates through a link to a PHY on the second chiplet, then to a stream to protocol converter, then to the NoC on that chiplet. Everyone is fully compliant with the standard, but still the link doesn’t work – unless it has been proven to work in production. Much tighter interoperability testing will eventually solve this problem, but that may be 5 years out. In the meantime, Arteris and customers are filling in cells in the interoperability matrix one (or maybe a few) at a time.

Bottom line, chiplets are real, totally under control for the vertically integrated system builder, evolving rapidly under autocratic customers, and inching forward for everyone else. You can read more HERE.

February 13, 2024February 12, 2024

2024 Outlook with Stephen Fairbanks of Certus Semiconductor

2024 Outlook with Stephen Fairbanks of Certus Semiconductor
by Daniel Nenni on 02-13-2024 at 10:00 am
Categories: Certus Semiconductor, IP

Certus Semiconductor is a unique company. Their customer centric business model ensures customer success at many levels. Certus is staffed by a team of IO and ESD experts that go above and beyond what you can get from free libraries, protecting your designs and your customers products from the risks of electrostatic discharge.

Tell us a little bit about yourself and your company.
My name is Stephen Fairbanks; I am classically trained as a semiconductor analog and RF circuit designer, specializing in designing and developing process-specific I/O and ESD libraries for over 25 years. I led the development of the ESD and I/O libraries for Intel’s wireless, cellular, and mobile computing groups for many years in the early 2000’s. I have been an ESD and I/O consultant since leaving Intel in 2006 as part of SRF Technologies. In 2009, I established Certus Semiconductor in partnership with Freescale’s I/O and ESD teams and Markus Mergens of QPX. When NXP acquired Freescale, the partnership dissolved, but I maintained the rights to the Certus Semiconductor brand and continued building the business, which has been quite a journey. Certus Semiconductor has expanded its IP offerings to include I/O libraries and ESD solutions in many foundries from 180nm to 11nm, with current research and development into more advanced nodes.

What was the most exciting high point of 2023 for your company?
The year 2023 was a great one for Certus Semiconductor. We were fortunate to sign the most contracts of any year since inception, onboarding several key new customers and signing new contracts with several long-term customers. Aside from the sheer volume of deals, the year’s high point was entering into a partnership with a new foundry to develop foundational IP for key process nodes. While Certus has a long history of developing I/O libraries for foundries, this will be the first time we have built a standard cell low-leakage library and our standard foundational IO Library IP. We’re excited to establish a long-term relationship with a foundry and develop their IP offerings.

What was the biggest challenge your company faced in 2023?
With the growth we experienced in 2023, we faced the challenge that all small businesses eventually have to face: learning how to scale. In years prior, Certus had not taken on so many projects or engaged with so many customers. This growth has led us to expand the team and improve the efficiency of our processes.

How is your company’s work addressing this growth?
We have addressed our growing pains in several ways. We have expanded the team, hiring several vital individuals. We brought on a COO towards the end of 2022 and onboarded some new additions to the engineering team in 2023. In addition to expanding the team, we have forced ourselves to become more formal in our internal and external procedures to Certus. The number of new projects we signed in 2023 has forced us to modify and update how we were doing things, which is all part of learning and growing a business. However, the key to this growth is maintaining responsiveness, agility, and flexibility in serving our customers. We have always taken great pride in being able to work with customers to optimize our solutions for their products. This responsiveness always requires a significant level of iterative interaction; we do not want to lose this. Still, being nimble and flexible as support teams grow is challenging.

What do you think the biggest growth area for 2024 will be, and why?
We see our most significant growth area in 2024 as expanding our LVDS portfolio and our multi-protocol GPIO Libraries. We have developed specialized LVDS IP in several foundries and in many process nodes ranging from 130nm and 65nm down to 12nm. This is not your standard multi-gigabit SerDes; there are many good companies in this space, and we collaborate with many of them. We are not attempting to compete with them. Instead, our LVDS is specialized for applications such as radiation-hardened Spacewire, reliability-hardened LVDS interfaces for Industrial products, or ultra-low power IoT spaces as well. We have also developed a few specialized ultra-low power LVDS interfaces for die-to-die interconnect.

In addition to this, our multi-voltage/multi-protocol I/O Libraries see increased interest. Customers are looking to create flexible I/O banks that can interface to many possible standards, including I3C, I2C, DDC, HPD, AVI, SPI, eMMc, ONFI, RGMII, etc., and at many voltages, ranging from 0.9V to 3.3V, and even 5V, all with a single I/O design. Creating these flexible I/O banks is a design space we have become very adept at.

What conferences did you attend in 2023, and how was the traffic?
We attended several conferences last year. We attended DAC for the third year in a row and were pleased with the traffic we received. We were also able to see old colleagues and build new relationships. I presented at the Siemens U2U conference, discussing Certus’ experiences and successes utilizing the Siemens Analog FastSPICE platform. Additionally, Certus received the opportunity to present at the TSMC OIP Ecosystem Forum in Santa Clara, California, and Tokyo, Japan. I presented, in partnership with Siemens, on the topics of High Voltage (>10V) RF and Analog Interfaces for Standard Low Voltage CMOS TSMC Processes and Multi-Protocal and Electrical I/O Flexibility Catered for Automotive and Mobile Applications.

Will you attend conferences in 2024? Same or more?
We will return to DAC in 2024, this time with a larger space. We hope to have equal or more traffic than last year, reconnect with old colleagues, and build new relationships. We will also be attending GOMACTech in March. It will be our first time attending, so we hope to have some good traffic and build new relationships.

Additional questions or final comments?
As Certus grows, we look to continue improving our IP and developing new leading-edge solutions at existing and smaller nodes. We aspire to be the go-to provider for I/O and ESD solutions. We enjoy working closely with our customers and always want to engage with other forward-thinking companies. Contact info@certus-semi.com or visit us at www.certus-semi.com to get started!

Also Read:

Unique IO & ESD Solutions @ DAC 2023!

The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries

CEO Interview: Stephen Fairbanks of Certus Semiconductor

February 13, 2024February 12, 2024

ESD Alliance and Silicon Assurance Host Industry Panel Discussion on Chiplet Security

ESD Alliance and Silicon Assurance Host Industry Panel Discussion on Chiplet Security
by Bob Smith on 02-13-2024 at 6:00 am
Categories: Chiplet, Events, Security

Phishing,,E mail,,Network,Security,,Computer,Hacker,,Cloud,Computing,Cyber,Security

Security threats are a hot topic of discussion today as they can have a profound impact on the electronic infrastructure and devices that are the backbone of our global economies. It is also clear that these threats can be introduced during the design of the very devices that we rely on in our daily lives.

Chiplet-based design is growing rapidly and the industry is recognizing that security measures must be taken during the design flow to ensure that security threats are not introduced — whether inadvertently or with malicious intent. These threats generally fall into one of two categories. The first are the unintentional hardware threats (circuitry) that may be a byproduct of automated circuit design technologies used to create complex chips. The second category includes hardware, such as trojans, that are maliciously and deliberately added to the design and can lay hidden within the design until triggered by specific signals or patterns.

Chiplets can come from many different sources and simultaneously the industry demand for new chiplet-based designs is accelerating. The industry needs to come to grips with the fact that the threats are real and that bringing security to the design flow is critical. Achieving this will require industry input, collaboration and consensus on supporting best practices and technologies for combatting these security threats.

The ESD Alliance, a SEMI Technology Community, and ESD Alliance member company Silicon Assurance are hosting an industry panel and discussion webinar Thursday, March 14, from 9 a.m. – 10 a.m. PST. The panel discussion will be moderated by Raj Gautam Dutta, CEO and co-founder of Silicon Assurance, a company focused on addressing trust and security assurance in the chip design flow.

Panelists come from a broad cross-section of the chip design industry and will discuss the threats that can occur during the various stages of the design flow and during assembly and test. They will also consider the latest advancements and different approaches that can be employed to safeguard the future of chiplet-based design.

The panel includes Swarup Bhunia, Semmoto Endowed Professor and Director of the Warren B. Nelms Institute; Steve Carlson, Director/Solutions Architect, Aerospace and Defense Solutions at Cadence Design Systems; John Hallman, Digital Verification Technology Solutions Manager for Siemens EDA; Serge Leef, Head of Secure Microelectronics at Microsoft; Salman Nasir, Senior Technical Program Manager from Battelle; and Ming Zhang, Vice President of R&D Acceleration at PDF Solutions.

Please join us for a better understanding of the magnitude of the potential threats and how the industry can come together to address them.

Registration for the virtual webinar Chiplet Security—Current and Future is free. Registration details can be found on the ESD Alliance website.

About The ESD Alliance

Hosting webinars and other educational events is part of the ESD Alliance’s charter to promote the growth of the electronic system design industry, including promoting small, innovative businesses and improving the efficiency of large and small companies. I encourage you to learn more about the ESD Alliance, a SEMI Technology, and recommend your company become a member if it is not one already. We represent members in the electronic system and semiconductor design ecosystem as the marketing advocate and address economic issues affecting the entire industry. We act as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry.

If your company is already a SEMI member, consider becoming a member of the ESD Alliance by submitting a short application with no extra fee. If your company is not a SEMI member yet, it can apply at the same time to join the ESD Alliance. No additional membership dues are required to become a member of the ESD Alliance. Contact me at bsmith@semi.org or Paul Cohen at pcohen@semi.org if you have questions.

Also Read:

Information Flow Tracking at RTL. Innovation in Verification

Rugged Security Solutions For Evolving Cybersecurity Threats

Cyber-Physical Security from Chip to Cloud with Post-Quantum Cryptography

February 12, 2024November 25, 2024

Sustainable Development: Connected Devices and the Role of Flexible Semiconductors

Sustainable Development: Connected Devices and the Role of Flexible Semiconductors
by Kalar Rajendiran on 02-12-2024 at 10:00 am
Categories: Foundries, Pragmatic Semiconductor

Global Goals for Sustainable Development

The ambitious United Nations Sustainable Development Goals (SDGs), from reducing food waste to enhancing global healthcare access, hinge on a connected world where every object whispers valuable data. As technology strives to address environmental challenges, healthcare needs, and promote responsible consumption, traditional integrated circuits (ICs) are facing limitations in emerging applications. While traditional ICs power our smartphones and computers, their mechanical rigidity and environmental footprint create hurdles in achieving sustainability for emerging applications.

Vision of the Future Connected World

Item-level Intelligence

Item-level intelligence involves enabling individual items or products to collect, store, and transmit data through sensors and communication capabilities. This concept is particularly relevant in the Internet of Things (IoT) and connected devices, providing valuable information about an item’s status, location, and usage. For instance, in retail, smart tags on products enhance inventory management, while in healthcare, sensors on pharmaceuticals ensure proper storage conditions. In addition, health monitoring systems can become more sophisticated by leveraging wearable devices for continuous data analysis and personalized health recommendations. For example, smart patches could help prevent strokes through early detection of heart arrythmia.

Overall, item-level intelligence improves visibility, traceability, and efficiency across various industries and applications.

Smart Packaging

Smart packaging, a transformative concept, involves integrating intelligence into packaging to monitor food freshness, for example, or optimize healthcare item handling. Challenges such as cost, chip scarcity, and environmental concerns with traditional semiconductors hinder adoption. An alternative solution is flexible semiconductors, offering customizability and a lower carbon footprint, providing a viable path forward. At the forefront of this wavefront stands Pragmatic Semiconductor, a UK-based company pioneering the technology. Pragmatic’s flexible Integrated Circuits (FlexICs) use thin-film transistor (TFT) technology in combination with conventional semiconductor processing to deliver the world’s most complex flexible circuits.

FlexICs

These ultra-low-cost circuits can be shaped to a millimeter-range radius of curvature without impairing functionality. FlexICs enable ease of addition of item-level intelligence at large-scale. FlexIC fabrication omits many of the resource-intensive stages of silicon semiconductor manufacturing, resulting in a single-site production process that is not only faster but also de-risks against a globally disaggregated supply chain, thereby promoting semiconductor sovereignty and onshoring production. Single-site production provides environment-friendly benefits as well, as discussed below.

Environmental Impact and Customization

FlexICs also boast a lower environmental impact compared to traditional silicon, since the simplified production requires less water and energy, and fewer hazardous chemicals, compared to silicon fabs. It also produces no PFASs – per- and poly-fluoroalkyl substances, otherwise known as ‘forever chemicals’. This aligns perfectly with the UN’s push for sustainability.

Traditional semiconductor supply chains can span several geographies. The single-site production process of FlexICs eliminates the air miles a standard silicon chip is likely to rack up as it jets around the world from the fab to the packager to final assembly.

Market Opportunities Galore

The IoT has connected our devices, but the future lies in the Internet of Everything (IoE), where every object, from furniture to clothing, interacts and shares data. FlexICs, with their adaptability and affordability, are the perfect bridge between these two domains. Imagine bendable displays integrated into shaped walls or smart fabrics that monitor our health. They’re the possibilities FlexICs unlock, paving the way for a truly interconnected ecosystem. Imagine wound dressings that not only protect but also monitor healing in real-time, sending data to doctors for personalized care. Use of microscopic smart sensors in “in vivo” applications for gaining crucial medical insights is a strong possibility, with of course FDA (or other country-specific equivalent) approvals. This is the healthcare revolution FlexICs bring, democratizing access to data-driven care and transforming the way we diagnose, treat, and prevent diseases.

The Pragmatic Revolution

Pragmatic’s solutions empower businesses to harness the power of flexible integrated circuits. FlexICs offer a compelling alternative to legacy-node chips, providing sufficient performance for simple tasks. The company’s rapid production method enables quick iteration of designs and chip production within weeks, accelerating time to market for IoT devices. By utilizing flexible semiconductors for tasks where “just enough” performance suffices, silicon can be freed up for high-end applications. This approach not only enables rapid, high-volume production through localized fabrication but also yields significant savings in production time, materials inventory, and transportation costs. In essence, FlexIC fabs offer the opportunity to achieve semiconductor sovereignty at a fraction of the cost, time, and resource consumption of traditional silicon fabs.

Summary

As the semiconductor industry aligns its trajectory with UN’s SDGs, FlexICs emerge as a catalyst for transformative change. Pragmatic’s dedication to providing sustainable solutions in diverse applications exemplifies the profound impact of FlexIC technology. The journey from traditional ICs to FlexICs signifies not only a technological evolution but a step towards a future where technology seamlessly integrates with our lives, fostering innovation, sustainability, and connectivity across industries.

For more details, visit www.pragmaticsemi.com

Also Read:

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February 12, 2024March 7, 2024

Outlook 2024 with Dr. Laura Matz CEO of Athinia

Outlook 2024 with Dr. Laura Matz CEO of Athinia
by Daniel Nenni on 02-12-2024 at 6:00 am
Categories: AI, Analytics, CEO Interviews

Laura Matz is also the Science & Technology Officer of Merck KGaA, Darmstadt, Germany. She has always been a key contributor to the growth in semiconductor materials, driving a strong R&D presence to enable business growth.

Laura is a strong advocate for young talent in science and engineering. As a leader, she builds teams to find innovative solutions to the problems facing humanity and implement them with the discipline and rigor to create the greatest impact. In 2023, she joined SEMI Impact for Skills as a board member, a governance program to support upskilling and reskilling, to attract new talent, and to unlock EU and national/ regional funding. In addition, she is a board member of AIChE (American Institute of Chemical Engineers), a leading organization for chemical engineering professionals.

Laura has a Ph.D. in Analytical Chemistry from Washington State University and an undergraduate degree from the Indiana University of Pennsylvania.

Tell us a little bit about yourself and your company.
I have a dual role: CEO of Athinia and Chief Science & Technology Officer at Merck KGaA, Darmstadt, Germany.

Athinia is a secure data analytics platform for collaborating on relevant information from materials and equipment suppliers, device makers, and fabs in the semiconductor industry, with the goal of improving decision-making, minimizing quality deviations, and increasing efficiencies. With the proliferation of digital technologies, there is immense pressure on the semiconductor industry to produce with zero defects and deliver new innovations to market faster. The immense amounts of data produced today create opportunities for not only a single company but for the entire value chain to achieve excellence in production, innovation, and cost reduction. The challenge is that individual companies do not want to establish an isolated ecosystem given the prohibitive cost and time investments. The industry needs a standard in quality and manufacturing management, one based on a data ecosystem that allows for the secure and continuous sharing of data between many companies in the semiconductor industry. This is why we started Athinia.

What was the most exciting high point of 2023 for your company?
In 2023, Athinia expanded its industry collaboration platform, connecting material suppliers and device makers more deeply. This enlarged network through Athinia’s secure platform has led to greater transparency in the supply chain, heightened efficiency in operations, spurred innovation with shared knowledge, improved risk management, and fostered stronger business relationships. These developments have collectively boosted the industry’s capacity for technological advancement and market adaptability.

In 2023, Athinia achieved a significant milestone by fostering a novel industry collaboration. By integrating Tokyo Electron Limited (TEL) into Athinia’s data analytics platform, Athinia has expanded its network and created a secure platform for device makers and equipment suppliers to collaborate effectively. The collaboration has led to feasibility to further improve equipment performance, efficiency, and maintenance, created mutually benefits for both equipment and device makers. Athinia’s platform facilitates this by offering a secure environment for sharing insights, which adds value to the entire industry and sets a new standard for collaboration.

What was the biggest challenge your company faced in 2023?
The semiconductor industry is data extensive and large-scale organizations need to deal with vast amounts of data. To be able to derive insights from data that unlock efficiencies, shorten time to market, and improve quality, supply chain and sustainability, data needs to be shared across the value chain while ensuring stakeholders maintain control of their intellectual property. To enable successful data collaboration, unstructured content needs to be curated, data quality improved, and diverse sources integrated. However, many companies on the materials side do not employ data scientists.

How is your company’s work addressing this biggest challenge?
Athinia leverages Palantir Foundry for AI/ML and data analytics, focusing on integrating diverse data sources into a unified environment. This process involves effective ETL (Extract, Transform, Load) operations, data quality management, and building a reliable data foundation from various systems like manufacturing, quality control, and supply chain management. Using Foundry’s advanced AI/ML toolkit, Athinia develops and deploys models, with tools for no-code development and custom model creation via shared workspaces. These models drive operational insights, helping inform decisions through visualizations and actionable recommendations.

Palantir Foundry features walk-up usable applications such as Object Explorer, requiring minimal setup for immediate use and low maintenance. Foundry’s Workshop allows the creation of customized applications for specific workflows, with no/low-code builders for intuitive user interaction and minimal backend management. Its widget-driven interfaces cater to various skill levels, ensuring adaptability and scalability. Foundry’s open API architecture facilitates seamless integration with emerging technologies, while its decision orchestration layer bridges analytics with operational workflows, promoting continuous learning and adaptability.

Athinia is designed for scalability, handling increased data and model complexity without losing performance. It includes robust model governance and ethical AI practices, ensuring continuous model evaluation and responsible use with a human-in-the-loop approach. Collaboration is facilitated across teams, with an extensible architecture that integrates with other systems, turning data-driven insights into operational actions. Foundry enables Athinia to transform data into meaningful insights and actionable business outcomes, ensuring improved operational performance and yield.

In addition, Athinia is leveraging the strict data and security standards of the Foundry platform that are trusted by, e.g., the healthcare and defense industry. The Foundry platform’s robust security end-to-end architecture protects intellectual property and ensures customers always stay in control of their data. Customers own their data, Athinia has no access to it. With tailored and granular permissions, customers control who they share data with, how the data can be used, and for how long. Multi-level approval workflows ensure that data sharing follows your company’s data governance framework. Whenever parties are not willing to share raw process data, they have the possibility to obfuscate and normalize the data before it is being shared to protect sensitive data while maintaining its usefulness for advanced analytics such as machine learning.

What do you think the biggest growth area for 2024 will be, and why?
We are on the cusp of a revolution of AI adoption in all aspects of our global society. The drive for higher performance, enabling new AI solutions and faster AI insights for next-generation technologies in both memory and logic devices have never been more important. The material’s intelligence and development of advanced materials becomes really important in order to build a new generation of technologies. Over the next five years, the industry will experience a significant evolution in new nodes and facilities being built.

How is your company’s work addressing this growth?
Athinia is working with its customers to understand which materials will be needed, predict material ramps, accelerate qualification of materials with new production characteristics, and facilitate rapid innovation in the semiconductor industry through secure data sharing and advanced analytics enabling real-time insights.

Our secure data analytics platform processes diverse supplier data using machine learning to predict material performance. The platform offers real-time analytics for process monitoring and decision-making, with scalable data ingestion for adapting to growing data needs. Continuous improvement is achieved through a feedback loop, refining qualification models for efficiency. This results in a secure, adaptable, and sophisticated analytics platform that streamlines the materials qualification process.

The Athinia platform enables quick, informed decision-making, enhances collaborative research and development, and optimizes manufacturing processes. With predictive maintenance and digital twins, companies minimize downtime, and the platform’s robust security measures safeguard intellectual property. Athinia also aids in regulatory compliance and promotes sustainable manufacturing practices, supporting companies in staying competitive in a fast-paced market.

Furthermore, Athinia can enable tracking of the movement of materials and components throughout the supply chain. This transparency helps to ensure that all parts are legitimate and meet quality and emission requirements. By integrating data from all tiers of suppliers and establishing a unified ontology, Athinia helps customers gaining comprehensive visibility into key sustainability metrics like energy use, emissions, and waste generation, while still maintaining each node/tier intellectual property. Athinia’s real-time data processing and visualization capabilities allow continuous monitoring. Its AI/ML tools enable predictive analytics and scenario modeling, assisting in foreseeing and managing potential sustainability issues. The platform also aids in supplier assessments, regulatory compliance, and reporting. Additionally, the collaborative tools and machine learning insights drive continuous improvement and resilience in the supply chain, ensuring Athinia not only meets but also sets new industry benchmarks in sustainability. Athinia is founding member of the SEMI SCC, committed to working with high vertical sustainability via the value chain.

What conferences did you attend in 2023 and how was the traffic?
Athinia actively engaged with key semiconductor industry trends and developments. In 2023, Athinia participated in and presented pioneering data analytics examples at several industry conferences, including SEMICON West and CMC Critical Materials Council.

Will you attend conferences in 2024? Same or more?
I just came back from CES where I spoke on an AI panel in my role as Chief Science & Technology Officer at Merck KGaA, Darmstadt, Germany. Also in January, Athinia was recognized as the technology-enabled data collaboration platform at ISS in Half Moon Bay.

We will continue to intensively engage with key semiconductor industry trends and developments. Athinia is planning to attend the key semiconductor conferences to showcase the more recent industry innovation that resulted from data collaboration. We hope to see everyone at SEMICON West and other events.

Also Read:

Semiconductor Devices: 3 Tricks to Device Innovation

Investing in a sustainable semiconductor future: Materials Matter

Step into the Future with New Area-Selective Processing Solutions for FSAV