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Chip Synthesis at DAC

Chip Synthesis at DAC
by Paul McLellan on 06-27-2012 at 8:30 pm
Categories: EDA

I visited Oasys Design Systems and talked to Craig Robbins, their VP sales. For the first time this year, Oasys has a theater presentations and demos of RealTime Designer which are open to anyone attending the show. In previous years, they have had suite demos for appropriately qualified potential customers but outside they have just had videos. Funny videos, but you don’t really get to look under the hood in them.

The theme of the theater presentation was “right here, right now” to reflect the fact that RealTime Designer is…err…real. As is Oasys themselves, having just had a cash injection from the #1 semiconductor company and the #1 FPGA company. That would be Intel Capital and Xilinx.

Oasys are proud of their customer list too. Qualcomm, Netlogic (now part of Broadcom), Texas Instruments. With Xilinx and Intel Capital they have relationships with the top US semiconductor companies. After all if companies like these are doing their most challenging designs with Oasys then that is a true vote of confidence in the technology. It is really hard to tell if an engine is any good just by taking the cylinder-head off, much easer to see who is confident enough to put the engine in their cars.

RealTime Designer’s big claim to fame is that it is blazingly fast and has huge capacity. Traditional synthesis takes in RTL and converts it to a rough-and-ready netlist and then optimizes that netlist. This requires the whole netlist to be in memory (so needs a lot of it) and means that only small incremental improvements are possible. Thus to get anywhere, it needs to make millions of these little changes which takes a long time. RealTime Designer operates by partitioning the RTL into small regions and each reducing each of those to a fully-placed netlist. If the design doesn’t make its constraints (paths with negative slack, meaning the netlist is too slow) then it returns to the RTL level, repartitions (if appropriate), resynthesizes and re-places just that small regions and perhaps its neighbors. This turns out to converge must faster on a solution with good quality of results (QoR) requiring only thousands of adjustments.

As a result RealTime Designer has a capacity of over 100M gates and runs 5-40 times faster than traditional synthesis tools.

The demo on the show floor didn’t actually run RealTime Designer live (most of the time) since most people don’t even have the patience to watch a 15 minute demo and presentation. But when they did that’s all that the design they used for the demo took to synthesize. How big was it? It was a full-chip 6 million gate quad-core SPARC T1, 421 macros, 261 I/O pads, 1.2GHz clock in 65nm.

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TSMC Threater Presentation: Lorentz Solution!

TSMC Threater Presentation: Lorentz Solution!
by Daniel Nenni on 06-26-2012 at 8:30 pm
Categories: EDA, Foundries, TSMC

Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.

TSMC and Lorentz work together in several ways. TSMC uses Lorentz’s PeakView for designing their RF IP. In addition to working to support mutual customers, there is collaboration on RDK’s and ongoing correlation projects. These projects ensure accurate results on a wide range of structures and devices. Special focus on capacitor structures, and proper handling of metal fills, guard rings, and pattern ground shields yields excellent correlation up through millimeter wavelength frequencies.

Lorentz says that PeakView is suitable for both design use and sign-off, avoiding the “two-tool” solution that many customers live with.

For design PeakView fits in the flow for new device creation with its PCircuit synthesis. Complex devices can be ‘what-if’ed to arrive at optimal tcoil, transformer, balun, tline and cap configurations that best suit the designer’s needs. Multiple devices can be compared side by side in the Device Editor.

Lorentz emphasized that synthesis with PCircuits does not require costly and time consuming EDA vendor set up: no scalable models are needed. As soon as a new layer stack-up is created in PeakView, the full power of PCircuits is available. They say that new and complex devices with high port counts are easily synthesized. There is no dependency on pre-characterization of the process or the cell. Apparently this opens a much larger design space for customers.

PeakView has a new circuit level capacities to electromagnetically model critical interconnections for RC and especially L in the LPE/PEX flow. Complex critical nets are easily and properly analyzed during design iterations, without manual intervention. Simon said the resulting circuit simulation accuracy improves silicon predictability.

PeakView is now also tightly linked to Laker, as well as to Virtuoso. PeakView’s PCircuits, used to create passive device designs, work equally well in both layout editors. PCircuits are process independent and can easily be created to handle new devices. Unlike Pcells, they are compact, object oriented and PDK driven.

Complex hand drawn or PCircuit generated structures can be electromagnetically simulated by PeakView with its fast full wave 3D field solver. Simon added that PeakView allows for accurate and efficient analysis of metal fills, via arrays and other complex structures.

After electromagnetic simulation, compact convergent DC accurate Physics Based Models (PBM) are generated as RLC sub-circuits, in addition to s-parameter output. Process variation and temperature coefficients are supported.

PeakView has built in visualization for viewing voltage, current and meshing. It also features a built in chart window. Its GUI based operation is perfect for increased designer and modeling team productivity.

Bottom line: Lorentz has built a platform for designers and modeling teams that increases creativity and productivity by letting designers create their own geometry and models, and at the same time improving the efficiency of the EM experts with a faster highly accurate solution for sign off model creation. Lorentz’s new capabilities at the circuit level add significant accuracy to high speed analog design.

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Robustness, Reliability and Yield at DAC

Robustness, Reliability and Yield at DAC
by Daniel Payne on 06-26-2012 at 8:15 pm
Categories: EDA, Events

On Wednesday at DAC I met with Bob Slee, distributor and Michael Siu, AE for MunEDA to get an update on what’s new. MunEDA has EDA software for:

  • Schematic porting
  • Nominal circuit analysis
  • Nominal circuit optimization
  • Statistical circuit analysis
  • Statistical circuit optimization
  • IP porting
  • Circuit model generation

Continue reading “Robustness, Reliability and Yield at DAC”

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Microsoft Messes Up Mobile Even More…and Already Went Thermonuclear

Microsoft Messes Up Mobile Even More…and Already Went Thermonuclear
by Paul McLellan on 06-25-2012 at 11:01 pm
Categories: General
8 Comments

Ed wrote recently about Microsoft going thermonuclear. I think that they already did. Ed wrote about Microsoft’s tablet announcement. The second announcement is a sort of follow up to my blog on what will happen to Nokia.

Two big announcements, the first one is that Microsoft is going to produce its own tablet computers (MiPads although they are offically called Surface). A low end ARM-based one and a high end Intel-based one. Daniel Payne was ahead of me at DAC bringing just his iPad and a keyboard (the MiPads have keyboards too) and leaving his laptop at home. I guess he’s not that far away from not bothering to buy a new laptop. So Microsoft is going full-bore to compete with its licensees, at least in laptops/ultrabooks.

The second big announcement…actually not big, they tried to downplay it…is that any WP7 cell-phone will not be upgradeable to WP8. This means that carriers will simply not sell WP7 based cell-phones. Not that they were really doing anyway. Nokia (the only significant Microsoft licensee) is down to 2% market share, and the other licensees (Samsung, Huawai, LG) all have Android phones and, in the case of Samsung, two more of its own operating systems. Is this significant? Well, here’s one datapoint: T-Mobile in Germany immediately announced it is not going to sell the Lumia 900…despite the fact that they have already been advertising it. Remember, in cell-phones, it doesn’t matter if your operating system is any good, just whether the carriers will sell it. And T-Mobile may be an also-ran in the US but they are Germany’s biggest carrier.

The official Nokia response from Elop himself:We have a lot of exciting capabilities coming as part of a pattern of updates for the existing Lumia products. This includes some of the most significant visual elements of WP8 – for example, the new start screen. As we have always been, Nokia is committed to delivering a long term experience to any purchasers of our products.
Count me underwhelmed.

My read: Microsoft has realized they are dead in cell-phones. The Nokia strategy has failed and all the other carriers are fed up of being screwed by non-upgradeable Micosoft operating systems: Windows Mobile to Windows Phone, not upgradeable. Windows Phone to WP7, not upgradeable. WP7 to WP8, not upgradeable. Fool me once, OK. Fool me three times, no way.

If Microsoft is not going to gradually decline into obsolescence (iPhone alone is already bigger than all of Microsoft) then they have to succeed in tablets. I guess they don’t feel that they can compete if they have to rely on their licensees (after all, how did that work for PCs…oh yes, incredibly well, they stole all the profit that Intel didn’t get) so they are going to do it themselves.

Microsoft has a mixed record in hardware. Some very successful products (early mice and keyboards, Xbox) and some total duds (Zune, Kin—the shortest lived cell-phone ever). But none of these (maybe Xbox a little bit) didn’t compete with their PC partners. Now they have launched what could turn out to be an all-out war. It may look minor, just like Anschluss in 1938, when Germany invaded Austria, but it will have huge repercussions. And if Microsoft gets into tablets, what about its own phones too, a smart-phone is just a small tablet with a chip added from Qualcomm, after all. Except for that carrier relationship thing…remember, the carriers hate Skype=Microsoft and with the lack of upgradability they hate them again. But won’t the MiPads also need carrier access. Well, yes, but for now they are WiFi only without also having the blazingly fast LTE access of iPad3 (sorry, the “New iPad”).

So what will happen? Prediction #1 the board will fire Elop as CEO of Nokia and the new guy will abandon Microsoft (after all Microsoft has already abandoned them). As Tomi points out, Nokia has three other operating systems:

  • Symbian, which used to be the market leader and is still be aggressively sold by China Mobile, the worlds largest operator (bigger than all operators in the US put together…well, that’s because it has more subscribers than the US population)
  • Meego, Linux-based somewhat Android-like. Some phones running it are rated higher than iPhone
  • Meltemi, for low end smartphones (not all smartphones can run everything, the lowest end Nokia Lumia for example can run neither Skype nor Angry Birds). Oh, and Elop just announced he is going to shut down this program and lay everyone off so if Elop doesn’t go soon it will be too late

Prediction #2: WP8 will have trouble finding tablet licensees. Dell, Lenovo etc already all have Android offerings. Where people have a choice, they don’t see Microsoft as a good one. And why wouldn’t the manufacturers want Microsoft. Oh yes, they took all the profit last time and that’s not going to happen again.

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AMS Simulation Update from Mentor Graphics at DAC

AMS Simulation Update from Mentor Graphics at DAC
by Daniel Payne on 06-25-2012 at 12:36 pm
Categories: EDA, Siemens EDA
6 Comments

I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.
Continue reading “AMS Simulation Update from Mentor Graphics at DAC”

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FinFET Standard Cells at DAC

FinFET Standard Cells at DAC
by Daniel Payne on 06-25-2012 at 11:45 am
Categories: EDA, Events, IP

Rajiv Bhateja, Dhrumil Gandhi and Neal Carney met with me at DAC on Wednesday to give an update on what’s new in 2012 for Tela Innovations, a provider of lithography optimized IP and tools. This team has a rich history in EDA and IP from companies like: ARM, Artisan, Mentor Graphics and Silicon Compilers. Continue reading “FinFET Standard Cells at DAC”

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TSMC Theater Presentation: Apache

TSMC Theater Presentation: Apache
by Paul McLellan on 06-25-2012 at 12:13 am
Categories: Ansys, Inc., EDA

At the TSMC Theater Apache (don’t forget, now a subsidary of Ansys) talked about Emerging Challenges for Power, Signal and Reliability Verification on 3D-IC and Silicon Interposer Designs. The more I see about the costs and challenges of 20/22nm and below, the more I think that these 3D and 2.5D approaches are going to be one of the main ways that we keep on the Moore’s law curve at the system level.

There are lots of challenges for 3D designs:

  • multi-die floorplan and place & route
  • manufacturing test
  • TSV-aware physical verification
  • TSV extraction
  • Power integrity
  • Reliability integrity
  • Signal integrtity
  • Wide I/O jitter analysis

Of course Apache is not directly involved in all of these, just the last 4. Apache have proactively been working with TSMC on these issues both for regular 20nm designs and for 3D designs.

One of the most recent changes is the addition of more complete thermal analysis. This is then fed back into the power analysis (because high temperature affects performance which affects power which affects temperature…, not to mention it accelerates metal migration and other reliability issues). RedHawk is used to generate the Chip Thermal Model (CTM) which is fed into Sentinel-TI also with input from IcePick system thermal tools (to analyze heat flow out of the package etc). This combination makes very accurate thermal analysis, and thus the way that this effects performance ane reliability.

Apache/ANSYS have been working closely with TSMC for 3D designs that combine power analysis from Apache with TSMC’s DFM Data-Kit (DDK) modeling to arrive at a complete analysis of a stack of die on an interposer in a package with heatsinks, in-package slugs etc.

One specific problem in the short term is analyzing Wide I/O since JEDEC has standardized wide I/O for memories meaning that there are lots of signal integrity issues, especially using Wide I/O on silicon interposer (where there is lots of routing involved too). The same problems arise with any wide bus, and wide-buses are common on 3D and interposer designs since the ability to have almost as many “pins” as you want is one of the advantages of 3D/2.5D.