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The First 14nm FinFET Wafer Sighting!

The First 14nm FinFET Wafer Sighting!
by Daniel Nenni on 01-11-2013 at 12:10 pm
Categories: Foundries, GlobalFoundries

Incredibly exciting! Even my beautiful wife was impressed by the rainbow of colors it reflected. From left to right: 28nm, 20nm, and 14nm wafers. The 20nm and 14nm wafers are from the GLOBALFOUNDRIES NY fab, made in the USA! GF also announced another $3-4B CAPEX for 2013 to increase capacity of all three of their 300mm fabs (Singapore, Dresden, and NY). Strangely enough I have been to the Singapore and Dresden fabs but not NY, and my family is from upstate NY. As soon as it warms up I will visit for sure. I love hanging with the fab guys.

This was the third annual GLOBALFOUNDRIES CES party and it was definitely the best. We got there early so I got a good look at the badges laid out for everyone. I won’t out anybody but let’s just say it was the Who’s Who of the semiconductor industry and was a big tell of who their customers and close partners are. Great food too! The Mirage Hotel really knows how to do a Las Vegas style backyard BBQ.

Good thing I did not make a bet on who would have FinFETs in production first because I would have lost! Just a minor detour but I will be keynoting FinFET Day at the Electronic Design Processing (EDPS) Symposium in Monterey this April. Friday morning there will be presentations on the challenges of FinFET design by designers from the likes of Qualcomm, ARM, NVIDIA, and Oracle. In the afternoon there will be a panel on the challenges of FinFET manufacturing with TSMC, GLOBALFOUNDRIES, and hopefully Samsung and Intel. Put it on your calendar and stay tuned to SemiWiki for updates as we get closer to the event.

GLOBALFOUNDRIES at CES is a great thing. Being at the bottom as we are, it is very important to see the entire supply chain including the final products and customers. It is a great perspective which is why I come every year. That and the hotels, food, drinks, shows, gambling, I love Las Vegas.

One funny thing about the GF party, the parting gift was a very nice world travel adapter and USB charger. The sticker on the bottom however said made in China…… whoops. Any guess on how many publications “borrow” the 14nm wafer picture taken by my nifty iPhone 5?

Don’t forget to register for the Common Platform Technology Forum. It will be FinFETtastic! Just click on the banner below. Spoiler alert: Free breakfast AND lunch!

And special thanks to the Hilton for putting us in a Penthouse Suite. Living large in Las Vegas. This room is bigger than our first apartment. You should have seen the look on my wife’s face when they said 39th floor. She is afraid of heights!

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Predictions are hard, especially about the future

Predictions are hard, especially about the future
by Paul McLellan on 01-11-2013 at 11:26 am
Categories: EDA

I was asked to make some predictions about the EDA, semiconductor and electronic systems markets for 2013. I decided that it would be more fun to make some plausible predictions, some of which will be right, rather than go for anodyne predictions (“Cadence will acquire a couple of startups”) which are uninformative, not to mention boring. So, drum roll, here are my 2013 predictions:

  • There will be a lot of discussion about the costs of 20nm since it is so much more than 28nm. It will be a very slow transition with some people going straight to 14/16nm (which is really 20nm with smaller transistors which is really 26nm with smaller transistors). Expect lots of discussion about the end of Moore’s law.
  • EUV lithography will not become commercial during 2013 and so will miss the 10nm node.
  • TSV-based 3D ICs will start to become mainstream. Memory on logic, and mixed digital/analog on interposer. Expect lots of discussion about “more than Moore” and how 3D is the new way for scaling.
  • The death of a giant will finally take place. Nokia, still #1 only a year ago, will be dismembered. A consortium of Apple, Google and Samsung will buy the patents for billions to stop any trolls getting any of them. Huawei will buy the handset and base-station businesses for peanuts.
  • Synopsys will acquire Mentor. EDA will otherwise be fairly boring with the big three being the only companies able to attack the upcoming problems that require dozens of tools to be updated, not just a new point tool inserted in the flow.
  • If the IPO markets are open, Jasper, eSilicon, Atrenta and Tensilica will go public. If someone doesn’t buy them first.

OK. Everyone can play this game. What are your predictions?

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A Brief History of Synopsys DesignWare ® IP

A Brief History of Synopsys DesignWare ® IP
by Daniel Nenni on 01-11-2013 at 9:00 am
Categories: IP, Synopsys

Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market requirements and reduce integration risk by providing the high-quality IP they need, precisely when they need it.

Today, Synopsys is considered by designers as the industry’s trusted IP partner. Its DesignWare IP is shipping in billions of chips … and counting. According to the latest research from Gartner, Synopsys is the leading provider of interface, analog and memory IP and the No. 2 provider of IP in the industry. In 2012 Synopsys achieved its 100th design win with its 28-nanometer (nm) IP and was awarded TSMC’s 2012 Interface IP Partner of the Year for the third consecutive year. These milestones, along with more than 1400 engineers and a worldwide technical support team demonstrate Synopsys’ commitment to helping customers achieve their design goals at every step. The world of IP is definitely changing. With the shift to IP subsystems, 20-nm IP and FinFET, Synopsys remains in the forefront of providing the IP needed for these technology advancements. Figure 1: Synopsys’ Growing IP Business:

So How Did Synopsys Get Here?
In the 1990s Synopsys launched the DesignWare Foundation Library, a collection of technology-independent, reusable building block IP such as adders and multipliers that are tightly integrated with Synopsys’ synthesis environment, delivering significant improvements in area, timing and runtime. Through the years, complex IP blocks were added to the library such as 8-bit microcontrollers, AMBA on-chip bus IP as well as verification IP (a.k.a. SmartModels). With these additions, the product became known as the DesignWare Library – and it has been the most widely used library of foundation IP ever since.

Fast forward a decade. We saw an explosion in the usage of standards-based communication protocols, setting the stage for the emergence of the commercial IP industry as companies realized they needed to focus their efforts on the differentiated portions of their design and not on developing standards-based IP. In 2002, Synopsys acquired inSilicon, adding popular interface protocols such as PCI-X, USB, IEEE 1394 and JPEG to its DesignWare IP portfolio. By 2004, Synopsys was seeing increased demand in PCI Express (PCIe) for data center and server applications. By acquiring Cascade Semiconductor, Synopsys rounded out its already successful DesignWare PCI Express Endpoint solution with root port, dual mode and switch ports, providing designers with a complete high-performance, low-latency PCI Express IP solution. Also in 2004, the acquisition of Accelerant Networks brought serializer-deserializer (SerDes) technology to Synopsys. Figure 2: DesignWare PCI Express IP Solution:

In 2007, Synopsys released the DesignWare USB 2.0 nanoPHY, its next-generation USB 2.0 PHY, which cut the power and size in half over the previous generation. The expansion of Synopsys’ IP portfolio continued that year with the launch of digital controllers for PCI Express 2.0 (5.0 GT/s), mobile storage, SATA AHCI and the acquisition of Mosaid’s DDR memory controllers and PHY IP. One year later, Synopsys continued its momentum in DDR by releasing a full range of silicon-proven DDR3 and DDR2 IP solutions and announced a complete SuperSpeed USB 3.0 IP solution.

In 2009, Synopsys moved into the analog IP business with the acquisition of the Analog Business Group of MIPS Technologies. The acquisition added to the DesignWare IP portfolio a new family of analog IP such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and audio codecs. It also added HDMI 1.3 transmitter (Tx) and receiver (Rx) IP to Synopsys’ existing interface portfolio. With this acquisition, designers were able to go to a single, trusted vendor for both their analog and interface IP needs. In the same year, Synopsys introduced new products such as minPower Components; Ethernet IP with support for the IEEE 1588 specification; DDR3 IP operating at 2133 Mbps data rate and 1.35V DDR3L, SATA 6 Gbps digital controllers; and a complete solution for PCI Express 3.0 (8.0 GT/s).

The acquisition of Virage Logic in 2009 added logic libraries and embedded memories, enabling designers to achieve the best combination of power, performance and yield; memory test and repair; non-volatile memory; and ARC processors targeted at embedded and deeply embedded applications. Throughout 2010, Synopsys continued to introduce new products that would help designers integrate advanced functionality into their SoCs such as:

  • Third -generation USB 2.0 PHY – the USB 2.0 picoPHY (30% smaller area and lower power compared to the previous generation)
  • 40-nm data converters
  • Universal DDR controllers supporting DDR2, DDR3, Mobile DDR and LPDDR2 standards
  • DDR multiPHY supporting six DDR standards
  • MIPI 3G DigRF, DigRF v4, CSI-2 controller, DSI host controller and D-PHY
  • HDMI 1.4 Tx/Rx controller and PHY
  • Ethernet controller with an audio-video bridging feature
  • DesignWare STAR ECC (error-correcting codes)
  • ARC processor cores for Blu-ray Disc players

In 2011, the focus was on helping designers develop 28-nm SoCs. Synopsys announced the availability of DesignWare Interface PHY and Embedded Memory IP for TSMC’s advanced 28-nm process as well as the collaboration with UMC on embedded memory and logic library in 28-nm. Significant milestones were also achieved, including Synopsys’ DesignWare STAR Memory System being shipped in one billion chips, DesignWare SuperSpeed USB 3.0 IP achieving more than 40 design wins, and GUC taping out 30 customer chips using DesignWare IP. The DesignWare ARC EM processor family for embedded applications was also launched this year.

In 2012, designers started to integrate more and larger third-party IP into SoCs, it wasn’t enough to just provide individual IP blocks – the market needed complete IP subsystems to ease the integration effort. In March 2012, Synopsys unveiled the industry’s first complete, pre-integrated and configurable audio subsystem consisting of hardware, software and prototyping. Figure 3: DesignWare SoundWave Audio Subsystem:

In the same year, Synopsys also had significant IP product releases such as the industry’s first 28-nm Multi-Gear MIPI M-PHY IP supporting six standards, DDR4 memory controller and PHY, MIPI UniPro and UFS, STAR Memory System for 20-nm designs and IP for the SMIC 40-nm low leakage process.

With more functionality going into a single device, third-party IP continues help designers reduce risk and speed time-to-market. Based on Synopsys user surveys, the top five criteria for selecting an IP provider are:

[LIST=1]

  • IP technology leadership
  • Quality/silicon-proven IP
  • Market leadership
  • Brand reputation, and
  • Breadth of IP portfolioThese have been Synopsys’ IP priorities as well.To learn about all the DesignWare IP developments, visit the website.
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TSMC Apple Rumors Debunked!

TSMC Apple Rumors Debunked!
by Daniel Nenni on 01-11-2013 at 8:00 am
Categories: Foundries, TSMC

Disclaimer: I’m a blogger and by definition I share my observations, opinions, and experiences. Journalists and Analysts on the other hand are held to a much higher legal standard which is why they cite undisclosed sources and use double speak to shield themselves legally. Why trust a SemiWiki blogger over a Journalist or an Analyst? Because we actually work inside the fabless semiconductor ecosystem and they do not, simple as that. My previous TSMC blogs are HERE if you want to check my credentials. Be sure and read the ones early last year on the rumors of problems with TSMC 28nm. I said FALSE and I was right, the Journalists and Analysts were wrong, and their pants are on fire once again.

The first rumor is that the next Apple A7 processor (28nm) will be made by TSMC. That rumor is FALSE! As I previously blogged, the Apple iPhone to be released this year (iPhone 5s) will be Samsung 28nm. The iPhone to be released next year (iPhone 6) will be TSMC 20nm. A company the size of Apple cannot switch foundries on a moment’s notice. The volumes are too high and the technology issues are too complex.I have no doubt Apple discussed 28nm with TSMC but since no other foundries had 28nm available there was no way TSMC could handle the wafer demands of Apple and the rest of the fabless companies. Apple also gets preferred pricing so why would TSMC give up higher margin 28nm business AND alienate their customer base? Not going to happen.

TSMC: Our mission is to be the trustedtechnology and capacity provider of the global logic IC industry for years to come.

20nm will be another story. Samsung and GLOBALFOUDNRIES will have 20nm in production and TSMC will see their 28nm customers use other sources. Qualcomm, TI, Broadcom, Marvell, and Xilinx all second and third source wafer manufacturing when possible. 20nm volumes will also not match 28nm due to a higher cost per transistor. To me 20nm is a half node in the economic sense in preparation for 16/14nm FinFETs, which will hit much higher volumes from the mobile guys due to lower power consumption (longer battery life).

The second rumor is that TSMC will build a fab in New York to help facilitate Apple business. I say FALSE. If TSMC builds a GigaFab anywhere in the United States I will eat my SemiWiki hat, simple as that.If TSMC needs to expand capacity above and beyond what they have planned today they can simply take over empty DRAM fab space in Taiwan which there is plenty of. Or if you want a more realistic rumor to spread here it is: TSMC will acquire the #3 semiconductor foundry UMC to increase capacity. This is much better than the rumor last year that GLOBALFOUNDRIES would acquire UMC. But I don’t do rumors so you didn’t hear it from me.

The Taiwan government founded the pure-play semiconductor foundry business working hand-in-hand with both TSMC and UMC. TSMC and UMC are brothers. The Taiwan economy is semiconductor centric. TSMC is one of Taiwan’s top employers. I have no doubt that TSMC is seriously looking at all options but why would they follow the GLOBALFOUNDRIES model of having “global foundries” in favor of the TSMC model of Taiwan based cost efficiencies? The U.S. environmental impact bureaucracy alone would kill that deal! :p The wafer business has always been about price and that will never change.The other prediction I made last year is that TSMC stock (TSM) is a $20 dollar stock. It will happen this year, believe it.That’s my story and I’m sticking to it.

Related: Apple will NOT manufacture SoCs at Intel!

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Reducing Dynamic and Static Power in Memories

Reducing Dynamic and Static Power in Memories
by Paul McLellan on 01-10-2013 at 3:46 pm
Categories: EDA

Sequential approaches to power reduction work well on logic implemented using standard cells. But part of every SoC, sometimes a very large part, is taken up with embedded memories for which alternative approaches are required. Not only do these memories occupy up to half of the area they also account for as much as 75% of the power dissipation, a mixture of static (leakage) and dynamic power.

The basic idea of how to reduce dynamic power in memories is simple: if you are going to read the same address as last time then don’t bother to do the read, just use the old latched value. Similarly, if you are going to write the same value as last time to the same location, then don’t bother with the write since it has no effect. Of course, both these will save the most power when the address remains stable for large numbers of clock cycles.

Designers know this, of course, and over time they try and analyze the registers for redundant accesses and look for opportunities to shut them off. Doing this automatically during synthesis is beyond the scope of RTL synthesis tools. But doing it manually can be error-prone. Missed opportunities to shut-off redundant access results in less than the maximum power saving. Worse, shutting off an access that turns out not to be redundant will result in an error (reading the wrong value, for example) and probably a very obscure system failure.

Sequential analysis involves analyzing the entire design, including memories. It looks over a window of several clock cycles to find which values are propagated, which changes are not observable, which registers are known to remain unchanged. This is the basis for power optimization which results in shutting off unused or unobservable computations, preventing “new” values from propagating when they are known to be the same as the old value and so forth.

The same approach can be used with embedded memories. Even though at first glance every read and write to memory may seem to be essential, depending on the control sequence of the design they may not be required. Removing such redundant accesses typically results in significant reduction in the dynamic power consumption of memories.


For a specific example, with the Synopsys/Virage 40nm memory above, the memory enable can potentially be held low for long periods, saving dynamic power.

Embedded memory vendors provide capabilities to reduce not just dynamic power but also static leakage power in memories that are not in use. These involve sleep and wake signals but, in turn, that means logic to create those signals. Of course this is a tradeoff: the power saving from the sleep mode has to be greater than the power taken up generating those signals, but as long as memories are sometimes put to sleep for many clock cycles, this balance is likely to be positive.


Again, using the same Synopsys/Virage memory, further savings are possible by generating appropriate sleep signals, taking into account the requirement that the memory takes an extra clock cycle to wake.

These two optimizations work together powerfully. The more redundant accesses are suppressed, the more the memory is idle and so can be put into a sleep mode saving even more dynamic and leakage power.

Calypto’s PowerPro is a sequential power optimization tool capable of doing deep sequential analysis of the whole design, including memories, and either guides designers to make manual changes safely, or automatically updates the RTL to produced a power-optimized version.

There will be a webinar on reducing dynamic and leakage power in memories on Tuesday February 12th at 10am Pacific time. Webinar details, including registration, are here. There is a white-paper on the same topic on the Calypto download page here(look for Memory Power Reduction in SoC Designs Using PowerPro MG).

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Global Design Closure

Global Design Closure
by Paul McLellan on 01-09-2013 at 8:34 pm
Categories: EDA

Satish Soman, chief solutions architect at Atrenta, was invited to give a presentation on Global Design Closure at the VLSI India conference in Pune at the start of this month. He talked about the need to close the gap between the typical SoC development methodology and what happens in reality.


SoCs are really put together in two phases. Block level or IP design is done and the RTL designers do what they can to verify not just functionality but whether the block will meet its performance specifications when put into the SoC. These blocks are handed off at the RTL level to the SoC design team who create the final netlist, do place and route, timing analysis, test insertion and so on.

The reality of what is actually handed off is that it is verified RTL, with verified constraints and verified testability (which are all straightforward to do at the RTL level). What is not handed off is any block-level physical awareness, any context of how the block will be used in the SoC, and there is no feed-forward of physical information about the block or IP.

This shows up as long and unpredictable SoC design closure cycles, with difficult iteration back to the RTL design teams (which are often geographically remote from the SoC design team). Current attempts to alleviate the pain are to do early drops to the physical design team, provide the RTL team with physical tools and so on. Basically get early feedback of the missing information.

SpyGlass Physical is Atrenta’s tool for addressing this. It is a tool for the RTL designer that gives them a dashboard for analyzing and addressing congestion and other physical issues at the block/IP design start, prior to RTL handoff to the SoC assembly team. It is also used a the SoC level to get similar information (plus, of course, additional features for padring, I/O etc) without having to go through a complete iteration of synthesis and physical design which typically takes several days.


Using SpyGlass Physical during RTL design will slightly increase the time taken before RTL is ready for handoff. But the RTL will be of superior quality and so the synthesis and place & route will be much reduced, as will iterations back to fix RTL issues that manifest themselves as physical design issues such as routing congestion.

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Oasys RealTime Explorer

Oasys RealTime Explorer
by Paul McLellan on 01-09-2013 at 8:00 am
Categories: Uncategorized
1 Comment

The current methodology in design in most companies, and certainly many of the biggest, is that front end RTL design is done by one team with a limited set of front-end design tools. This is then eventually passed off to the physical design team who run all the scripts, do the “real” synthesis, place & route and timing verification. Essentially we have two separate groups with RTL handoff between them. This methodology worked fine for 1M gate designs a couple of process nodes ago. It doesn’t work for 10M and 100M gate designs.

In practice what happens is that everything looks fine to the front-end designers who are looking at individual blocks without the true physical information. They may be using approximate synthesis and are certainly using approximate physical information. When the back end team put the whole design together there are dozens if not hundreds of violations that need to be resolved by passing the design back to the front end designers to change the RTL. Simply redoing the design using different constraints or different scripts is not good enough.

Add to this the increasing tendency to use an offshore group of comparatively inexperienced designers to do all the front end design and this is a recipe for trouble. It takes about 3 days or so to run a design all the way through the back end, although sometimes the engineers just are not available (especially during a critical tapeout) and it can take weeks to get anything beyond the most basic feedback.


RTL engineers, not just the back end team who run the real synthesis of the entire design, need to be able to visualize and interact with the physical RTL results of their synthesis. But, critically, not at the block level but the entire design. Since RTL level blocks will be grouped into the physical hierarchy, block level information is fundamentally incorrect. This enables them to produce higher quality RTL that is free of top-level timing violations, routing congestion, designs that are too big for the floorplan or the power budget.

Of course the two things to make this possible are capacity (so that the entire design can be synthesized and analyzed as a whole) and speed (since RTL designers aren’t going to sit around for days waiting to find out what they need). Oasys’s RealTime technology, already used in RealTime Designer, is now available in RealTime Explorer, which is targeted specifically at making the front-end designer more effective and eliminating iterations between the frontend and backend design teams.


A simple-to-explain example is when a very wide multiplexor causes routing congestion. This cannot be fixed effectively in the back end. Someone who understands what the multiplexor is really doing needs to alter the RTL to something better. Just tightening the timing constraints isn’t going to do it.

Bottom line: RTL engineers can eliminate their dependence on physical design teams for top level timing & routability analysis.

More information on Oasys’s (new) website here.

UPDATE: there is a webinar on RealTime Explorer every couple of days from January 15th to 31st. Details on the webinar page here.


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Interface Protocols, USB3, PCI Express, MIPI, SATA… the winners and losers in 2012

Interface Protocols, USB3, PCI Express, MIPI, SATA… the winners and losers in 2012
by Eric Esteve on 01-08-2013 at 5:25 am
Categories: Uncategorized
4 Comments

Who makes the decision and declare that a specific interface protocol is successful? Not me, as I can only consolidate market share data and some insight information coming from the industry. The end user, when going to a shop (real or virtual) and spend a significant part of his budget to buy an electronic product, selecting among hundreds, will eventually decide for the success of a certain feature (SuperSpeed USB, HDMI or ThunderBolt). But, if you wait for the success of this feature on the mainstream market to integrate it into your system (OEM), your SoC (chip maker) or your IP portfolio (EDA/IP vendor), then you are respectively 12/18 months, 2 years or more late…
Continue reading “Interface Protocols, USB3, PCI Express, MIPI, SATA… the winners and losers in 2012”

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OTP @ 2013 Common Platform Technology Forum

OTP @ 2013 Common Platform Technology Forum
by Daniel Nenni on 01-06-2013 at 9:00 pm
Categories: IP, Sidense

Sidense will be exhibiting at the Common Platform Technology Forum in Santa Clara, California on February 5, during which time they will be discussing their one-transistor, one-time programmable (1T-OTP) memory IP products. Based on their patented 1T-Fuse™ bit cell, Sidense antifuse-based 1T-OTP macros offer a secure, reliable, low-cost and field-programmable alternative solution to mask ROM, eFuse, EEPROM and flash memory technologies in many applications.

Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (LNVM) IP solution. With over 100 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense 1T-OTP macros are implemented in standard logic CMOS processes and need no additional masks or process steps. The macros are available at many process nodes and variants, including BCD and high-voltage nodes, from 180nm down to 28nm from leading top-tier foundries and selected IDMs. Sidense macros are available in densities up to 512 Kbits per macro, which can be combined to implement several megabits of storage on a chip. Sidense offers some products with read and programming capability up to 150ºC, ideal for automotive “under the hood” applications. Programming may be done at test, at wafer probe, or in the field from an external source or with an on-chip charge pump.

1T-OTP macros are inherently low power, making them ideal storage choices for mobile communications and other handheld devices. Designers are using Sidense 1T-OTP for code and key storage, look-up table data, processor and logic configuration, ID tags, and analog trimming and calibration. Typical applications include sensor conditioning, power management, display drivers, image processors, network controllers, wireless LAN and Bluetooth controllers for the automotive, mobile, commercial and industrial market segments.

Sidense 1T-OTP is now licensed to more than 100 customers including several of the top semiconductor manufacturers and is now designed into devices in mass production in all major semiconductor markets including: media processors, display drivers, automotive sensors, image sensors, wireless peripherals and microcontrollers. 1T-OTP is available with more than 10 foundry partners and IDMs including all top-tier foundries. Sidense also broadened the process node availability from 180nm to 28nm for the Company’s products. To further align the portfolio with customers’ requirements, 1T-OTP has been ported to power/BCD processes qualified for automotive applications and high-voltage processes for display drivers.

For more information, please go to www.sidense.com and visit Sidense at the Common Platform Technology Forum in Santa Clara, California on February 5, 2013:

General Agenda:

  • 8:30am – 9:00am Registration and Continental Breakfast
  • 9:00am – 11:30am Keynote Session
  • 11:30am – 1:00pm Lunch / Exhibit Area Open
  • 1:00pm – 4:40pm Technical Session
  • 4:40pm – 6:00pm Reception

Partner Exhibit Hours:

  • 11:30am – 6:00pm

Who said there is no such thing as a free lunch! I hope to see you there!