SILVACO 073125 Webinar 800x100
Semiconductor Expert Forum

Posted on

Genevi, isn’t that a city in Switzerland?

Genevi, isn’t that a city in Switzerland?
by Paul McLellan on 06-14-2012 at 8:05 pm
Categories: EDA, Siemens EDA

I got an email from Mentor Embedded this morning about a webinar on Implementing a GENIVI-compliant System. I have to admit I had no idea what GENIVI is, which surprised me. I spent several years working in the embedded space and so I usually have at least a 50,000 foot view of most things going on there. One reason for my ignorance is that it only started in November 2011 unlike automotive standards such as FlexRay and CAN that have been around for a long time.

GENIVI turns out to be an automotive infotainment standard (the IVI on GENIVI stands for In-Vehicle Infotainment). This means it gets used in things like GPS maps, CD players, satellite access, but is not used for things like powertrain management or ABS braking (which are safety critical and so have a completely different set of tradeoffs). The GENIVI website describes itself as:”a non-profit industry alliance committed to driving the broad adoption of an In-Vehicle Infotainment (IVI) open-source development platform.”

GENIVI seems to be based in that hotbed of automotive…San Ramon, one valley over from Silicon Valley. Unlike, say, Android, Genivi is not an open-source development at the code level, it is a set of standard services, some of which are not optional, along with compliance programs.

The most recent specification of the specification is 2.0. On the prior iteration (that would be 1.0) 19 platforms from 9 member companies were declared compliant. Already under the 2.0 there are compliant platforms from:

  • Accenture
  • Intel/Samsung
  • Mentor Graphics (not exactly a surprise)
  • MontaVista
  • Renesas
  • Wind River

The obvious missing name is Google and Android.

The seminar will cover:

  • Implementing IVI, current trends and infrastructure
  • Gaining GENIVI compliance
  • Integrating open source and proprietary components
  • Building in adjacent functions, such as AutoSar and Android-based applications

The webinar is at 11am central time (9am on West Coast) on June 21st. Register for it here.

Posted on

Semiconductor equipment returns to growth

Semiconductor equipment returns to growth
by Bill Jewell on 06-14-2012 at 7:37 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Semiconductor manufacturing equipment has returned to growth after a falloff in the second half of 2011. Combined data from SEMI (U.S. andEuropean companies) and SEAJ (Japanese companies) show billings peaked at a three-month-average of $3.2 billion in May 2011. Bookings and billings began todrop in June 2011, with billings reaching a low of $2.3 billion in November 2011. Bookings and billings began to turn around in December. Billings recovered to $2.9 billion in April 2012.


Total semiconductor manufacturing equipment billings were $33.4 billion in 2011. SEMI’s May 2012 forecast for wafer fab equipment called for 2% growth in 2012. 2% growth would result in $34.1 billion in billings for 2012, still 2% below 2007 billings of $34.7 billion and well below the record high of over $45 billion in 2000. Thus semiconductor capacity appears to be headed for moderate growth, but nowhere near the overheated growth which could lead to overcapacity.

What is the current capacity utilization in the semiconductor industry? The demise of the Semiconductor Industry Capacity Statistics (SICAS) program makes the answer difficult to determine. The final SICAS data for 4Q 2011 showed MOS IC capacity utilization of 88.9%, down from 91.7% in 3Q 2011. WSTS data showed a 2.3% decline in the semiconductor market in 1Q 2012 from 4Q 2012. Thus MOS IC shipments likely declined by a similar amount. MOS IC capacity growth was probably roughly flat in 1Q 2012 based on the falloff in manufacturing equipment billings in the second half of 2011. We at Semiconductor Intelligence estimate industry MOS IC capacity utilization was86% to 87% in 1Q 2012.

Forecasts for 2012 semiconductor market growth are generally fairly low. Mike Cowan’s June forecast was 0.3% growth, similar to WSTS’ May forecast of 0.4% growth. Our forecast at Semiconductor Intelligence is for 2% growth. Forecasts made in March and April from major semiconductor analyst firms range from 4% to 6%. Slow growth in the semiconductor market combined with slow growth in the semiconductor manufacturing equipment market should result in no significant movement in capacity utilization. MOS IC utilization should remain in the mid 80% range through 2012.

The two largest semiconductor foundries, TSMC and UMC, provide information on their wafer capacity and shipments. Data over the last year reflects the industry trends above. Both companies saw declines in revenue and shipments in 3Q 2011 and 4Q 2011. Shipments began to pick up in 1Q 2012. Both companies expect strong growth in business in 2Q 2012. TSMC expects 2Q 2012 revenue to increase 20% from 1Q 2012. UMC expects wafer shipment to increase 15%. Capacity growth has slowed significantly from prior quarters. TSMC expects capacity will decline 1.3% in 2Q 2012. UMC forecasts a 0.6% increase in capacity in 2Q 2012 following a 0.9% decline in 1Q 2012.

Posted on

The Black Swan that Catapulted Intel into 2012

The Black Swan that Catapulted Intel into 2012
by Ed McKernan on 06-14-2012 at 7:30 pm
Categories: Arm, Foundries, Intel Foundry
3 Comments

Black Swan Events are not to be embraced, they are to be feared, if conventional wisdom holds true. And yet, the 2011 Black Swan that slammed the PC market (i.e. the Thailand Floods that wiped out a large part of the disk drive market) has turned out to be the key catalyst for reshaping the semiconductor industry in 2012 and 2013. Instead of hobbling through what was seen to be at least a 6 month crises with underutilized 32nm fabs, Intel made a decision last November to ramp 22nm production faster and thus catapult them to a position that will result in Apple entering its fabs and Samsung dropping ARM development, embracing x86 across the board within two years. This may seem an extreme view, but the announcement that TSMC will see 28nm shortages into 2013 highlights that Mobile Tsunami, like PCs require leading edge process technology and there is only one true leading edge volume semiconductor supplier: Intel.

Intel reported its best quarter ever (Q3 2011) on October 18 2011 and projected a further 3% revenue upside for Q4 2011. This announcement came just three days after WD’s Hard Disk Drive factory was flooded and thus the extent of any impact was probably not understood. However, because Intel is a heavy CapEx, fast depreciating driven company, it is key for them to assess quickly how external events affect market demand and drives fab loading. In the past they have been known to quickly shift gears to get to where the market is going at the cost of short-term revenue. And so as they admitted in their January 2012 conference call they converted some of their production from 32nm to 22nm. We will never know how much was converted, but I speculate it was significant. Wall St. was initially not pleased and AMD benefited from Intel’s pull back. But now the benefits are starting to accrue as Qualcomm, AMD and nVidia scramble for 28nm production that targets the Mobile Tsunami marketplace. Only Apple and Intel are prepared.

Apple’s announcement on its refresh of the MacBook Air and MacBook Pro line this week shows that Intel has gained additional sockets with its Ivy Bridge with integrated graphics at the expense of AMD and nVidia. Whereas two years ago, an external graphics chip was used across the Apple product line, now it is relegated to the $1799 and higher MacBook Pro notebooks. Expect Intel to make similar inroads with the Ultrabook market.

Question: How much of the 28nm TSMC shortage has forced nVidia to focus its limited supply on desktop add-in cards instead of mobiles? It’s a Major Retreat that is likely unrecoverable.

Now consider Qualcomm and their 28nm ramp for the upcoming Apple iPhone5 and the Snapdragon all-in-one chip going into a wide range of non-Apple smartphones and tablets. Two months ago, it was revealed that they would not be able to meet demand until Q4. Now they won’t meet demand until the end of Q4 2012. As I speculated in a previous blog, I believe Apple has worked Qualcomm into a position that it has its supply needs met at the expense of its competitors and thus setting themselves up for a strong second half ramp with reduced competition from Samsung, HTC and the rest of the mobile players.

All of the above however doesn’t encompass the full extent of what is transpiring in the mobile semiconductor market and how Intel is prepared to increase its presence. Intel’s Medfield processor is late to the smartphone market but still competitive. Built in written off 32nm fabs, I presume Intel is cutting some very nice deals in order to ramp the product in volume and create havoc for nVidia, Mediatek, TI, Broadcom and Marvell. Qualcomm’s dominance at the high end with Snapdragon combined with Medfield at the low end will cause a market squeeze with several of the above exiting in the next twelve months.

Looking ahead to 2013, I expect Intel to enter the market with a 4G LTE solution and the mobile market merchant suppliers to narrow down to Qualcomm and Intel with Apple and Samsung continuing to develop for their own needs. If Apple gains significant market share in the Smartphone market over the next 9 months due to the 4G LTE supply situation, then I expect Intel will make inroads at Samsung with x86 Atoms. Samsung will have to do some serious soul searching as to whether it makes sense to design ARM based processors when Intel can offer solutions that are lower in cost and power and higher in performance – all due to Intel’s three to four year lead in process technology. If Samsung balks, look for Intel to leverage another player like HTC, Motorola to undercut the market.

Apple, unlike Samsung, can get Intel to build an ARM based processor in its fabs and likely has silicon running in its 22nm process at this moment. The dilemma they face is that going to Intel offers all the upsides mentioned above but the risk of losing other alternative suppliers. In addition, for Apple to get the best deal, they have to get to Intel before Samsung signs up. It is a true high stakes negotiation as Intel will try to land both Samsung and Apple at the exclusion of none.

Looking back over the past 18 months, one can see a definite trend that likely drove Paul Otellini’s decision to ramp 22nm hard last November. In my experience, the PC market has always had a need for processors built on the most leading edge process technology. Qualcomm is experiencing this same phenomenon today in the smartphone market with their 4G LTE chips. Intel, with its process lead, is making a bet that they will win the entire mobile market by 2014 when the successors to Medfield will integrate all functions, including baseband and be significantly cheaper, higher performance and lower power than anything its competitors can delivery. The Black Swan of 2011 likely gave Otellini the excuse he needed to break free from Wall Street’s quarterly demands in order to embrace the Mobile Tsunami Leading Edge Process End Game much sooner.

FULL DISCLOSURE: I am Long AAPL, INTC, ALTR, QCOM

Posted on

Fast Monte Carlo from Infiniscale at DAC

Fast Monte Carlo from Infiniscale at DAC
by Daniel Payne on 06-14-2012 at 10:56 am
Categories: EDA
5 Comments

Firas Mohamed, President and CEO (Ph.D.) of Infiniscale met with me on Monday at DAC to provide an overview of what EDA software they offer to IC designers at the transistor-level.


Vision – analog flow that Monte Carlo simulation is required, which is thousands of circuit simulations, however the higher the sigma the more simulations like 10,000 or 100,000 – way too slow, or too expensive to simulate.

Continue reading “Fast Monte Carlo from Infiniscale at DAC”

Posted on

IC Layout Tools from Japan at DAC

IC Layout Tools from Japan at DAC
by Daniel Payne on 06-14-2012 at 10:29 am
Categories: EDA
4 Comments

Last Monday I met with Nobuto Ono, VP Business development at Jedat (Japan EDA Technologies) while attending the DAC conference.

The company started in Tokyo and is Ex Seiko Instruments, in 2004.

Main product – layout editor for IC (SX 9000). New system is ALpha SX in 2002. 2007 listed on JASDAQ market. Like Virtuoso tools, based on OA for AMS design. Continue reading “IC Layout Tools from Japan at DAC”

Posted on

TSMC Theater Presentation: Atrenta SpyGlass!

TSMC Theater Presentation: Atrenta SpyGlass!
by Daniel Nenni on 06-13-2012 at 9:10 am
Categories: EDA, Foundries, TSMC

Atrenta presented an update on the TSMC Soft IP Alliance Program at TSMC’s theater each day at DAC. Mike Gianfagna, Atrenta VP of Marketing, presented an introduction to SpyGlass, an overview of the program and a progress report. Dan Kochpatcharin, TSMC Deputy Director of IP Portfolio, was also there. Between Mike, Dan, and I there are about 100 years of semiconductor ecosystem experience. If Paul McLellan was there it would be double that.

TSMC and Atrenta announced the Soft IP Alliance Program last year at DAC. The program uses a special set of SpyGlass rules specified by TSMC to validate that soft IP meets an established set of quality goals before it is included in TSMC online. The program leverages Atrenta’s SpyGlass platform that is used by about 200 companies worldwide to analyze and optimize their RTL designs before handoff to back-end implementation. SpyGlass checks things like linting rules, power, clock synchronization, testability, timing constraints and routing congestion. It highlights problems and provides guidance to improve the design.

SpyGlass can also be used as an IP validation tool, and this is the foundation of the Soft IP Alliance Program with TSMC and Atrenta. Atrenta developed a set of SpyGlass rules specifically tuned to verify the completeness and integration risks associated with soft, or synthesizable IP. Called the IP Kit, the integrated package also produces concise DashBoard and DataSheet reports that summarize the results of the IP Kit tests. Figure 1 shows an example of a DashBoard Report.

TSMC and Atrenta collaborated on the development of a version of the IP Kit that met TSMC’s requirements for delivered quality of soft IP. This technology formed the basis of the Soft IP Alliance Program, and testing of partner IP began last year. Deliverables for the Soft IP Alliance Program include: installation instructions, a reference design to test installation procedures, documentation, automated generation of all reports and a training module. For soft IP to be listed in TSMC Online, the DashBoard report must show a clean (or passing) grade for all tests. Figure 2 illustrates the kind of tests that are performed before IP is listed on TSMC Online.

At DAC this year, a progress report was presented on the results of the program. Ten IP vendors have joined the program, including Arteris, Inc., CEVA, Chips&Media, Inc., Digital Media Professionals Inc. (DMP), Imagination Technologies, Intrinsic-ID, MIPS Technologies, Inc., Sonics, Inc., Tensilica, Inc. and Vivante Corporation. Three additional soft IP vendors have recently joined the program as well.

TSMC and Atrenta are now working on the second generation of the soft IP validation test suite. This version will add physical routing congestion metrics. An update for the program will be presented at the TSMC Open Innovation Platform® Ecosystem Forum in San Jose on October 16, 2012. I hope to see you there!

Posted on

Carbonize your Imagination

Carbonize your Imagination
by Paul McLellan on 06-13-2012 at 7:00 am
Categories: EDA, Imagination Technologies, IP

Just up the road from Cambridge-based ARM in Kings Langley is Imagination Technologies, their biggest competitor in the GPU market. Interestingly they also were a customer of VLSI Technology in the early days back when they were called Videologic. Tomorrow, jointly with Carbon, they are announcing that a wide range of their PowerVR, Ensigma and Meta core IP will be available as 100% accurate virtual models from Carbon’s IP Exchange web portal.

Subject to approval from Carbon and Imagination (I’m guessing ARM need not apply!) users can download the models from the portal and drop them onto the design canvas. You can then do architectural design, pre-silicon firmware development and all the usual stuff for which virtual platforms are great.

More and more chips involve multimedia. Probably the most famous customer of Imagination is Apple: theirs is the GPU used in both the iPhone and the iPad. Funnily enough Apple doesn’t appear in their list of licensees on their website, I guess even though everyone knows that is what is in A4 and A5 (I believe Apple has actually said so) they still aren’t allowed to use the logo. But Imagination have other non-GPU cores for other markets too.

The models are implemented by Carbon using master data supplied by Imagination. This uses the same compiler to generate them from RTL as is used for ARM mdoels. But users can generate their own ARM models at the portal. The Imagination models are handcrafted on request (and require Imaginations permission).

Models available include:

  • PowerVR Series5, Series5XT and Series6 family of Graphics Processing Units (GPU)
  • PowerVR Series3 VXD and VXE families of video decoders and encoders
  • Ensigma Series3 UCCP family of multi-standard receivers and Wi-Fi/Bluetooth connectivity
  • Meta Series2 hardware multi-threaded SoC processors

Carbon’s website is here. Carbon IP Exchange is here.
Imagination’s website is here.

Posted on

How to Use Those Licenses Effectively

How to Use Those Licenses Effectively
by Paul McLellan on 06-12-2012 at 8:05 pm
Categories: EDA

So DAC is over and you are no longer thinking about the features and benefits of new tools or even the tools that you already own. But once you have lots of tools then you need to worry about how to use them efficiently.

But here are three things that you need to worry about to get the most out of your EDA investment:

  • how do you measure the actual license usage?
  • how do you build best of breed flows to encapsulate the tools you have invested in?
  • how do you maximize the use of the licenses you have invested in?

This is increasingly important since both the scale of the hardware infrastructure (server farms, perhaps with a wide range of different machines) and the scale of the jobs themselves (huge number of runs) are enormous.

Runtime Design Automation (RTDA) has three tools that address the three problems above and which scale to the size of the infrastructure and the jobs.

LicenseMonitor is a tool for gathering data on license usage and displaying it in useful intuitive ways. It operates with most license managers such as FlexLM.

FlowTracer captures all the details of a flow and so allows best-in-class flows to be created and deployed across an organization.

NetworkComputer is the fastest available commercial job scheduler. It interfaces with license managers to make efficient use of the licenses and can even statistically over-schedule. It can share licenses across an organization based on demand and policies, and use pre-emption to ensure licenses are allocated to important jobs (such as designs nearing tapeout).

As an example, RTDA told me about a typical timing run that a customer would make. It is a block flow of timing runs with 45 timing corners multiplied by plain/noise/interface-logic-models making 135 jobs in parallel (and 144 for the full-chip runs). This is completely distributed across a farm taking into account availability of both servers and licenses.

Download the LicenseMonitor datasheet.
Download the FlowTracer datasheet.
Download the NetworkComputer datasheet.

Posted on

Jasper’s Kathryn Kranen Elected EDAC Chairman

Jasper’s Kathryn Kranen Elected EDAC Chairman
by Paul McLellan on 06-12-2012 at 8:05 pm
Categories: EDA


Kathryn Kranen, CEO of Jasper was elected chairman of EDAC for 2012-2014. She has has 20 years EDA industry. She started her career as a design engineer at Rockwell International and then joined Daisy Systems (one of the DMV, the second generation of EDA companies). She then moved to be VP of North American sales at Quickturn (emulation) before becoming CEO of Verisity Design.

Wally Rhines (Mentor) and Lip-Bu Tan (Cadence) were elected vice-chairmen.
The other directors are Raul Camposano (Nimbic), Ed Cheng (Gradient), Dane Collins (AWR), Aart de Geus (Synopys), Dean Drako (IC Manage), John Kibarian (PDF Solutions), Simon Segars (ARM) and Ravi Subramaniam (BDA).

The EDAC press release is here.

Posted on

BDA TSMC Theater Presentation

BDA TSMC Theater Presentation
by Daniel Nenni on 06-12-2012 at 5:00 pm
Categories: EDA, Foundries, TSMC

I caught the Berkeley Design Automation presentation in the TSMC Theater, where Simon Young (BDA’s director of product marketing) described the Analog FastSPICE (AFS) nanometer circuit verification platform, built on their foundation of very fast, very accurate, high capacity circuit simulation.

BDA claims the AFS platform offers the fastest and most accurate circuit simulation, with single-core performance 5x to 10x faster than other foundry-certified simulators, and up to a further 4x faster with multithreading. AFS is consistently endorsed by designers of data converters, PLLs and DLLs, SerDes and other high-speed I/O, RFCMOS, and CMOS image sensors.

AFS is certified on several TSMC process technologies from 65nm down to 20nm through the TSMC SPICE-Qualification Program. In addition, BDA and TSMC have for several years collaborated on the device noise sub-flow for the TSMC analog and mixed-signal reference flow. Together the two companies qualified AFS’s full-spectrum transient noise analysis for this flow. A great many transient simulations are needed for this qualification process, including MOS white and flicker noise sources. Very close correlation to silicon is necessary for certification to be granted. These steps are repeated for a variety of complex mixed-signal IPs, including ADCs and PLLs.

Two recent customer example circuits illustrate the value of this qualification. Firstly, a closed-loop 14GHz PLL circuit from Analog Bits, designed for 100GbE applications, passed through performance signoff with AFS transient noise. Correlation between transient noise simulation and silicon was within 2dB. A second circuit, a delta-sigma ADC from Qualcomm, exhibited a 25dB increase in SNDR when AFS simulations including transient noise were run. Correlation between transient noise simulation and silicon was within 1.5dB. Many other examples were share last fall, at BDA’s nanometer Circuit Verification Forum.

AFS’s numerical noise floor is well below 160dB. Nanometer circuit designers demanding high dynamic range and high noise bandwidth value this accuracy. SPICE simulators achieve 60dB dynamic range with default settings, so tightening tolerances is required for trustworthy performance signoff of innovative architectures on nanometer process technologies.

Contrary to digital fastSPICE simulators that use table lookup models and an event-driven algorithm to deliver speed and capacity at the cost of accuracy, Simon compared the AFS Circuit Simulator to foundry-endorsed “sign-off” SPICE simulators. AFS solves the device analytical equations and the full matrix every simulation time-step. The difference is that tightening simulation tolerances doesn’t cause AFS to slow-down in the same way that other simulators do. And AFS always converges on a DC solution and runs transient simulation quickly, even for circuits above 10M elements.

For all this accuracy and speed, some designers want to run fast functional verification and don’t need nanometer SPICE accurate results. AFS offers a combination of user-selectable options to relax tolerances, simplify models, and simplify netlists (with RC reduction, for example). With these options set, AFS performance increases by another 4x to 5x.

Clearly, for nanometer accurate circuit simulation, 5x to 10x — or more — faster than alternatives, for large and complex circuits of 10M elements, foundry-certified AFS offers a great solution.