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Taiwan Travel Explained!

Taiwan Travel Explained!
by Daniel Nenni on 09-23-2012 at 7:00 pm
Categories: Foundries, TSMC
2 Comments

Whenever people hear that I travel internationally one week a month they cringe at the thought of crowded airports, 12 hour flights, jet lag, and days packed with meetings. I generally shrug, accept the label of travel warrior, and say it is all part of doing business in the semiconductor ecosystem. But in reality, it is not as bad as it sounds, especially if you include the knowledge gained as part of the ROI calculation.

First and foremost, I rarely travel alone. As a business consultant I work for the CEOs of emerging technology companies advising them on a variety of topics. I wish I could say they learn more from me than I do from them but that is rarely the case. Successful emerging technology CEOs are a unique breed and are almost always a pleasure to work with. These CEOs wear so many hats and work so many hours that I get a headache just thinking about it. Every trip brings new problems and new ways to solve them which is an excellent learning experience on many different levels.

As a frequent traveler, I get perks from airlines and hotels fit more for a king than a regular working person. Executive lounges at airports are a good example. Right now I’m in the EVA airlines Evergreen Lounge sipping champagne and eating rice crispy treats (I don’t like caviar). Seat upgrades, personalized in-flight service, priority baggage handling etc…, it really does take the sting out of air travel. Even the airport garage I park my car in has frequent parking perks: Car washes, oil changes, priority shuttle services etc…

The hotels are the most generous. I get corporate rates for the cheapest rooms and the upgrades just keep coming. The rooms I usually get are huge with every modern convenience you can imagine. Sometimes the bathrooms are absolutely amazing. As you approach the toilet the seat raises, auto flushes, washes and dries, and closes as you walk away, semiconductor technology at its finest! The hotel welcome baskets are quite tasty and quite fattening, so I always bring my gym clothes to burn the extra calories that come with travel. Exercise also helps with jet lag. Another way I avoid jet lag is to NOT eat airline food and drink lots of water, believe it.

The boxes in the picture are Taiwan tea which is an interesting story in itself. A fellow international traveler convinced me that green tea is the key to a long and fruitful life and I have been drinking it ever since. That was more than ten years ago and I still believe it. I started with Japanese green tea but now Taiwan tea is my favorite.


In the hills right above the TSMC fabs in Hsinchu Science Park is one of the more famous green tea farms which I visit quite frequently. As the Taiwanese tea legend goes:

A tea farmer’s crop was infested by little green-leaf worms. Trying to recover from this catastrophic loss, the tea farmer went into town to sell his low-grade tea anyway. As it turns out the tea had a unique flavor and gained huge popularity. This guy was a great salesman for sure! When the tea farmer returned to his village and told the story it was viewed as bragging so they called his tea “puffing tea”, puffing means bragging in Taiwanese. The legend also says that Puffing Tea was a favorite of Britain’s Queen Victoria (1800’s) and she gave it the name Oriental Beauty Tea. European aristocrats later named it Champion Oolong Tea.

The tea is harvested three times a year. In the spring it is green tea (the green box) which has a mild flavor. Next harvest is orange tea. Fall harvest is red tea with the strongest flavor. If you look on the top of the boxes there are pictures of green-leaf worms which determines the price. The more worms the higher the price. There is more on Taiwan Tea Farms HERE. Even though Starbucks has invaded every corner of Taiwan, tea is still a big part of modern life here.

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Cadence Mixed Signal Technology Summit

Cadence Mixed Signal Technology Summit
by Paul McLellan on 09-21-2012 at 6:46 pm
Categories: Cadence, EDA
1 Comment

Yesterday I attended some of the Cadence mixed-signal technology summit. The day ended with a panel session on Are We Closing the Gap Yet in Mixed-signal Design? Richard Goering moderated. The panelists were all mixed signal experts:

  • Nayaz Khan of Maxim
  • Nishant Shah of Broadcom
  • Shiv Sikand of IC Manage
  • Bill Meier of Texas Instruments
  • Bob Chizmadia of Cadence

The panelists were invited to say which gaps have been closed and where the current gaps are. There seems to be a large amount of agreement, in fact, in both the panel session and some of the sessions earlier in the day.

Problem #1: Adding analog into the digital flow is a sort of second class citizen, especially when trying to use SystemVerilog. Especially Connect Modules. And never mind multi-language.

Problem #2: People need to know a lot. Finding individuals who can work with object-oriented code and understand analog and understand power is really hard. As a result, AMS designs require an extra level of support. TI even have a program called AMSmadeEZ the Bill heads up. Ideally you want a separate team for AMS verification since it is much more effective if people do it a lot and not just a couple of times per year. TI and Maxim seemed to do this.

Problem #3: It is really hard to keep all the files aligned between the analog world and the digital world. Especially keeping the models the digital people need of the analog aligned with the analog development itself. Hierarchy doesn’t always match. Wires can only carry voltage or current but not both, further complicating things. AMS assertions don’t work the same in all the different simulators.

Problem #4: When using CPF (for power policy) in the digital world it works well. But the checks with analog are not clean. There is no way to ensure that when a domain is powered down that an analog gate doesn’t float, for example. Or if the analog already contains a level shifter to make sure it doesn’t get doubled.

Problem #5: At 20/22nm and 14nm the problems are daunting. The process, tools and methodology are all developed concurrently. The number of design rules explodes. Variability goes way up.

On the other hand there have been huge advances in the last 5 years. Back when I was at Cadence we kicked off a program called Superchip that was supposed to merge the analog and digital design environments and also move them onto OpenAccess. It rapidly became clear we were years away from being able to do that (despite sales having committed it to a huge customer who had better remain nameless). But a lot of that vision is now a reality.

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Atrenta Wins Gold

Atrenta Wins Gold
by Paul McLellan on 09-21-2012 at 6:16 pm
Categories: EDA

What is the most read article on design on EE Times website? Brian Bailey has an article up running through the top 10. It turns out that the #1 article is Understanding Clock Domain Issues by Saurabh Verma and Ashima S. Dabare of Atrenta. It actually had more than double the views of the second place paper. Checking clock domain crossing is complicated but really important. I’ve been suprised at how many views blogs get here when I write about it.

But wait, there’s more. Atrenta also had a second article in the top 10. Coming in at #9 is Power Awareness in RTL Design Analysis by Narayana Koduri.

But wait, there’s even more. John Cooley does a survey of users at DAC. The #1 hot tool at DAC was SpyGlass Power. Well, it was actually first equal, sharing the spot with Calypto’s PowerPro RTL and Apache’s PowerArtist. Clearly power reduction is a hot(!) topic.

For the silver medal, in Cooley’s #2 place, was Atrenta IP Kit (sharing with IC Manage’s IP Central and Sonics SGN). Design really is changing towards much more of an IP assembly process and ensuring the quality of the IP and managing all the views is really important.

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The End of an Era

The End of an Era
by Paul McLellan on 09-21-2012 at 5:45 pm
Categories: General
1 Comment

I drove down from San Francisco, where I live, to Silicon Valley this morning. Something odd was going on. As I approached San Francisco Airport there were a couple of buildings with lots of people standing on the roof. As I got further south, the bridges over the freeway all had lots of people just milling around. It was when I got to Moffat and the crowds were huge that I remembered that the space shuttle was passing through the bay area on its way to its final home in Southern California.

I was actually in a conference room when the shuttle flew by, but somehow we managed to miss it even though we were supposedly facing in the right direction. But John Linthacum, a Cadence AE, didn’t. He got the picture above (click for a larger version).

Who knows whether there will ever be manned space program again in our lifetimes? As the capability of computers improves and technology like driverless cars becomes mainstream, the advantages of manned versus automated exploration get less and less. Of course a lot of the improved technology comes about as a result of improvements in semiconductor manufacturing and in EDA that drives it (obligatory semi reference to justify blogging on SemiWiki).

It is a fun coincidence that the Mars rover Curiosity should have just landed there at roughly the same time as the Space Shuttle finally goes to its retirement home. When I heard about the process by which it landed, with a mother ship and the strongest parachute ever built and a sort of flying saucer lowering the rover onto the surface it seemed unlikely to work. Remember it is minutes away for any radio signal so it is a completely automated landing sequence. Mars was so far away that it took 14 minutes for the Jet Propulsion Laboratory (JPL) to even know it had landed successfully, touching down at a vertical speed of about 2 feet per second.

But for sure it feels like the end of an era…

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Displaced but Looking to Add EDA Tools Skills?

Displaced but Looking to Add EDA Tools Skills?
by Daniel Payne on 09-21-2012 at 1:12 pm
Categories: Cadence, EDA
1 Comment

In this tough economy you may find yourself displaced and looking for the next opportunity. If you’d like to add some new EDA tool skills, then check out what EMA Design Automation is offering with free Cadence OrCAD training. Continue reading “Displaced but Looking to Add EDA Tools Skills?”

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Virtual Prototype your SoC including Arteris FlexNoC and optimize architecture using CPAK from Carbon

Virtual Prototype your SoC including Arteris FlexNoC and optimize architecture using CPAK from Carbon
by Eric Esteve on 09-21-2012 at 7:37 am
Categories: Arteris, EDA, IP

I have talked about Virtual Prototyping a SoC including FlexNoC Network on Chip IP from Arteris by using Carbon Design Systems set of tools in a previous post. A blog, posted on Carbon’ web, is clearly explaining the process to follow to optimize a fabric (FlexNoC) successively using the different tools from Carbon. Bill Neifert, CTO with Carbon Design Systems introduces the SoC context: “Fabric optimization is a prime area for architectural analysis. SoCDesigner Plus is an ideal tool for this and since it’s the only virtual prototype tool which will deliver 100% accurate results it’s extremely valuable for making crucial design decisions. It also made a lot of sense as well that Arteris IP would be requested. Their constant stream of press releases with customer design wins is pretty strong evidence of how widely their IP has been adopted.”

The first step is to create a 100% cycle accurate models of Arteris FlexNoC interconnect models by using Carbon Model Studio. To do so, Eric Sondhi from Carbon has used the FlexNoC project file (.PDD file) that matched AXI interconnect configuration and initial memory map definition of the system, this project file being generated either by Arteris, or by the designer using Arteris’ tools. Then, entering the project file into the FlexNoC tool to generate the Verilog RTL for the specific FlexNoC, lead to the 100% cycle accurate description. As Eric Sondhi point it out, the value that 100% cycle accurate models provide by enabling SoC developers to guarantee their functional behavior and performance results will match final silicon is huge!

Screenshot of the Arteris FlexNoC CPAK

At this stage, the SoC designer can start virtual prototype the design, providing he has already created (or re-use) the various models describing the different functions, also generated by Carbon Model Studio. Virtual prototyping is done by assembling the different models together, with SoCDesigner Plus tool from Carbon. Once this task has been completed (there is a very accurate description of this process in Eric’s blog), the designer can start “to have fun”, and move to the Carbon Performance Analysis Kits (CPAK) tools.

A9 Read Latencies from FlexNoC Input

This last step is precisely described by Eric on a real-world ARM Cortex A9 based system with DMA-like traffic generators running Carbon’s ARM boot & initialization code with Performance Validation software provided in some of other CPAKS from carbon. For SoC architect, this should be the most amazing task, where he runs SoC performance analysis simulations and observe latency on both sides of the FlexNoc, then try various options in order to optimize architecture.

Read Latencies from FlexNoC Output

At this stage, you should go and read Eric’s blog to more precisely all the possibilities offered by the joint Carbon/Arteris solution, as it offers design teams a way to easily create and import accurate Arteris FlexNoC interconnect models for Carbon SoCDesigner Plus: the new Carbon/Arteris flow allows Carbon’s SoCDesigner Plus users to use Arteris FlexNoC to configure their NoC interconnect fabric IP and then upload the configuration to Carbon IP Exchange. The web portal then creates a 100% accurate virtual model of the configuration and makes it available for download and use in SoCDesigner Plus. “We see strong demand for models of Arteris’ NoC interconnect IP,” states Bill Neifert, chief technology officer at Carbon Design Systems®, the leading supplier of virtual platform and secure model solutions. “Our partnership with Arteris enables engineers to make architectural decisions and design tradeoffs based upon a 100%-accurate virtual representation.”

By Eric Esteve from IPNEST

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Over-under: Apple, 52M iPhones in 4Q

Over-under: Apple, 52M iPhones in 4Q
by Don Dingee on 09-20-2012 at 8:15 pm
Categories: General
6 Comments

I’m in a Twitter conversation with some friends, with the subject: how many phones can Apple ship in the 4th quarter?

A respected analyst said 52M is “an easy mark” for Apple; others are saying 58M is the target for just the iPhone 5 in 4Q. However, the start for the iPhone 5 has been anything but easy. Oh, the orders are probably there – 2M iPhone 5 orders in 24 hours indicates really strong demand.

It’s been a good year. Apple’s 1Q iPhone shipments were 35M units, 2Q were 26M units, and we’re obviously waiting on a figure for 3Q.

The questions for 4Q are two-fold, however. One is supply, the other is demand.

Apple’s supply problem is pointing to their selection of a Sharp 4″ LCD display, at least for the initial build. Rumors have it the yield at Sharp is less than 40%. Other sources are LG and Japan Display, but no word on how well they will ramp up. Sources say capacity of each supplier is something like 7M units per month, if everything goes right. There are also unspoken concerns about the A6 chip inside, but my guess is Samsung has that pretty well in hand. Since the display and memory have been taken away for the iPhone 5, Samsung doesn’t want to be the long pole in the tent on the A6.

Then there’s demand. Apple is now saying they are 3 to 4 weeks from filling the initial orders. I’d also question how prior demand for iPhone 4S units will hold up in the face of iPhone 5 availability. Both those factors may slow down the frenzied pace of orders just a bit. One thing that might help would be if Lucy Koh somehow puts the kibosh on shipments of the Samsung Galaxy SIII. There’s also the remote possibility that the Nokia Lumia 920 and the just announced HTC 8x will ship as expected in time for the holidays, Microsoft willing, and might actually take some demand.

The numbers being tossed around for Apple are huge, to the point where one has to question if they can ship as many orders as they can book. I have no doubt this gets worked out in 2013, but the pressure is on and I think 4Q12 is in some doubt.

I say “under” 52M, with new, untested suppliers in the critical path. Discuss.

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Damn! Cramer Figured It Out

Damn! Cramer Figured It Out
by Ed McKernan on 09-20-2012 at 8:04 pm
Categories: Uncategorized

As an investor, one has to always be aware when Jim Cramer informs the world of the investment scenario you have been playing comes out of the shadows and sees the light of day. Soon the herd will follow which is positive, but now one has to figure how long to ride the roller coaster. In an article posted on thestreet.com entitled “Tech is Treacherous”, Jim Cramer bemoans the fact that it is September and the annual seasonal trade for technology stocks doesn’t appear to exist outside of Apple and its derivatives (Qualcomm, Broadcom and Cirrus Logic). What is going on?

The PC, if I can be blunt is becoming unfashionable. I must have bought or built at least 15 of them since the late 1980s, but I have recently been taken in by my wife’s iPAD with 4G. If I can get my company to outlaw powerpoint, then I can completely convert and drop a few pounds from my Hartman bag. Many of you are probably thinking the same thing and it doesn’t necessarily have to be Apple. Samsung and Amazon have you covered as well. We want devices that can be carried in only one hand and the option to have a keyboard or not.

The economics and the trends of the Mobile Tsunami are shaping up to be more powerful as they become substitutions and not additions to our PC environment. Winners become losers, or should I say travellers on the road to extinction because the Device Makers have decided to go Vertical in the supply chain, cutting out Intel, nVidia, AMD while reducing Toshiba, Micron, Elpida and others to a subservient status. Apple makes 90% margins on NAND Flash upgrades as it rides the cost curve down without increasing density and therefore this makes it difficult for NAND players to envision a future of making money.

The battlefield for the coming year is to be played out in the $500-$999 market segment that Intel has designated as the heart of the volume ultrabook computer. Apple has held the Mac Air up at $999, allowing the iPAD to be its product line to occupy the space with its average performing $20 processor. Meanwhile, Intel expects to receive between $100 – $200 for its ultrabook processors. The dilemma then is not just the processor price disparity but the form factor and the O/S. If the consumer and corporate purchaser turn away from 13” LCD based notebooks or the Microsoft Win 8 O/S, then there is no price that Intel can sell processors at that will win the market. Just to be clear, I do believe there will be a >$1000 corporate market for notebooks. It will, however, be the consumer who turns first and serve as the canary in the coal mine.

And so back to Jim Cramer. He is getting close to the truth without understanding the complete picture. Back in the good old mainframe days, IBM was vertically integrated and highly profitable. In the early 1980s however, they found themselves way behind the curve in the nascent personal computing market. Don Estridge’s newly formed group was given the flexibility to outsource the semiconductor components and the Operating System, thus the creation of Wintel and what would become the vast horizontal supply chain that profited immensely during the next 20 years. Now, though, we are returning to the Vertical Integration Model through the example of Samsung and Apple. Google and Amazon may follow, but options are limited. Perhaps Intel will step in to be the Semiconductor Foundry for $15 processors and $25 baseband chips and hope that the Foundry model doesn’t creep up in to the higher PC price bands and swallow them like Ivy Bridge is expected to do to AMD and NVIDIA.

The surprise to many this year is that the Smartphone and Tablets are pushing the envelope on leading edge process. One node back will not do when low power and integration drive out costs or increase battery life. Global Foundries announcement that they will have a 14nm production process in 2014 completes the picture that every foundry has to jump into the leading edge pool or be left high and dry. This however doesn’t guarantee profitable. More likely Qualcomm and Apple will continue to squeeze down on the Foundries who will be investing heavily in semiconductor equipment and thus create a new, unexpected winner in the Mobile Tsunami Race: ASML.

If this scenario unfolds and ASML turns out to be a growth proxy for the Leading Edge Semiconductor Industry then it will be ironic that the investment provided to it by Intel, Samsung and TSMC will be in many ways analogous to IBM buying a 20% stake in Intel in the early days of the PC to ensure that it had the R&D funds to develop future x86 processors. That investment turned out to be exactly at the beginning of the great semiconductor growth cycle of the 1980s.

FULL DISCLOSURE: I am Long AAPL, INTC, QCOM and ALTR. I am not invested in ASML but may do so next week or afterwards.


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2nd International Workshop on Resistive RAM at Stanford

2nd International Workshop on Resistive RAM at Stanford
by Ed McKernan on 09-20-2012 at 8:02 pm
Categories: IP

A Veritable who’s who of ReRAM researchers will be present at the 2nd International Workshop on Resistive RAM at Stanford in the beginning of October. Sponsored by IMEC and Stanford’s NMRTI (Non-Volatile Technology Research Initiative), the program features two days of talks, panel sessions and no doubt lots of networking. The advanced program is online and over at ReRAM-Forum.com, moderator Christie Marrian has some observations on the topics and presenters. While there is a true global presence, there are some intriguing sounding talks from local Si valley companies, Adesto, Intermolecular and Rambus. For more information on the workshop visit www.ReRAM-Forum.com.

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Automating Complex Circuit Checking Tasks

Automating Complex Circuit Checking Tasks
by SStalnaker on 09-20-2012 at 7:24 pm
Categories: EDA, Siemens EDA
2 Comments

By Hend Wagieh, Mentor Graphics

At advanced IC technology nodes, circuit designers are now encountering problems such as reduced voltage supply headroom, increased wiring parasitic resistance (Rp) and capacitance (Cp), more restrictive electromigration (EM) rules, latch-up, and electrostatic discharge (ESD) damage, which are all sources of possible circuit failure. While none of these effects suddenly appeared in the nanoscale era (sub-130nm), they have become progressively more serious, and must now be addressed during circuit verification to ensure robust designs and reliable operation.

ESD protection is one of the most important reliability issues in today’s CMOS integrated circuit (IC) products. ESD failures caused by thermal breakdown due to high current transient, or dielectric breakdown in gate oxide due to high voltage overstress, can result in either immediate failure of IC chips, or gradual degradation of circuit performance. To obtain high ESD resistance, CMOS ICs must be designed with on-chip ESD protection circuits at the input/output (I/O) pins and across the power lines. Turn-on-efficient ESD protection circuits clamp the overstress voltage across the gate oxide to limit the voltage swing.

The conventional approach to checking such circuitry is to use DRC rules to target areas of a layout that have potential reliability issues to check, which requires adding extra layers called “marker layers” to the IC layout database. Adding marker layers is a manual process, making it ripe for mistakes, and requires additional DRC runs, which extends verification time.

A better solution is provided by a circuit verification tool that automatically identifies the reliability-sensitive geometries and applies specialized physical checks to catch real design problems that impact circuit reliability. The Calibre® PERC™ tool uses information from an IC’s netlist to identify circuit topologies of interest, such as possible ESD paths and probable electrical failure sources, as well as the presence or absence of ESD protection circuits. For example, protection circuits are identified by recognizing device types and connectivity patterns based on any of the ESD configurations commonly known and widely used in designs today (Figure 1). Beyond verifying that the required circuits are present and connected properly, Calibre PERC measures the layout to ensure that interconnects are sufficiently sized to meet a maximum current density requirement. This can be accomplished without the need for marker layers or other manual interventions.

Figure 1. Some commonly used ESD protection configurations

The ESD EDA working group has defined and recommended 39 ESD checks that can be implemented using Calibre PERC to assure a reliable design that is robust against ESD events and electrical failure. In these checks, ESD verification is performed on multiple levels, from cell level to package level, including intra-and inter-power domain ESD checks.

As an example, to implement verification of ESD protection between I/O and power rails, the tool performs the following steps:

[LIST=1]

  • Identify the core circuit that requires ESD protection.
  • Check that the correct ESD protection devices are being used, and are appropriately connected to the core circuit.
  • Check that there are no violations in the ESD protection device connection polarity.
  • Check the sizes of ESD devices against existing ESD sizing rules (to meet current density requirements, clamp width requirements, etc.).

    Since the tool is programmable, ESD checks can easily be expanded to cover parasitic extraction on metal interconnects, and design rule checks on selected ESD topologies, protected circuits, or violating circuits. It can also validate electrical compliance by performing resistance and current density analysis to ensure that the wiring of these devices is robust enough to support the largest currents that can be induced (Figure 2).

    Figure 2. Calibre PERC can address P3P extraction in the physical design, perform current density analysis, and execute design rule checks on identified topologies.

    Automatic voltage propagation of input sources through the design, and voltage-dependent DRC checks, provide additional capabilities to simplify complex circuit verification. For example, the tool can be used to perform advanced electrical rule checks (AERC), which identifies signal lines crossing voltage domains in mixed-signal or multi-domain low power digital designs.

    Additional information about advanced ESD checking can be found in the white paper entitled Solving Electrostatic Discharge Design Issues with Calibre PERC.

    Hend Wagieh is a Senior Technical Marketing Engineer for Calibre Design Solutions at Mentor Graphics. She may be contacted at hend_wagieh@mentor.com.