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Samsung going vertical Qualcomm cry CEVA laugh

Samsung going vertical Qualcomm cry CEVA laugh
by Eric Esteve on 09-27-2012 at 11:09 am
Categories: Ceva, Intel Foundry, IP
2 Comments

These last days have been full of Apple related stories; maybe it’s time to discuss a new topic? Like for example Samsung, direct competitor for Apple in the smartphone market, and take a look at the company move toward more vertical integration. Everybody working in the SC industry knows that Samsung is ranked #2 behind Intel, even if the two companies SC products mix are pretty different. When Intel revenue is essentially coming from processor, Samsung SC revenue is coming from 3 families: DRAM, NAND and System LSI. As you can see from the Quarter by Quarter revenues from the last four years, System LSI revenues are drastically growing, both in value and, even more important, in percentage of overall SC sales. “System LSI” sounds almost obsolete as a name for a product line, but when you realize it represents products like Exynox (Application Processors) or CMC221S (2G/3G/4G Baseband GSM/WCDMA/LTE), in direct competition with, for example, Qualcomm MSM8960 integrated Application Processor, Texas Instruments OMAP5, or Apple A6, you then consider the System LSI name more respectfully…

If you look at the Bill Of Material (BOM) for a smartphone, you can see that there will always be DRAM, NAND Flash and an Application Processor plus a Baseband Processor (or an integrated AP + BB). You can imagine that Samsung top management has made this analysis some time ago, when they decided to heavily invest in developing top class smartphones, considering that manufacturing the high value above mentioned SC content was a good way to keep the value inside the company, which is the definition of the vertical integration: try to develop (and manufacture if it make economic sense) as much as possible of the various parts of a system, and the system itself.

Let’s focus on these non-memory semiconductors: Application Processor and Baseband processor, as these two are the heart of a smartphone and both part of System LSI. Samsung is not part of the handful pioneers of the wireless industry, like Nokia, Ericsson, RIM or Panasonic, and Samsung SC has entered the wireless chip segment more recently than the Qualcomm, TI or ST-Ericsson. This position can be seen as a challenge, but it also gives the new comer a competitive advantage. The company can select very quickly the winning solution, ARM IP core for the application processor, and CEVA DSP IP core for the baseband processor, when the pioneers have made some experimentation at the early days, sometime going to a dead end.

When Samsung (OEM) builds smartphone, the company can select the chips which best fit the need for a specific product, or even a specific market for the same product. We have a good example with the Galaxy Nexus LTE, using TIOMAP 4460 AP, Samsung CMC221 LTE Baseband and VIA Telecom CBP 7.1 CDMA Baseband, to be compared with the Galaxy S3 LTE supporting Korean operators, integrating Samsung devices for both the AP and the Baseband. In this case, both products integrates Baseband developed around CEVA DSP IP, as VIA Telecom also licenses CEVA products.

But the road for a complete vertical integration is long, and certainly passes by compromises, as Samsung (OEM) does not necessarily integrate Samsung SC products. We have a good example with these three variant of the Galaxy S3, in Korea, Europe and US. The Korean product, as above noticed, is 100% Samsung for the AP and the Baseband, when the product sold in Europe integrates a Baseband from Intel Wireless (Infineon for those who remember). By the way, in both cases, the Baseband also rely on a CEVA DSP IP core for the processing, as Intel Wireless licensee CEVA as well. The Galaxy S3 sold in the US is based on a Qualcomm MSM8960, integrated 2/3/4G Baseband and Application processor. This is strength for Qualcomm as Samsung are one of the biggest revenue drivers for the company today. It also represents a significant threat to Qualcomm as Samsung is going toward more vertical integration…

This vertical integration strategy represent a huge opportunity for CEVA: from a DSP perspective, Samsung exclusively use CEVA DSPs for their LTE designs, so this represents a very strong LTE driver for CEVA. Interesting to notice, many of CEVA’s other customers supply chips into Samsung handsets today, including Broadcom, Intel, ST-Ericsson, Spreadtrum and VIA telecom. A rough estimation (from CEVA) is that CEVA ships in more than 50% of all Samsung handsets today and that market share continues to grow, as Samsung tend to use non-Qualcomm Baseband solution. This did not happen by chance: CEVA has been a long time partner and is the DSP inside Samsung’s LTE roadmaps, as we can see from this press release from 2010 that Samsung has been using CEVA for its LTE development. That’s why, when Samsung is going further in vertical integration, as well as gaining market share in the smartphone segment (the market segment where most of the profit of the overall handset market are made), Qualcomm could cry, Apple displace the fight in the legal field… and a much smaller but successful IP company, CEVA DSP, will laugh!

By Eric Esteve from IPnest

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A Brief History of Atrenta and RTL Design

A Brief History of Atrenta and RTL Design
by Daniel Nenni on 09-26-2012 at 7:41 pm
Categories: EDA
9 Comments

We’re plagued by acronyms in this business. Wikipedia defines RTL as follows: “In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.” This is kind of wordy for my taste. I’ve always thought of an RTL description as “what” the circuit does and not necessarily “how” it does it.

Increasing complexity has forced designers to retreat to higher levels of abstraction. You just can’t deal with all the issues at the gate level anymore, time and money won’t allow it. This trend has created a new EDA market segment for RTL design tools. RTL design has been around for a long time – over 20 years – but the market has seen some significant growth in the last 10 years, owing to the need to deal with design abstraction at a higher level due to complexity. Another way to think about this market is that it’s the pre-synthesis part of the design flow. Everything you do at RTL is basically intended to maximize the chances that the synthesis/place & route flow will go smoothly and there won’t be any surprises or fire drills. Things like lack of timing closure, not fitting in the package or not meeting the power budget all constitute fire drills in this context.

The Big 3 offer RTL design tools, but so do a whole host of other smaller companies. There are quite a few startups that focus exclusively on this market. If you think about it, this makes sense. The back-end flow is dominated by the Big 3, and that flow is becoming increasingly commoditized. It’s not a good place for a small company to try and break into. On the other hand, the design flow above the back-end has plenty of growth opportunity. To get another perspective on this market and how it has evolved, I turned to a guy who has been at it for quite a while – Ajoy Bose. He is the founder of Atrenta, the company that builds SpyGlass. This product has become something of a de-facto standard for RTL design. It’s so popular, the company actually re-branded themselves as “the SpyGlass Company” at DAC this year.

Ajoy is no stranger to RTL design, having led the team that developed the Verilog simulator at Cadence in its early days. When I asked Ajoy how Atrenta got started, I was surprised at the answer. In the late 1990’s, he was running a services company called Interra. One of their projects was to work with a large semiconductor company to help them develop a better methodology for IP reuse. During that project, they developed a piece of software that looked at a synthesizable description of an IP to see if it had any design constructs that would be inherently difficult to reuse. The project was a big success, and Ajoy and the team realized they were on to something. Could that software be generalized and made available as a product, and not just service-ware? The team thought so, and so Atrenta was born in 2001. I’m not sure if it was luck or extreme wisdom, but the Interra contract allowed the company to retain rights to the software they built for that services customer. That came in handy. Atrenta productized the code, and a new generation of RTL linting was born in the form of SpyGlass.

It seems that testability analysis was added next, then clock domain crossing (CDC) analysis followed by power and so on, creating a complete RTL platform all under the brand of SpyGlass. Today, there are probably a dozen companies all competing for your RTL analysis dollars. Some specialize in power reduction, some focus on CDC analysis and others on timing constraints. Everybody seems to have a linter. It’s good to see this level of competition from smaller companies. It suggests maybe there is growth opportunity in EDA after all.

I wondered where the next level of growth could come from in this market, so I went back to Atrenta. When I asked Ajoy that question, he paused for a moment and then said “if you’re looking for growth, never look down. Look sideways or look up.” It took me a minute, but I got the message. Sideways means adding more or better tools to the RTL flow. Different approaches to simulation and verification come to mind as one area for growth. Atrenta’s recent acquisition of NextOp looks like that kind of play. When you look up, there are lots of opportunities. The level above RTL includes things like SystemC. Anyone up for an integrated high-level synthesis to gates flow? I’d say there’s still a lot of work to do on that one.

Links to software is another interesting one. What if your RTL description can create a model that is accurate enough and fast enough to run software? You could then iterate the hardware design based on the way the software performs. Real hardware/software co-design. I suspect whoever gets that right will make some serious money.

Also see: A Brief History of RTL

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Mentor Graphics Update at TSMC 2012 OIP

Mentor Graphics Update at TSMC 2012 OIP
by Daniel Payne on 09-26-2012 at 10:45 am
Categories: EDA, Foundries, Siemens EDA, TSMC

What
In just 20 days you can get an update on four Mentor Graphics tools as used in the TSMC Open Innovation Platform (OIP). Many EDA and IP companies will be presenting along with Mentor, so it should be informative for fabless design companies in Silicon Valley doing business with TSMC.
Continue reading “Mentor Graphics Update at TSMC 2012 OIP”

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iPhone 5: Boost to semiconductor market?

iPhone 5: Boost to semiconductor market?
by Bill Jewell on 09-25-2012 at 11:03 pm
Categories: Arm, IP, Semiconductor Intelligence
13 Comments

The release of Apple’s iPhone 5 has led to much speculation on its impact on the economy. An analyst at J.P. Morgan estimated the iPhone 5 could add $3.2 billion to U.S. GDP in the fourth quarter, adding ¼ to ½ point to the GDP growth rate.

Analysts’ estimates for total iPhone sales in 4Q 2012 are in the range of 46 million to 50 million units. iSuppli estimates the semiconductor content of the iPhone 5 at $154 for the 16G model, $165 for the 32G, and $175 for the 64G.

In the fourth quarter of 2011 when the iPhone 4s was released, 89% of iPhone sales were the 4s, according to Consumer Intelligence Research Partners. Assuming 90% of iPhone sales in 4Q 2012 are 5’s and total iPhone sales of 48 million units results in 43 million iPhone 5’s. Assuming $165 average semiconductor content, the 43 million iPhone 5’s would generate $7.1 billion in semiconductor sales in 4Q 2012.

Our latest forecast at Semiconductor Intelligence for the year 2012 semiconductor market was $297 billion, a 1% decline from 2011. Adding $7.1 billion from iPhone 5 semiconductors would result in a $301 billion semiconductor market in 2012, a 1.4% increase from 2011.

However these numbers are not realistic. The underlying assumption in the above estimates is that people who buy iPhone 5’s in 4Q 2012 would not have bought any other mobile phone in 4Q 2012. It also assumes the money people spend on iPhone 5’s does not displace money they might have spent on other electronics purchases. The table below shows IDC estimates of total mobile phone sales and smart phone sales. iPhone sales numbers are from Apple and other smart phone sales are calculated. The last two columns show the change in millions of units for smart phone sales compared to the prior quarter. The forecasts for 3Q 2012 and 4Q 2012 mobile phone sales are from Semiconductor Intelligence (SI) and other analysts.

Over the last three years, sales of iPhones have declined in either the quarter before or the quarter of a new iPhone release. Many buyers delayed purchasing iPhones until the new model was released. After the release of the new model, iPhone sales grew strongly. However sales of other smartphones showed similar or stronger growth.

iPhone sales in 2Q12 were down 9 million units (inanticipation of the iPhone 5) while other smart phone sales were up 18 million units. Despite the surge in iPhone 5 sales in September, 3Q12 iPhone sales will be up only about 1 million units while other smart phone sales will be up about 15 million units. Semiconductor Intelligence believes 4Q12 other smart phone sales will be up 19 million units, close to the 21 million unit increase for mobile phones.

Semiconductor Intelligence forecasts total smart phone unit sales will be up 40% in 2012. However total mobile phone sales will be up only 2%. Thus the decline in non-smart phones almost offsets the increase in smartphones. Since the semiconductor content of smart phones is higher than non-smart phones, the semiconductor growth in total mobile phones should be higher than 2%.

We at Semiconductor Intelligence are making no adjustments to our 2012 semiconductor market forecast due to the iPhone 5. Strong iPhone shipment growth in 4Q12 is largely offset by weak iPhone shipments in 2Q12 and 3Q12. Strong sales of smart phones are at the expense of non-smart phones, resulting in weak total mobile phone growth. With the current weak economic environment, any boost in consumer spending on iPhone 5’s will likely be at the expense of other consumer electronics such as media tablets, notebook PCs and HDTVs.

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Aldec-Altera DO-254

Aldec-Altera DO-254
by Daniel Nenni on 09-25-2012 at 9:58 pm
Categories: Aldec, EDA, FPGA

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements describing FPGA I/Os must be verified by test. The problem is that testing the FPGA device at the board level provides very low FPGA I/O controllability and visibility, therefore, giving you the inability to verify specific requirements by test.

In this webinar, Aldec will demonstrate how you can verify all FPGA level requirements by test. All of the requirements verified during simulation can be repeated and verified in the target device. We will demonstrate a unique solution that enables requirements-based test by reusing the testbench as test vectors for testing the device at-speed.

In this webinar, Altera will also share insights into the market trends observed from different applications and discuss some of the solution strategies that will address the system reliability concerns. Using the Altera-Aldec partnership as an example, Altera invites collaboration and partnership to address the industry needs.

Live Webinar Presenters
Louie De Luna, Aldec DO-254 Program Manager
Ching Hu, Altera Military BU, Sr. Marketing Manager

[TABLE] cellspacing=”10″ style=”width: 100%”
|-
| US Session
Date:September 27, 2012
Time:11:00 am – 12:00 pm
Pacific Daylight Time (USA)
Register for US Session
|-
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|-
| EU Session
Date:September 27, 2012
Time:3:00 pm – 4:00 pm
Central European Summer Time
Register for European Session
|-
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|-
| Time does not fit your Schedule or Time Zone?
We invite you to proceed with registration. Following the Webinar, all registrants are emailed a link to download the recorded Webinar Presentation to view at their convenience.
To register or view more Aldec Events, please visit:
http://www.aldec.com/events
|-

Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs.

With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.


Aldec market share is estimated at 38% of all mixed-language RTL Simulators sold to FPGA designers worldwide. (Excludes OEM simulators supplied directly from FPGA vendors). Aldec delivers high quality EDA solutions for government, military, aerospace, telecommunications, automotive and safety critical applications. Large companies including IBM, GE, Qualcomm, Rohde and Schwarz, Bosch, Texas Instruments, Applied Micro, Hewlett Packard, Toshiba, Intel, NEC, Mitsubishi, LG, Hitachi, NASA, Invensys, Westinghouse, Raytheon, Panasonic, Lockheed Martin, Samsung, as well as mid-size and small firms utilize Aldec EDA verification suites to boost product performance, cut design development cycles and reduce cost.

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Jasper User Group

Jasper User Group
by Paul McLellan on 09-25-2012 at 1:19 pm
Categories: EDA

The Jasper User Group meeting has been announced. It will take place on November 12th and 13th. As last year, it will be at the Cypress Hotel at 10050 De Anza Boulevard in Cupertino. The user group meeting is free for qualified Jasper customers.

Topics to be covered are, of course, all things verification:

  • SoC subsystems verification
  • Designer-based verification
  • Architecture validation
  • Low Power verification
  • Deadlock Detection
  • Coverage
  • Jasper technology roadmap
  • Glimpse of future technology

But the user group meeting wouldn’t be a user group meeting without users, and not just in the audience. Jasper is inviting users to submit case studies and user experience with Jasper’s products. Last year I thought these were some of the most interesting presentations. The deadline for abstracts is October 15th and then final presentations are due on November 5th. For more information about submitting a presentation, contact Rob van Blommestein at robvb@jasper-da.com.

More information on the user group meeting including a link for registration is here.

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CEVA DSP Technology Symposium Series 2012

CEVA DSP Technology Symposium Series 2012
by Daniel Nenni on 09-25-2012 at 4:45 am
Categories: Ceva, IP

You are cordially invited to register to attend the CEVA DSP Technology Symposium Series 2012, which will take place in Taiwan, October 16th, China, October 18th and Israel, November 1st.

CEVA’s industry-leading experts and engineers will present a full day of lectures and seminars where you will learn about the latest technological developments from the world’s leading licensor of silicon intellectual property DSP Cores and platform solutions for the mobile, portable and consumer electronics markets.

You will see first-hand how CEVA’s DSP technologies and platforms together with CEVA’s expansive partner ecosystem can enable your next-generation communications, audio, voice and imaging and vision product roadmaps.

CEVA and its partners will present and demonstrate licensable solutions for 4G communications such as eNodeB and DTV demodulation, in addition to software solutions for WiFi and GPS and a range of next-generation multimedia platforms enabling gesture control, computer vision, imaging, audio and voice.

Register and you can win a new Samsung Galaxy tablet

or new Google Nexus smartphone*, powered by CEVA
*requires participation in the event and winning the raffle

The format will consist of 2 concurrent lecture tracks targeting communications and multimedia applications, enabling you to attend the sessions most relevant to your area of interest. There will also be ample opportunity to interact directly with CEVA’s experts and partners in attendance at the events. Attendance is free of charge and includes lunch.

The day will conclude with a raffle for all attendees, where you could win a new Samsung Galaxy tablet or new Google Nexus smartphone*, powered by CEVA DSP technology.

With more than 2 billion CEVA-powered handsets shipped worldwide to date, CEVA is the world’s leading provider of DSP technology for the wireless market.

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Chip Aware System Design

Chip Aware System Design
by Paul McLellan on 09-24-2012 at 5:45 pm
Categories: Ansys, Inc., EDA

On Wednesday this week Ansys/Ansoft/Apache are presenting a new webinar Chip Aware System Design. It is presented by Dr Steven Gary Pytel Jr of the Ansoft part of Ansys, and Matt Elmore of the Apache subsidiary. The topics that will be covered include:

  • Power Delivery Network (PDN) design requirements
  • ABCD Matrix theory
  • SYZ Matrix theory
  • Chip-level Extraction
  • Effect of Chip inclusion on time and frequency domain system simulations

The webinar is in two parts, the first part fairly theoretical and mathematical (as you can see from the above list), that gives the foundation for analysis, especially frequency domain analysis. The second part takes that theory and uses it for practical analysis of power delivery networks.

The goal is that by the end of the webinar, attendees will be able to:

  • gave a basic understanding of impedance, transmission and scattering parameters
  • perform basic analyses on return and insertion loss
  • understand the impact of chip parasitics in both time and frequency domains
  • create and analyze “what if” test cases for real chip, package and PCB designs


The webinar is at 11am Pacific Time on Wednesday, 1pm on the east coast and corresponding times elsewhere. Pre-registration is here.

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SAME 2012 Conference on October 2-3 in Sophia is coming soon!

SAME 2012 Conference on October 2-3 in Sophia is coming soon!
by Eric Esteve on 09-24-2012 at 11:01 am
Categories: Arm, Cadence, Events, IP
1 Comment

This is the 15[SUP]th[/SUP] anniversary for the SAME Conference, dedicated to innovation on Microelectronics. Sophia-Antipolis is not only close to Mediterranean sea, but also at the heart of Telecom valley in south of France, with Texas Instruments design center dedicated to Application Processor design (OMAP), Cadence research center (managed by Jacques-Olivier Piednoir) developing Virtuoso Full custom layout edition tools (along with other team in India and the US), ST-Ericsson and many more. This area is a nice place to attract high level engineers, this explains why many companies, including ARM, Cambridge Silicon Radio (CSR), Intel, NVIDIA, Maxim, Mentor Graphics and Synopsys have a subsidiary here. To see the full company list, just go here. If you want to register, click on the SAME Logo:

I plan to attend the conference, especially the morning session about MIPI, a Tutorials given by Texas Instruments (M-PHY), Arteris (LLI Implementation challenges) and Cadence (New MIPI protocols), but, if you’re more interested about RF Modeling and RF Design, the session run in parallel. The conference agenda can be found here, just click on the agenda:

Also, you should not miss the Keynote talk from Mike Muller, ARM CTO, “A 2020 View & Perspective”:
Comparing the original ARM design of 1985 to those of today’s latest microprocessors, Mike will look at how far has design come and what EDA has contributed to enabling these advances in systems, hardware, operating systems, and applications and how business models have evolved over 25 years. He will then speculate on the needs for scaling designs into solutions for 2020 from tiny embedded sensors through to cloud based servers which together enable the internet of things. He will look at what are the major challenges that need to be addressed to design and manufacture these systems and proposes some solutions.
Mike Muller was one of the founders of ARM. Before joining the Company, he was responsible for hardware strategy and the development of portable products at Acorn Computers and was part of the original ARM design team. He was previously at Orbis Computers who developed network computers. At ARM he was VP, Marketing from 1992 to 1996 and EVP, Business Development until October 2000 when he was appointed Chief Technology Officer. In October 2001, he was appointed to the board of ARM Holdings plc.

If you plan to attend it will be a pleasure to meet you there!

By Eric Esteve from IPnest

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A Brief History of Helic

A Brief History of Helic
by Daniel Nenni on 09-24-2012 at 10:00 am
Categories: Uncategorized

As I have mentioned before, you can tell al lot about a company by their CEO. The previous trip I made to Taiwan was with Helic co-founder and CEO Dr. Yorgos Koutsoyannopoulos. One of the benefits of my job is I get to spend time with some very interesting people from around the world and this was no exception.

Prior to founding Helic, Yorgos worked as a research engineer of ICCS (an academic institute in Athens), in technology development projects for European corporations such as ST Microelectronics, Atmel-ES2 and Infineon. He received his Ph.D. and Diploma in Electrical Engineering from the National Technical University of Athens and he has attended executive courses on leadership and marketing at LBS and Harvard. Yorgos is a well-rounded guy and very personable, and a pleasure to work with.

Helic is an EDA specialist developing innovative and disruptive design automation technologies for the semiconductor market. Founded in May 2000, the company is backed by strategic and venture capital investors including the legendary Andy Bechtolsheim, Synopsys (formerly Magma), and Fujitsu. Helic reaches its customers with a business model combining EDA tools, IP and services, with a mission to enable first-pass silicon while greatly shortening the development cycles of high-speed digital, analog RF and millimeter-wave ICs.

Helic has more than 60 corporate customers and more than 1,500 users who design chips for a wide range of applications; from cellphone standards (1-2.1GHz), Bluetooth and WiFi (2.4-5.8GHz) to Gbit Ethernet, to multi-core CPUs and GPUs and to mm-wave applications. Helic is also the only emerging EDA company that I know of that has a full silicon correlation lab to perform on-chip measurements up to 70GHz.

Helic’s background technology is a unique high-speed parasitics extraction methodology. It was conceived to address a critical missing link in custom IC design flows and accelerate the development of complex RFICs and systems-in-package by enabling rapid, whole-chip electromagnetic modeling early in the design flow. The technology has been in use since 2000 by fabless companies and silicon IDMs worldwide.

Helic develops and provides EDA technology that enables rapid electromagnetic synthesis and modeling of on-chip passive devices, high-frequency interconnects, bondwires and package parasitics. At the core of Helic’s technology, an ultra-fast RLCK modeling engine offers signoff accuracy comparable to full-wave EM simulators, while outperforming the fastest reported EM engines by 100x or more in terms of speed and capacity. Helic has made significant advances in the development of efficient design flows that help designers overcome some known obstacles in the development of high-performance RF and high-frequency ICs.

Helic’s tool flows help fabless semiconductor and IDM customers achieve:

  • Minimization of silicon real estate employed by on-chip inductors and passives.
  • Centering of challenging high-speed circuits such as wideband amplifiers and oscillators.
  • Rapid simulation of signal integrity aspects such as inductance- and package-loaded transient response.
  • Concurrent low-noise/low-power RF circuit optimization, based on the synthesis of passive devices.
  • Model higher-order effects on power grids and clock networks due to magnetic coupling.

The company has 50 highly skilled professionals in its ranks today (30% hold a PhD, 35% a Master’s Degree, and another 30% a Bachelor); offices in San Francisco and San Jose, CA, Athens, Greece, and Yokohama, Japan and a sales network of partners in Korea, Taiwan, Israel, and China.

At this year’s Design Automation Conference in San Francisco, Helic and TSMC co-organized a workshop on “CMOS Design at 60 GHz and Beyond: Capabilities and Challenges”, with speakers from Silicon Image, TSMC, Helic, KU Leuven, Integrand Software, and Presto Engineering. A white paper on the workshop can be found HERE.