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May 29, 2013June 14, 2019

RTL Signoff Theater

RTL Signoff Theater
by Paul McLellan on 05-29-2013 at 11:00 am
Categories: EDA

We have talked for years about RTL signoff, the idea that a design could be finalized at the RTL level and then most of the signoff would take place there. Then the design would be passed to a physical implementation team who would not expect to run into any problems (such as routing congestion, missing the power budget or similar problems). Obviously this requires tools that run at the RTL level that have adequate predictive power to spot problems so they can be resolved prior to handoff. In particular, since so many designs are essentially assembly of pre-designed IP, they need to work on blocks of IP and pick up potential problems. Further, to be useful, tools for doing this need to run fast otherwise there is no big gain versus doing a trial layout with the full synthesis, place & route suite. The trick is to get almost as much accuracy as you would from doing the full design at a fraction of the cost in runtime and, indirectly, tool license costs.

Atrenta’s Spyglass, in its various flavors, does just this. It works at the RTL level to provide good accuracy and fast runtimes to ensure that the RTL is “good”.

During DAC, Atrenta is running a series of customer/partner presentations in their RTL Signoff Theater. SO stands for Signoff.

Every day at 5.30 there will be a drawing for an iPad mini.

Full details of Atrenta activities at DAC, including links for registration, are here. Atrenta is at booth 1847.

May 29, 2013June 14, 2019

Transistor, Gate and RTL Debug Update at DAC

Transistor, Gate and RTL Debug Update at DAC
by Daniel Payne on 05-29-2013 at 10:53 am
Categories: Concept Engineering, EDA

Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor, Gate and RTL designs, and one company called Concept Engineeringis appearing at DACagain this year in Austin to showcase many incremental improvements to their debugging tools. To get an overview of Concept Engineering visit the Wiki page.

I first started using SpiceVision PRO more than a decade ago to read in a SPICE netlist, and then traverse it graphically by creating on-the-fly schematics when no schematics were available to me. This graphical view allowed me to quickly understand my SPICE netlist and its simulation behavior.

At DAC next week you’ll get an update on several improvements:

1) Parasitic netlist debugging, new support of SPEF (Standard Parasitic Exchange Format) input format to StarVision PROand SpiceVision PRO tools.

Many extraction tools create the SPEF format, so now you can use that input format for post-layout created netlists.

In the schematic viewer tool above you can see in the top window a very readable auto-generated schematic of an IC netlist, then by just clicking the interconnect between cells you see the RC interconnect appear in the lower window. This is a great time saver from having to stare at a text netlist to understand how the interconnect was extracted.

2) Improved digital debugging in RTLvision PRO (RTL debug), GateVision PRO(Gate debug) and StarVision PRO (mixed-signal debug) by:

Improved waveform viewing
Improved automatic path extraction (points A to B)
Improved clock tree visualization and clock domain crossing visualization.

Clock Tree Extraction

3) Visualization engine improvements in EDA widgets (used by other EDA companies) called Nlviewand T-Engine.

Improved support for system-level visualization
New support for stacked or arrayed components
New logic cloud component that can include or hide logic elements and is represented by a cloud symbol

Nlview

T-engine

To see these improvements at DAC visit Concept Engineering in booth #1842, and ask for Gerhard Angst.

lang: en_US

May 28, 2013June 14, 2019

The never-ending quest to kill metastability

The never-ending quest to kill metastability
by Don Dingee on 05-28-2013 at 4:00 pm
Categories: Aldec, EDA

The difficulty of an engineering problem can be gauged by two things:
1) The number of attempts to generate a solution.
2) The degree of hyperbole used to describe the effectiveness of the latest solution.

The problem many folks in the EDA industry are after right now is clock domain crossings (CDCs) and the resulting metastability of designs. Continue reading “The never-ending quest to kill metastability”

May 28, 2013June 14, 2019

Jasper’s DAC Program

Jasper’s DAC Program
by Paul McLellan on 05-28-2013 at 3:52 pm
Categories: EDA

Jasper’s booth is 2346 where you can see demos of the JasperGold Apps and attend seminars on the experiences of ST and Broadcom, and others:

The Broadcom presentation on making formal an integral part of chip design is Tuesday at 10am.
The ST presentation on adapting formal methods in ARM subsystems is Monday at 1.30pm and again on Tuesday at 4pm.
Security path verification is presented by Gila Logic on Monday at 11.30am and Wednesday also at 11.30am.
Oski Technology will present on Sequential equivalence checking on Monday at 10am and Wednesday at 1.30pm.
Duolog will present on a Duolog/Jasper flow with ARM on Monday at 10am and 3pm, on Tuesday at 10am and 2.30pm and on Wednesday at 10am and 3pm.

Full details on all the above presentations are here.

Also around the show are various presentations either by or about Jasper’s formal technology:

Designer track presentation by ST: Adopting formal methods to increase productivity and quality in verification. Wednesday 12.30pm to 1.30pm in hall 5
Designer track presentation by Broadcom: Formal–an integral part of chip design. Wednesday 12.30pm to 1.30pm in hall 5.
Tutorial: A formal approach to low power verification. Wednesday 9-11am, room 18D.
Teens Talk Tech, moderated by Kathryn Kranen, Wednesday 2.30pm to 3.15pm at the DAC Pavilion, booth 509.
Visionary talk: Views about the future of our electronic design ecosystem presented by Kathryn. Thursday 11am to 11.15am in ballroom ABC.
DAC Monday night party at Austin City Limits. Jasper is giving T-shirts to the first 400 people. 8pm until 1am.

May 28, 2013June 14, 2019

Barbecue at DAC

Barbecue at DAC
by Paul McLellan on 05-28-2013 at 1:55 pm
Categories: EDA, Events

I already wrote about Franklin Barbecue, by some rankings the best in the whole country. If you want to go there you must be there early. They start serving at 11am and run out of food around 1pm. Closed on Monday.

But there are other barbecue and similar places near the convention center. Since I’m not an Austin native (we’ll be back in my comfort zone the next couple of years since I live in San Francisco) I gathered local knowledge.

IronWorks– walking distance around the corner from the convention center; a well-known great, local BBQ…an Austin icon…
Iron Works Located on 100 Red River St. The place is very rustic, but when you walk in, the smell will keep you there (happily) until you get your order. It really is not much to look at, but the baby back ribs are to die for. They are also known for their beef brisket and sausages, and I have heard that many people drive for miles to get their brisket, but I use to drive 6 hours for their ribs. Side orders are just OK, nothing to write home about, but you will leave there with a smile on your face, if you like smoked meat. Lest I forget, you will be hot in the summer (no AC) and cold in the winter unless you get to sit by the wood burning fireplace. Their sauce is a great ketchup based thick sauce. 5 min. walk

Stubbs– one of the fun historical places for BBQ and great music downtown…you may know Stubb’s famous BBQ sauce you can see in most grocery stores across the country.
Stubbs Located at 801 Red River St. This is a hard one to place among my top 5. The fact that it is Stubb’s BBQ, could be swaying my opinion, as it is one of the biggest tourist draws in Austin. It’s almost like The Bluebird restaurant in Nashville, you go for the music and the food is good too. However, this BBQ is REALLY good too! Their sauce is ketchup based sauce and is nationally famous. It is good but it is not the best of these others on my list. But there is just something about Stubb’s that keeps me going back. Maybe the fact that the first time I stopped there to eat, I found out just by happenstance that Willie was playing at their amphitheater that night, all I had to do was kill an extra 2 hours there, and I could see Willie Nelson. I don’t drink alcohol but it was still an easy task. First of all my wait for a table was almost an hour, so that killed one of those hours, then we just took our time eating and that was really easy. I have had their sampler and that comes with smoked brisket, sausage and chicken. The brisket was just good, nothing to write home about, but the sausage and chicken was real good. Since that time, I usually have the pulled pork and it is better than most, but I have had better. 20 min walk; 5 min cab ride

Lamberts– High-class BBQ with excellent food and drink. Also, music most nights…a bit expensive, but good!
Lamberts Downtown BBQ, located at 401 West 2nd St. “Carved out of a brick-walled general store that dates from 1873, it is raising the bar (and provoking outrage among purists) with its newfangled ‘fancy barbecue’ : think brown-sugar-and-coffee-rubbed brisket and maple-and-coriander-encrusted pork ribs.” 10 min. walk from hotel–Pricy but great food!

La Condesa– This place is special Mexican with great food and tequila drinks…one of the best in the country! 10-15 min walk, or 5 min cab ride. Pricing is a little high…but it has been voted “Best Restaurant in Austin 3 years in a row”!
Eclectic Mexican- La Condesa
Warning: One might fall in love with tequila at La Condesa restaurant—perhaps because it has Austin’s largest premium selection, with over 80 varieties of 100 percent blue agave tequila, or perhaps because the passion fruit and spiced mango Margarita really is that seductive. Second warning: One might also fall in love with the space, which is vibrant, modern, and trendy and has an enviable outdoor patio that feels quiet and secluded. Third warning: One can also fall head over heels with the perfectly paired dishes, such as the Hongos y Huitlacoche (tacos with mushrooms, truffle oil, huitlacoche, and Oaxacan cheese), the elotes (Mexican-style corn on the cob), and the ejotes (grilled Texas green beans with garlic and epazote). One preparation you will never encounter anywhere else is the costillas de puerco, pork ribs glazed with spicy guava and served with sweet plantains, pickled onions, fresh cheese, green salsa, and cilantro. It is that dish that will have you booking your next trip back to Austin. (400A W. Second St.; 512-499-0300;

Moonshine– Unique Austin style food, with excellent variety and good drinks! One of my favorites!
Moonshine Patio Bar & Grill 303 Red River St. Moonshine takes you back to a simpler time. Comfortable and familiar, relaxed and easygoing, Moonshine greets guests like family. Serving up great cooking with an innovative take on classic American comfort food, Moonshine’s menu satisfies even the big city tastes. For dinner, I ordered the half chicken with Dr. Pepper BBQ sauce with a side of Mac & Cheese. I think I was full about halfway through but I polished off every bite. It was absolute heaven… one of the best meals I’ve had in a long time. My husband had the chicken fried steak and I thought his jaw would never come off the floor when he saw it delivered. A humongous piece of tender, tasty steak covered in chicken batter and gravy.. across from Convention center…Excellent menu and food!

May 28, 2013July 18, 2025

Enabling 14nm FinFET Design

Enabling 14nm FinFET Design
by Daniel Payne on 05-28-2013 at 12:54 pm
Categories: EDA, Samsung Foundry, Synopsys

There’s never a dull moment in the foundry race to offer FinFET processes that enable leading-edge SoC design. Today I attended a webinar hosted by Samsung and Synopsys on how to enable 14nm FinFET design. The two speakers were Dr. Kuang-Kuo Lin from Samsung and Dr. Henry Sheng from Synopsys.

Dr. Kuang-Kuo Lin, Samsung

Dr. Henry Sheng, Synopsys
Continue reading “Enabling 14nm FinFET Design”

May 28, 2013June 14, 2019

Calypto AMD Renesas and #50DAC

Calypto AMD Renesas and #50DAC
by Daniel Nenni on 05-28-2013 at 10:00 am
Categories: EDA

This year for DAC, Calypto has assembled an impressive lineup of customer presentation, suite sessions and Designer Tracks. To start with customer presentation, Steve Kommrusch, Fellow Design Engineer from AMD will be giving a talk in the Calypto Suite on AMD’s methodology for low power and will show how AMD was able to get further 20% power reduction on a SoC that was already optimized for low power. AMD’s methodology for low power is centered on the notion of efficient clock gating. In this private suite presentation, Steve Kommrusch from AMD will discuss AMD’s methodology for reducing power on the Jaguar SoC and will show how AMD used PowerPro to improve clock-gating efficiency. Steve will also share the results and advantages of doing power analysis and optimization at the RTL stage rather than waiting until post-gate synthesis.

Another customer presentation in the suite is from Renesas. In this private presentation Shintaro Imamura-san of Renesas, will describe how they were able to cut down verification time by using C to C and HLS formal equivalency flow using Calypto’s SLEC product. This presentation will be given in English and Japanese at two different times.

As some of you may know, Calypto has been running a webinar series that has been very successful. What I like about Calypto’s webinar series is that it is truly a technical tutorial and without any marketing or product pitch. Calypto has scheduled two of its most popular webinars in the suite session.

The first one is How to Use Deep Sequential Analysis to Minimize Power. In this 50 minute tutorial, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL. They will cover basic, yet important concepts; such as how to best set up your environment to accurately measure power. The tutorial will cover more advanced topics—such as how to analyze the RTL for wasted power—and show optimization techniques to reduce power on real designs. The latest sequential analysis techniques will be described; including stability-based and observability-based sequential clock gating for maximum power optimization.

The other one is A Practical Comparison between C++ and SystemC for High Level Synthesis. This 50 minute tutorial will provide a practical overview of the differences between the two most common ESL hardware description languages. The tutorial will show side-by-side coding examples for basic hardware concepts; such as, hierarchy, IO, numerical precision, and timing. As the only company to support both SystemC and C++ for synthesis with the industry’s most successful HLS tool (Catapult), Calypto is uniquely placed to discuss the differences between the two languages.

In addition to these special suite session, there are number of suite sessions on Calypto’s three product lines: Catapult, which is a high level synthesis tool that takes C++ or SystemC and synthesizes it into Verilog or VHDL RTL. PowerPro is industry’s only RTL power analysis and optimization tool that incorporates Calypto’s patented deep sequential analysis technology for best power optimization. SLEC is industry’s only production proven sequential equivalence checker.

Calyptp will also be showing Catapult LP. Catapult LP embeds Calypto’s unique PowerPro® technology “under the hood” to seamlessly produce the lowest power RTL by optimizing designs at the architectural and register transfer levels, where 80% of power decisions are made. Catapult LP enables designers to explore different hardware architectures and measure the power, performance, and area (PPA) of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed loop PPA optimization during high-level synthesis. Catapult LP goes beyond the architecture level by leveraging Calypto’s patented sequential analysis technology to deliver automatic fine-grain clock gating. In this session we will show how to design for the lowest power hardware by first optimizing the architecture and then maximizing clock gating efficiency.

In addition to these suite sessions which are listed on the Calypto website and users can sign up for them, there are some private sessions which are not listed and is by invitation only. These sessions are about new products and future roadmap. To find out more about these sessions contact your Calypto account manager.

There are also two Designer Tracks that talk about Calypto’s PowerPro product. In the first one on Tuesday, Udupi Harisharan, of Cisco Systems will discuss Practical Consideration in a Sequential Power Optimization Flow. In the Wednesday Designer Track session, Steve Kommrusch of AMD will discuss how AMD’s Power Regression Methodology Reduces Dynamic Power by 20%.

There is also an Insight presentation where Calypto’s Bryan Bowyer will talk about Reducing Design and Debug Time with Synthesizable TLM

To get more details and sign up for these presentations, visit http://calypto.com/en/events

lang: en_US

May 26, 2013June 14, 2019

AMS Design, Layout and Verification @ #50DAC

AMS Design, Layout and Verification @ #50DAC
by Daniel Nenni on 05-26-2013 at 9:00 pm
Categories: EDA, Tanner EDA

Competition in EDA is absolutely necessary in order for the fabless semiconductor ecosystem to thrive. AMS tools with a low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership. That is why Tanner EDA has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries. I work closely with Tanner EDA as a liaison between the foundries and the top fabless semiconductor companies so this interview was more like a conversation between friends:

Q: What are the specific design challenges your customers are facing?

Before we discuss design challenges, it may be helpful to share bit about our diverse customer base. We’re coming into our 25[SUP]th[/SUP] year in EDA and we’re seeing some consistent themes across a majority of our customers:

Core application domains include power management, imagers, life sciences, automotive systems, displays, consumer electronics, sensors and MEMS,
Users of our layout tool (L-Edit) are actively working at process nodes down to 20nm,
Users of our entire A/MS tool flow are typically designing at 90nm and above, and
Common foundry partners include specialty fabs like TowerJazz, XFab, and Dongbu as well as high volume fabs such as TSMC and Globalfoundries.

As far as design challenges go, we partition them based on workflow. We have customers using our entire tool suite and we have customers who choose to integrate selected Tanner EDA tools with other point tools. We find that the challenges are very closely related to the part of the design flow a customer is working. For example, we very often hear from our front-end tool users (schematic capture, simulation, waveform analysis) that growing design complexity is driving increased need for advanced analysis methods. Through our partnership with BDA, we offer FastSPICE and Transient Noise Analysis solutions in addition to our Tanner Spice (T-Spice) offering.

As far as back-end goes, analog layout productivity is a consistent design challenge we are working on with customers. Shortened time-to-market lead times are putting a strain on the inherent artistic (often time-consuming) nature of analog layout. Executives, CAD managers and layout engineers are struggling to balance the artistic nature of analog and the productivity requirements of the market. L-Edit – our hallmark layout editor – continues to add capabilities that tackle this design challenge head-on. This includes our analog acceleration product called HiPer DevGen – a high performance device generation tool.

The other component around layout productivity is design reuse. In the past, we had customers express frustration over the fact that designs they created on other tool flows were not easy to port to our tools. We worked hard to develop and launch our latest version – v16 – that features OpenAccess. Now users are able to open and save designs and elements within designs across different tool environments.

Another set of Tanner EDA users are focused on MEMS design. Tanner has a long history in the MEMS space, and we even have a separate business division that operates a MEMS fab for prototyping and low-volume production runs. The design challenges commonly expressed by our MEMS users are centered around the co-design of MEMS and IC devices. We’ve recently produced several webinars and a live seminar to offer best practices and design guidance to help with this manifold issue.

Q: What does Tanner EDA do?

Tanner EDA provides a complete flow for the design, layout and verification of analog and mixed-signal integrated circuits. Our tools offer just the right mix of capability and performance to provide designers a highly productive design environment. Interoperability within the EDA ecosystem has recently been bolstered with our release of L-Edit with OpenAccess.

Q: Why did you join Tanner EDA?

I was introduced to John Tanner in 2008 through our mutual participation in a Southern California business leaders organization. As I learned about Tanner EDA and their unique position in the market, I began to think about ways I could bring my own experiences and expertise to the company. Having worked in the software and services industries for much of my career, I was intimately familiar with both the challenges and opportunities Tanner EDA had given their position in the market. Since I had worked with several founders to grow their businesses and transform their business models, I also had insights into leading a division within a privately-held, founder-owned business.

When I joined, Tanner EDA was in many ways a start-up, yet the division had been in business since 1988. When I say “start-up,” I mean they were operating as a very nimble and problem-focused company. They had (and still retain) a very tight focus on the analog and mixed-signal designer. While there was great market awareness of Tanner EDA tools, it was mostly associated with the layout editor, (L-Edit), and many users had interacted with the tool five or even ten years back. There was not as much awareness around our proven commercial success. For example, Tanner EDA had been used by CSR to tape out their seminal Bluetooth chip designs, yet many people still thought of us as being a tool for universities.

Along with our investments in internal product development and other technology partnerships – with foundries and other EDA companies like BDA, Aldec, and Incentia – we’ve worked hard to improve awareness and knowledge of how robust and capable Tanner EDA tools are. I’ve enjoyed being able to draw on my skills to help engage new partners within our ecosystem and elevate the brand awareness for our company.

Q: How does Tanner EDA help with your customers’ custom IC design challenges?

Tanner EDA offers analog, mixed-signal and MEMS designers a cohesive and highly capable tool flow that provides the industry’s leading price-performance and customer support. A growing number of designers have cited issues with “Big 3” tools being bloated with features that are specific to requirements for the deep nanoscale process nodes. While our layout tool supports designers working at these nodes, our mainstay user is typically working at 90nm and above. Those users consistently cite our tools as being “just right” to help solve their design challenges efficiently and effectively, with no extraneous features getting in the way.

Operating platform is another area our users give us high marks for. Our tools run on both Windows and Linux. The ubiquitous nature of Windows-based computers and workstations aligns well with one of the principles on which John Tanner founded our company. He was intent on providing robust design tools with compelling price-performance. This shaped our direction early-on in terms of supporting Microsoft and it’s something a majority of our users continue to cite as a benefit. They like the flexibility and efficiency to upgrade PCs and maintain their Tanner EDA suites, often without a staff of dedicated CAD engineers.

Another important aspect of helping customers is technical support. We consistently hear from our users that Tanner EDA provides a level of customer support that is unrivaled in the industry. We understand that our tools are directly tied to our customers’ success in the marketplace, so we make sure that our support teams have the resources they require to ensure that success.

Q: What are the tool flows your customers are using?

Customers who use our complete design suite are running HiPer Silicon AMS. That is our full mixed-signal solution that covers schematic capture through to tape-out.

Some customers integrate a sub-set of our design suite to build out their own solution. Our longstanding commitment to interoperability and adherence to industry standards enables users to utilize Tanner EDA tools within a hybrid flow.

We have customers using our front-end tools – incorporating our schematic capture, simulation (T-Spice and/or FastSPICE) and waveform viewer with back end tools from other vendors.

Our back-end tools can also serve as the foundation of a hybrid tool flow. Users integrate their simulator of choice with Tanner EDA’s layout editor (L-Edit) and (optionally) our physical verification products. Back-end tool integration has been greatly enhanced by our recent release of L-Edit v16 featuring OpenAccess.

Our physical verification tools are in use across a wide range of commercial applications. We have a base of users who rely exclusively on Tanner EDA for their verification needs. We also have a set of customers who use our HiPer Verify product in conjunction with other verification engines, offering a comprehensive verification solution that offers compelling price-performance.

Q: Will you be at the Design Automation Conference this year?

YES! Tanner EDA has been a long-standing exhibitor at DAC, and this year is no exception. We’ll have our own booth — #2442 – where we will be offering demonstrations of our tool suite. We will also be exhibiting in the ARM Connected Community® Pavilion. We’re again one of the sponsors of the IPL Alliance event on Tuesday night and we have a Designer Track Session on Wednesday.

Pre-registration for a demo is not required, but is strongly recommended. This link goes to our DAC2013 registration page.

Q: Where can SemiWiki readers get more information?

An overview of our tool suite can be seen here
Videos of our tools in action along with webinar replays can be found here (registration required)
We have customer case studies posted here on our website
MEMS designers can visit our dedicated MEMS page
Our whitepaper on Analog Layout Acceleration can be downloaded here
You can contact Tanner EDA directly by calling 1-626-471-9701 or emailing salesw@tannereda.com

lang: en_US

May 26, 2013January 27, 2022

IROC Technologies CEO on Semiconductor Reliability

IROC Technologies CEO on Semiconductor Reliability
by Daniel Nenni on 05-26-2013 at 8:10 pm
Categories: CEO Interviews, EDA, IROC Technologies

One of the best things about being part of SemiWiki is the exposure to new technologies and the people behind them. SemiWiki now works with more than 35 companies and I get to spend time with each and every one of them. Much like I do, IROC Technologies works closely with the foundries and the top semiconductor companies so it was a pleasure to do this CEO interview:

Q: What are the specific design challenges your customers are facing?

A: The design flow is an always evolving, ever-demanding beast. The continuing evolution of the technology allows building increasingly complex electronic devices integrating more and more functions. This evolution is not free of problems, or more appropriate, challenges to overcome. Reliability is a natural concern. Particularly, perturbations induced by radiation – Single Event Effects (SEEs) may cause system downtime, data corruption and maintenance incidents. Thus, the SEEs are a threat to the overall system reliability performance causing engineers to be increasingly concerned about the analysis and the mitigation of radiation-induced failures, even for commercial systems performing in a natural working environment. Our observation is that from the classical Power, Area and Timing-driven design flows, going through the Design for Manufacturability, Yield and Test (DFM/DFY/DFT) design and manufacturing frameworks, our customers are increasingly aware and adepts of the Design for Reliability (DFR) paradigm.

Q: What does your company do?

A: We provide services, tools and expertise to qualify and improve the reliability of electronic designs and systems with a focus on radiation induced effects, process variation and ageing. We help engineers to evaluate the susceptibility of their designs to different perturbations. We assist them in improving the primary reliability characteristics (uptime, event/fault/error/failure rate …) that are relevant for their specific application. We accompany the reliability engineers in their exchanges with the suppliers in order to select best performing materials and processes. We also help them to prove the fitness of the delivered solution for the reliability expectations of the current application. Ultimately, we assist all the actors from the design and manufacturing flow to select and improve the best reliability-aware processes, designs approaches and frameworks with the overall goal of providing high reliability solutions to demanding end users. Moreover, our continuous 10+ years’ service as an independent trusted advisors and test experts has been positively recognized by technology & solution providers and end-users alike.

Q: Why did you start/join your company?

A: I’ve joined the company in September 2000 as one of the earliest employees. From my initial R&D Engineer position, through the role of VP Engineering and moving up to the CEO position in February 2013, I’ve accompanied the company through a long history of challenges and opportunities. My current focus is on preparing the organization for growth, technical excellence and leadership and aligning our solutions, services and tools to the needs of our partners and customers.

On the academic side, I hold a Ph.D in Microelectronics from INPG, Grenoble Institute of Technology, France and I’m fairly active in the R&D community, both industry and academy. I’m currently helping as a program chair, the organization of the International Online Test Symposium (IOLTS) in Crete, Greece, event focusing on the reliability evaluation and improvement of very deep submicron and nanometer technologies.

Q: How does your company help with your customers’ design challenges?

A: Our solutions, tools and testing services have been designed to evaluate and improve the Soft Error Rate of sophisticated systems – from the technological process and standard cell library up to the complexity of a failure mechanism in complex systems. Our tools can present an itemized contribution of the SER of every design feature (individual cell, memory block, IPs, hierarchical blocks) and our expertise can address the reliability concerns of cell, chip or system designer by improving the underlying technology reliability and adding error management IPs and solutions to the chip and system.

Q: What are the tool flows your customers are using?

A: Our TFIT (transistor/cell SER evaluation) and SoCFIT (platform for SER evaluation and improvement of complex systems) tools have been designed for a seamless integration in existing design flows and methodologies. The TFIT tool is usually used by the designers of standard cells, in conjunction with a SPICE simulator (HSPICE, Spectre). SoCFIT integrates a collection of modules and tools that aim at providing SER-aware evaluation and improvement capabilities in standard design flows (i.e. Architecture>RTL/HLS>GLN), possibly connecting to commercial simulation tools (NCSim, VCS, ModelSim, QuestaSim) or synthesis, verification and prototyping platforms (Synopsys DC, PrimeTime, First Encounter)

Q: What will you be focusing on at the Design Automation Conference this year?

A: We want to meet our customers, and our prospective customers. Austin is a large design center, and chances are we will be meeting many designers and engineers who don’t usually travel to Silicon Valley or other places for conferences.

Q: Where can SemiWiki readers get more information?

www.iroctech.com

http://www.semiwiki.com/forum/content/section/2094-iroc-technologies.html

Vision: We believe that every modern chips should have the highest level of reliability throughout the product life time. IROC Technologies helps the semi-conductor industry significantly lower the risks of soft errors by providing software and expert services to prevent soft errors when designing IC’s.

With the introduction of submicron technologies in the semiconductor industry, chips are becoming more vulnerable to radiation induced upsets. IROC Technologies provides chip designers with soft error analysis software, services and expert advisors to improve a chip’s reliability and quality.

Exposure of silicon to radiation will happen throughout the lifetime of any IC or device. This vulnerability will grow as development moves to smaller and smaller geometries. IROC proved that the soft errors that cause expensive recalls, time-to-volume slow-down, and product problems in the field can be significantly reduced. The mission of the company’s soft error prevention software and expert advisors is to allow users to increase reliability and quality while significantly lowering the risk of radiation-induced upsets, throughout the lifetime of products under development.

Also Read:

CEO Interview: Jens Andersen of Invarian

CEO Interview: Jason Xing of ICScape Inc.

Atrenta CEO on RTL Signoff

May 26, 2013June 14, 2019

The History of Arasan Chip Systems

The History of Arasan Chip Systems
by Sam Beal on 05-26-2013 at 8:05 pm
Categories: Arasan, IP

In 2002 few people outside of Steve Jobs, could have predicted the iPhone. But a forward-looking technology CEO could expect Moore’s Law to extend into portable devices as it did with PCs. While 2G and 2.5G cellular phones were shipping in the hundreds of millions, the features were rather primitive. 3G, 4G, WiFi, Bluetooth, etc. were not available. The mega-pixel cameras, displays, and HD video capability of a modern smartphone were stuff of dreams.

That same year Arasan and his core team began its journey to deliver silicon intellectual property (IP) for portable electronics. The focus was not just on delivering IP Cores, but customer relationships and awareness of trends and evolving standards for portable electronics.

Arasan acquired the specifications from the SD Card Association (an apex body constituting Panasonic, SanDisk, and Matsushita) and entered the SD card market. SDIO, based on the SD standard, enabled add-on cards. While early adoption of the SD card and SDIO interface was limited to PDA and gaming systems, ACS established SDIO as a viable IP product for mobile devices. The first major break came when WiFi ICs using SDIO became a de-facto standard in mobile applications. SDIO has since evolved to support additional wireless standards like GPS, Bluetooth, WiMax, 3G, etc.

ACS actively participates and contributes to a number of major standards groups. In 2005, ACS pioneered the universal card host controller combing SD, SDIO and MMC. After joining JEDEC in 2008 eMMC support was added to the controller. Today the“3MCR” is the leading host memory card controller in mobile computing.

ACS was one of the first companies to join the MIPI Alliance and to contribute to the initial introductions of standards like DSI, CSI, Unipro, and SLIMBus. The high-speed serial interface required by many MIPI standards, led Arasan to invest in analog design – resources and mixed signal methodology for MIPI D-PHY and M-PHY. Today the largest microprocessor manufacturer and the leading suppliers of chipsets to cell phone companies are licensees of ACS’s MIPI based products.
First to design, first to market with a “Total IP Solution” has been Arasan’s goal from the formative years, and a key reason for making ACS the leader in mobile connectivity and mobile storage. The company prides itself on deep domain and system expertise. As a result ACS provides IP Cores with verification IP, software drivers and stacks, and validation platforms to enable customer success. Arasan Chip Systems established a reputation of the highest quality, unprecedented support, and a unique personal touch.

Mobile computing technology is constantly evolving to meet insatiable market demands for more features like higher resolution displays, multiple cameras, new WiFi standards, etc. To support these features, high-speed serial (SERDES) interfaces will drive growth in silicon IP (for example SSIC and Mobile PCIe, which will use the MIPI M-PHY). ACS customer engagements help tremendously to gauge these emerging trends, and to select future product offerings.