SemiWiki – Page 905 – The Open Forum for Semiconductor Professionals

February 3, 2013June 14, 2019

Common Platform Technology Forum February 5th 2013 Live or Online!

Common Platform Technology Forum February 5th 2013 Live or Online!
by Daniel Nenni on 02-03-2013 at 8:00 am
Categories: Events, Foundries

Can’t make it to Santa Clara? Join us online!

The detailed 2013 CPTF agenda is now up in preparation for the February 5th event at the Santa Clara Convention Center. This is one of the rare times that you can get a free lunch! Watch this quick video to see what is in store for us this year. Dr. Paul McLellan and I will be there so please introduce yourself, it would be a pleasure to meet people who follow us on SemiWiki. Space is limited so register today HEREor click on the banner below. Did I mention it is FREE? This is an excellent opportunity to mingle inside the fabless semiconductor ecosystem.

Agenda

Bruce Kleinman, Vice President, Product Marketing, GLOBALFOUNDRIES
Mike Cadigan, General Manager, IBM Microelectronics, Systems and Technology Group

Handel Jones, Owner and CEO, International Business Strategies, Inc.
Brian Fuller, Journalist, EE Times

Dr. Shawn Han, Vice President, Foundry Marketing, Samsung
Dr. Antun Domic, Senior Vice President and General Manager, Implementation Group, Synopsys

Subramani Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES
Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics

Dr. Mukesh Khare, Director, Semiconductor Technology Research, IBM Research
Dr. Supratik Guha, Director of Physical Sciences Department, IBM Research
Dr. Vassilios Gerousis, Distinguished Engineer & Technologist, Cadence

February 1, 2013June 14, 2019

Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs

Design IP including Multi-standard SerDes enables risk-free, faster customer ASIC designs
by Eric Esteve on 02-01-2013 at 8:25 am
Categories: Uncategorized

ASIC design service companies are an essential piece of the SC ecosystem, as well as Silicon Foundries, EDA and IP vendors. Their customers range from pure fabless with no ASIC design resources, who need a third party to turn a concept into a real product (IC) and then market and sale it, to large IDM temporarily lacking design resource to support a project. For a small fabless, building an efficient ASIC design team require a strong investment, covering H/W, up-to-date and expansive EDA licenses and also key peoples, able to successfully manage a project as well as a design team. All of the above represents a lot of energy that the management would have to spend, when the most important part of their job is the market understanding leading to the definition of the ideal system or of the “killer application” which will make their company successful. Using a third party can also be the best way to avoid traps linked to advanced ASIC technology and secure the go-to-market strategy.

Selecting an ASIC design service tightly coupled with a Silicon Foundry, like GlobalUniChip (GUC) is with TSMC is another step to a successful product release, especially during the ramp-up to production. In fact, even if your prototype is first time right, if you are not able to quickly ship the IC to your customers to support their production needs, best case you will delay the revenue flow… worst case a competitor will win the race just on the line! If you’re a Qualcomm or an Apple, you probably build a joint team with TSMC, when the size of the company is more modest, it can be useful to benefit from a well-trained team of Product Engineers, able to manage the Test, Packaging and knowing the target process. Such a service should be offered by an ASIC design service.

This (rather long) introduction help understanding what should be the positioning of ASIC Design Service, in general, and what is effectively the way GUC is running. Designing an ASIC today is often synonym to developing a large SoC. Thus, integrating pre-existing and Silicon proven IP is an absolute requirement. Pre-existing IP to speed-up the design integration, and silicon proven to minimize the risk. The design service company could decide to externally source complexes functions like Interface IP (USB3.0/2.0/1.0, HDMI V1.4 TX and RX for example) or DDR2/3 Memory Controller and PHY, to name a very few, but integrating internally developed IP will be much faster: it will ease the vendor/customer relationship, avoiding to insert another third party, and even more important, the design team will quicker integrate an already known function. Both will positively impact the design cycle, and finally improve the Time-to-Market (TTM).

GUC’s IPs are silicon and production proven in the ASIC projects of a global customer base, and provides designers with a broad range of synthesizable implementation IP, hardened PHYs and verification IP for ASIC, FPGA, and SoC designs. The GUC in-house IP portfolio includes bus interface, mixed signal, data converter, multimedia, power management, and SERDES.

Bus Interface IP includes digital and mixed-signal standards-based connectivity IP such as 1G and 10G SerDes (supporting GPON/EPON applications as well as XFI and 10G BASE-KR back plane applications), PCI-e 3.0/2.0, SATA 3.0/2.0/1.0, SAS 2/1, USB3.0/2.0/1.0, HDMI V1.4 TX and RX, Interlaken/Double XAUI, XAUI, SGMII, SRIO, Fiber Channel, AHB/AXI, and Ethernet.
Data Converter IP includes SAR and pipelined ADCs and wide bandwidth, precision and high speed DACs.
Mixed-Signal IP includes LVDS, power management, DC-DC converters, clock generator IP, 3.3V/2.5V high voltage tolerant/drive I/O, etc.
Memory Element IP includes many offerings from TSMC including single- and dual-port memory compilers and memory types are also available.
Peripheral Core IP includes DDR2/3 Controller and PHY IP up to 1600Mbps silicon-proven IP (next generation targeting 2133Mbps) with both wire bond and flip chip solutions.
Processor IP includes MCU/MPU and hardened ARM processor cores including an ARM development platform for quick prototyping.

Bus Interface IP includes digital and mixed-signal standards-based connectivity IP such as 1G and 10G SerDes (supporting GPON/EPON applications as well as XFI and 10G BASE-KR back plane applications), PCI-e 3.0/2.0, SATA 3.0/2.0/1.0, SAS 2/1, USB3.0/2.0/1.0, HDMI V1.4 TX and RX, Interlaken/Double XAUI, XAUI, SGMII, SRIO, Fiber Channel, AHB/AXI, and Ethernet.
Data Converter IP includes SAR and pipelined ADCs and wide bandwidth, precision and high speed DACs.
Mixed-Signal IP includes LVDS, power management, DC-DC converters, clock generator IP, 3.3V/2.5V high voltage tolerant/drive I/O, etc.
Memory Element IP includes many offerings from TSMC including single- and dual-port memory compilers and memory types are also available.
Peripheral Core IP includes DDR2/3 Controller and PHY IP up to 1600Mbps silicon-proven IP (next generation targeting 2133Mbps) with both wire bond and flip chip solutions.
Processor IP includes MCU/MPU and hardened ARM processor cores including an ARM development platform for quick prototyping.

Last point: the Multi-standard SerDes (pictured above) has been successfully deployed in 20+ customer projects and the IP solution integrates MAC/PCS/PMA, another guarantee of faster TTM.

To learn more about IP port-folio from GUC, just go here.

By Eric Esteve from IPNEST

January 31, 2013June 14, 2019

Startups: the Biggest Challenge

Startups: the Biggest Challenge
by Paul McLellan on 01-31-2013 at 9:00 pm
Categories: General

What is the biggest challenge facing an EDA startup today? By a startup, I mean a brand new company, not a company that already has a few customers and is either on a fast path to success or a slower path whereby the company can continue to grow slowly forever.

Obviously, one challenge is the funding environment. Since EDA acquisitions have typically been at low valuations, this has put investors off starting EDA companies. Of course there have been exceptions: Apache and Denali were acquired for healthy valuations but it took a long time to get there in both cases. But with computers so cheap, cloud computing providing almost infinite resource when you need it, and modern programming tools, the amount of money required to get “ramen profitable” is a lot less than it used to be. Another challenge for EDA funding is that it doesn’t need enough money to interest VCs, who have large funds and want to invest the fund in a manageable number (board meetings etc) of large investments.

But I think money is easier to get hold of than something else critical: test-cases.

To be successful as a startup, you have to intercept the future, create technology that isn’t essential today (or someone would already have created it) but will be when you are ready, maybe at 14nm or 10nm. If you are targeting 20nm or above it’s already too late. There are only a handful of groups doing anything at all at 14nm, so how do you get them to work with you?

Answer: you can’t, at least initially. So you have to create your own test-cases to get the product developed. The trouble is that it isn’t clear what the characteristics of a good test-case are. Say someone gives you a 45nm design (even that might be a big ‘if’). How do you need to change it to be a good archetype for a 10nm design. Must be larger for sure. All those sub-20nm stuff like double patterning and layout-dependent-effects. Plus some stuff that probably nobody knows yet.

This was brought home to me during the time I was CEO of Envis. We had some power reduction technology that worked really well on the test-cases we had, reducing power (and occasionally area) by 30% or so. But those designs were old designs that had been designed during an era when power wasn’t an issue so there was lots of low-hanging fruit to be harvested. When we engaged with real customers on real designs, the power savings dropped to more like 7-8%. Not nothing, but not compelling enough for anyone to upend their design methodology.

Another challenge in EDA today is that I think many of the problems are becoming too big for a startup to handle. TSVs require changes to the entire tool flow of the big guys, not just adding a new point tool into the mix. Double patterning, ditto. FinFETs, not a point tool. I’m sure there are niches but that is a problem. Niches are small. To be successful as an EDA startup you need to have something that everyone is going to require eventually, and preferably need lots of licenses. The big guys will eventually have one but maybe you can be first. And best. And if you are, one of the big guys will probably get theirs by buying you.

But you have to get to the point of having something compelling enough to get leading edge groups to engage with you before you get your hands on a real leading edge test-case. Chickens and eggs come to mind.

January 31, 2013June 14, 2019

Seeing inside SoC designs, from the beginning

Seeing inside SoC designs, from the beginning
by Don Dingee on 01-31-2013 at 8:10 pm
Categories: EDA

Engineers have this fascination with how things work. They are thrilled to tear stuff apart, and sometimes to even be able to put it back together afterwords. So I can keep my recovering engineer card, I thought I’d take a few moments and look inside a technology Daniel Payne and I have been covering here, exploring where the idea started and how the approach is different.

Continue reading “Seeing inside SoC designs, from the beginning”

January 31, 2013June 14, 2019

Dynamic/Leakage Power Reduction in Memories

Dynamic/Leakage Power Reduction in Memories
by Daniel Nenni on 01-31-2013 at 8:05 pm
Categories: EDA

Embedded memories have an important impact on power. SoCs that integrate multiple functions on a single silicon die are at the heart of many electronic devices. As process geometries have scaled, design teams have used more and more of the additional silicon real estate available to integrate embedded memories that serve as scratch-pads, FIFOs, and caches to store data for the computational cores. As a result, most current designs have over 50 percent of their area used by embedded memories and these memories account for 50‑70 percent of total SoC power dissipation. Clearly, any attempt to reduce SoC power is incomplete if it does not attempt to reduce the power consumed by the embedded memories in a design.

Given the complexity of today’s SoCs, efficient power management requires a holistic approach where the control logic, data paths, and memories are analyzed together and optimized for both dynamic and static power. However, identifying sequential clock and memory gating opportunities is beyond the scope of RTL synthesis tools. Power conscious designers try to analyze the registers for redundant accesses and look for conditions under which such accesses can be shut off. There is no single known method of achieving this, and designers mostly develop this expertise over time. Even so, the process can get very tedious and error prone without suitable assistance.

In an earlier webinar Calypto presented the concept of deep sequential analysis (DSA) and how it can be used to reduce power at RTL. Sequential analysis involves temporal analysis of the complete design — including gates, flops, and memories — over several clock cycles and the examination of the stability, propagation, and observability of signal values. This is important for power optimization in identifying unused computations, data dependent functions, and don’t-care cycles in the original code.

Sequential analysis is equally applicable to embedded memories. Memories are used to store the results of intermediate computations in the data pipelines; serve as buffers between interacting computations; or serve as caches to store frequently read data. Even though locally the reads and writes to a memory may appear to be necessary, depending on the functional mode or complex control sequence of the design, they may not be needed. Removing such redundant memory accesses can result in significant reduction in the dynamic power consumption of memories.

Memory vendors provide several capabilities to reduce leakage power in memories that are not in use, and various flavors of sleep modes are now available in embedded memories, but using these modes requires the creation of controllers to generate the sleep and wake signals. In addition, the leakage power savings gained during sleep mode must be greater than the dynamic power dissipation associated with transitioning the memory in and out of sleep mode. The memory must be in sleep mode for a minimum number of cycles to actually save power. Finally, creating the sleep mode control signals and ensuring that sleep modes are triggered only during periods when the memory is quiet for an extended period require analysis of the design functionality over multiple cycles. DSA is very effective in analyzing and identifying optimum sleep modes for embedded memories.

In their next webinar Calypto will show how its patented deep sequential analysis (DSA) technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory.

Dynamic/Leakage Power Reduction in Memories
A Webinar on Slashing your Dynamic/Leakage Memory Power in your Verilog/SystemVerilog/VHDL RTL
February 12

January 31, 2013June 14, 2019

TSMC ♥ Oasys

TSMC ♥ Oasys
by Paul McLellan on 01-31-2013 at 8:05 pm
Categories: EDA

Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling with new QoR and time to market issues.

RealTime Explorer enables RTL engineers to have a physically aware, implementation accurate synthesis tool for top-level PPA and routing analysis without requiring them to be physical design experts. Without an accurate tool like RealTime Explorer, RTL designers either ignore physical design issues and their impact on timing and physical issues such as congestion. Or else they have to go through a complete iteration of physical design which can take days, even assuming that tools and physical design engineers are available to perform the work.

One feature that makes a big productivity difference is the logical-to-physical cross-probing capability that makes it easy to get at the root cause of timing and routing issues before even handing the design off for physical design. It is simple to go straight from the violation in the physical domain and connect straight back to the line(s) of RTL that originate the problem.

January 31, 2013August 22, 2024

Advanced Technology-Design-Manufacturing Co-optimization

Advanced Technology-Design-Manufacturing Co-optimization
by Daniel Nenni on 01-31-2013 at 7:00 pm
Categories: Foundries, GlobalFoundries

I spent some quality time with Subi Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES in Las Vegas during CES. Great guy, he worked at Silicon Access, Virage and TSMC before GF. One thing you should know about embedded memory guys, SRAM is the first thing that goes through a new process so they know their process technologies.

At Silicon Access Networks, Subi Directed a WW Engineering team to a first pass silicon sucess on industry’s first 10G classification processor SoC. At Virage, with responsibilities of WW design centers and advanced memory R&D, Subi took the Company to a leadership position on 90nm, 65nm and 40nm nodes. At TSMC, Subi was the Sr. Director in Design and Technology Platform and the Head of their North America Design Center. With a large engineering team in the US and Taiwan, Subi was responsible for technology enablement of advanced nodes and interfaced with strategic customers and partners.
Subi also has 30+ patents.

At GF, Subi is responsible for determining the technology feasibility, competitiveness and manufacturability of all elements of technology platform and to establish the advanced technology (14nm) roadmap. Subi is also one of the presenters at the Common Platform Technology Forum next week at the Santa Clara Convention Center:

Subramani Kengeri, Vice President, Technology Architecture, Office of the CTO, GLOBALFOUNDRIES
Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division, Mentor Graphics

This session explores the challenges of bringing advanced technology into high volume manufacturing. Similar to a Triathlon, there are three legs: Technology Architecture Development, Design Enablement and Manufacturing Ramp. Careful co-optimization of the interactions among all three disciplines is required at each stage of the process node maturity cycle. This technical session delves into critical requirements, challenges and solutions to enable SoC level product value and accelerated Time-to-Volume at current and future nodes, and touches on new approaches such as multi-patterning, FinFETs and IC reliability checking.
|-

Subi will start off with a quick overview of broad requirements that drive Foundry Technology which calls for deep collaboration with market drivers. Some areas of system design and technology collaboration will be discussed. Extending Mike Noonen’s point on changing landscape in the Mobile industry, Subi will touch upon the impact to foundry business and technology requirements before discussing details of two major challenges ahead: Device Architecture and Lithography.

Next he will go into details of critical technology considerations for mobile applications with focus on power density and EM issues. He will explain the technology architecture options for reducing active and standby power in SoCs. This will lead into a discussion on why FinFET architecture requires very careful focus of parasitic modeling, EM-aware standard cell design and metrology to ensure optimization of critical SoC metrics and volume ramp. With first generation FinFET architected for time-to-volume, he will discuss how GF is leveraging their HKMG Production ramp. Further, all the SoC level optimizations done on 20nm planar, which gave it ~15% competitive area advantage, are being carried over to 14XM. He will show a comparison of critical metrics between 28nm, 20nm and 14XM that will highlight the key values of GLOBALFOUNDRIES offerings.

In the third section, Subi will go over 14XM development status and all the technology risk mitigation approaches we are using to bring up first generation FinFET into high volume quickly. Also, Subi will summarize ecosystem readiness for advanced technologies and then provide a view of the 10nm and 7nm technology roadmap. The talk will end with the importance of packaging technologies and show the GF roadmap for the next few generations.

I hope to see you there! Join me for lunch!

January 31, 2013June 14, 2019

Building Energy-Efficient ICs from the Ground Up

Building Energy-Efficient ICs from the Ground Up
by Daniel Payne on 01-31-2013 at 6:02 pm
Categories: Cadence, EDA

My oldest son just upgraded Smart Phones from a 3″ display to a 4.5″ display and was shocked to discover that his battery barely lasted 8 hours, so I welcomed him to the reality of limited battery life in modern SoC-based mobile devices. There is some hope in increasing battery life for our consumer-oriented devices and the engineers at Cadence make a case for this in a White Paper: Building Energy-Efficient ICs from the Ground Up.

Continue reading “Building Energy-Efficient ICs from the Ground Up”

January 30, 2013June 14, 2019

Going to DAC 2013 in Austin? The Country’s Best Barbecue is a 20 Minute Walk

Going to DAC 2013 in Austin? The Country’s Best Barbecue is a 20 Minute Walk
by Paul McLellan on 01-30-2013 at 8:05 pm
Categories: EDA, Events

Going to DAC? I just booked my plane ticket last weekend since flights from the Bay Area to wherever DAC is are so often overbooked. It’s in Austin this year in case you’ve been living under a rock. There are lots of reasons to go, from the academic conference to the world’s biggest EDA exhibition. And here is one more: barbecue.

The Austin area is famous for great barbecue. But you used to need a car (and a lot of time) to really experience the best and make your road trips to Lexington, Lockhart, Luling, Llano, and more. But now there is Franklin Barbecue in downtown Austin. Bon Appétit magazine reckons it is the best in America.

It is at 900 East 11th Street which is a 20 minute walk from the convention center (work up an appetite). They open at 11am but you can expect lines. They stop serving when they run out of food which is around 1pm.

My son was recently sent to Austin to help open an office there. He said it is far and away the best barbecue he’s ever had but you really do need to be prepared to wait an hour to get it. The line starts at 9am and can be hundreds of people long. Make sure to say it is your first time there and if you are lucky they’ll give you samples of all the other stuff you didn’t order. To make sure you come back next time.

They are only open for lunch but they are closed on Mondays. So go and see the exhibits and all the other good stuff at DAC on Monday. Their website is here.

Anthony Bourdain was there:

January 30, 2013June 14, 2019

Catch Jasper at SemiIsrael Verification Day and at DVCon 2013

Catch Jasper at SemiIsrael Verification Day and at DVCon 2013
by Paul McLellan on 01-30-2013 at 4:08 pm
Categories: EDA

Jasper is presenting at both ends of the world at both ends of February.

First in Israel, it is SemiIsrael Verification Day 2013 on February 5th (next Tuesday) at Green House in Tel Aviv.

Zihad Hanna, VP of Research and Chief Architect and General Manager of Jasper Israel will be talking about Security Formal Verification of Hardware Design. I assume this will cover similar ground to the presentation from Haifa Verification conference that I already blogged about. That is at noon.
Then at 12.50pm, Mody Miller, Verification Manager at Broadcom will talk about Verifying Connectivity Across SoCs Using Jasper Formal Technology. He is in the unwelcome position of having the last presentation before lunch.

The website for the SemiIsrael Verification Day, including links to register, is here.

Then from February 25th to 28th it is DVCon in San Jose at the DoubleTree Hotel. Hotel rates for DVCon are discounted through tomorrow, Friday.

On Tuesday February 26th from 9-10.30am Rajeev Ranjan will present on Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability Standard. Details on the UCIS session are here. (UCIS is the Unified Coverage Interoperability Standard).
On Thursday afternoon of February 28th from 1.30pm until 5pm Lawrence Loh will give a tutorial on A Formal Approach to Low-power Verification. Full details, including an abstract of the tutorial, are here.

Jasper will also be exhibiting at booth 601. The exhibits will be open from 3.30pm to 6.30pm on Tuesday 26th and Wednesday 27th. Drop by to see demos of JasperGold Apps.

The DVCon website, including a links to register and for those discounted hotel rates if you are not local, is here.

Video introduction to DVCon (3 mins):