SemiWiki – Page 866 – The Open Forum for Semiconductor Professionals

May 10, 2013June 14, 2019

Prototyping Over 100 Million ASIC Gates Capacity

Prototyping Over 100 Million ASIC Gates Capacity
by Daniel Payne on 05-10-2013 at 12:42 pm
Categories: Aldec, EDA, FPGA

Most SoCs today are being prototyped in FPGA hardware before committing to costly IC fabrication. You could just design and build your own FPGA prototyping system, or instead choose something off the shelf and then concentrate on your core competence of SoC design.

Thanks to the FPGA vendors like Xilinx we now have FGPA prototyping platforms that can reach over 100 million ASIC gates in capacity at a reasonable cost. Aldec has created such an FPGA prototyping platform called the HES-7 and we’ve been blogging about it here on SemiWiki:

These prototyping boards use two of the Xilinx Virtex-7 2000T devices which have 4 million FPGA logic cells, or about 24 million ASIC gates in capacity, and that’s not counting the RAM and DSP resources available. You can then connect up to four of these boards together, so your total ASIC gate count is 96 million plus the RAM and DSP resources, crossing the 100 million gate barrier.

The popular ARM architecture is also available as the dual-core Cortex-A9 MPCore using the Xilinix Zynq-7000 device. You can even run open-source Linux, Android and FreeRTOS available from Xilinx on these prototyping boards, enabling your hardware and software teams to verify more quickly.

The speed of the HES-7 is fast enough (up to 1GHz or so) that you can prototype SoCs designs for: Video, Communications, Control Systems and Bridging. Add your own hardware to this board using the daughterboard connectors, which are open and fully specified. See a full list of features here.

Is my Library or Semi IP really OK to use?

Is my Library or Semi IP really OK to use?
by Daniel Payne on 05-10-2013 at 11:42 am
Categories: EDA, Fractal Technologies

The tremendous growth in IC and SoC design complexity has now enabled engineers to place bilions of transistors on a single chip. To make that growth possible design teams resort to using libraries and semi IP provided by other groups in their company, or outside IP vendors. To lower risk, you must know that the IP being used in your next SoC is correct and that no errors are present.

You could create some incoming tests on your re-used IP, or maybe even buy some Verification IP (VIP). There’s a three year old EDA start-up called Fractal Technologies that has a tool that help you test the quality of IP by:

Reporting mismatches or modeling errors for Libraries and IP
- Do all schematic pins occur as terminals in layout and abstract views?
- Are all delay arcs from Liberty present in Verilog?
- Can all pins be routed in first-metal?
- Is a reset pin active-low in SPICE, Verilog, and .lib files?
- Does the LEF abstract correctly cover the layout view?
- Do all cells abut?
- Check on presence and contents of cell- or pin-properties?
- Verify that certain pins are located correctly within a cell?
Checking view consistency (ECSM, CCS)
- Are CCS peak currents increasing with capacitance?
- Are cell delays increasing with increasing temperature and decreasing supply voltage?
Checks occurence and correctness of cells, pins and terminals
Cross-checks delay tables, delay path conditions, setup and hold-times
Checks consistency of Liberty characterization data
Checks routability requirements on cell terminals
Checks functionality descriptions
Checks layout representations
Checks can be coded by end-users in popular scripting languages

This checking technology is called Crossfire and it works with industry standard formats:

LEF, DEF
GDS II, Oasis
CDB
OA (Open Access)
Liberty NLDM, NLPM, NLNM, CCS, CCSN, ECSM
Milkyway from Synopsys
Verilog, SystemVerilog, Verilog AMS, VHDL
PLIB
Timing Library Format
HSPICE
FastScan, Tetramax
STIL/CTL (Core Test Language)

If you are a group that creates or uses Libraries or semi IP, then using this technology would improve your quality in a shorter time.

At DAC you can see the folks at Fractal Technologies in booth #1617, ask for Rene Donkers.

lang: en_US

May 10, 2013June 14, 2019

Forte CEO on Design and Verification Complexity

Forte CEO on Design and Verification Complexity
by Daniel Nenni on 05-10-2013 at 9:00 am
Categories: EDA

Sean Dart’s first DAC (Las Vegas) was as a customer in 1989. Designs were hitting 15,000 gates back then so he was looking for better schematic editors and simulators for gate level design. Fast forward 25 years and Sean’s customers are doing 15,000,000 gate subsystems and that number is growing steadily every year. Unfortunately design schedules are not growing so again EDA is critical. By automating the generation of high-quality RTL code from high-level design descriptions, companies like Forte provide a way for designers to handle the increasing gate counts without increasing design schedules.

Q: What are the specific design challenges your customers are facing?

The dimension that Forte addresses for our customers is that of complexity. Allowing designers to code models at much higher levels of abstraction allows them to deal with the complexity of both design and verification in a much more complete manner.

There is, of course, a productivity benefit in the initial creation of models (IP), but the most noticeable improvement comes through reuse. High-level IP is significantly more reusable (and retargetable) than RTL IP. This dramatically improves the value of that IP for our customers by both increasing the effective longevity of the IP and making it much cheaper (and more timely) to retarget in future designs.

Q: What does your company do?

Our flagship product is Cynthesizer, the number one SystemC-based high-level synthesis tool on the market. In the last few years we have also invested heavily in IP. This includes industry-leading fixed-point and floating-point IP which is shipped in tens of millions of consumer devices. We have also added a lot of IP in SystemC form, which is very high-level, retargetable and ready for use in your ESL flow. I believe that the industry will move to high-level IP in order to realize the gains offered by its flexibility and productivity gains.

Q: Why did you join your company?

I started out with Chronology in 1997 and was focused on verification. We merged with CynApps in 2001 to form Forte and the product direction moved to being more synthesis-focused. At that time, I was the VP engineering and became CEO in 2006.

The idea of building a high-level synthesis tool was intriguing to me and the concept of ensuring that verification was considered in the tool flow from the very ground up obviously fit my previous experience. This has proved to be one of the critical components leading to successful deployment of HLS in the marketplace. I am still very passionate about the technology and the continued growth in adoption of Cynthesizer is great motivation to continue down the path.

Q: How does your company help with your customers’ design challenges?

As I mentioned before, our products really help with the issue of design complexity. But it is not only about the core implementation tools. Forte has added a lot of supplementary IP that comes with the tool in order to help users get started more quickly. One example of this is the Interface Generator, which is a utility that allows users to quickly configure a number of complex interfaces and have full SystemC versions of those interfaces generated automatically.

Other non-core elements that are very important include tools to develop and debug your SystemC code and very complete training and kick-start materials and examples. This includes many white-papers, a complete online Knowledge Base, online instructional videos and detailed pre-canned examples and tutorials. Simply producing the best result from synthesis is not the only requirement. We have recognized that we need to work closely with new users to get them to the “expert” development level as quickly as possible, and these collateral materials are a critical element in that process.

Q: What are the tool flows your customers are using?

The Forte tool flow sits right on top of our customers’ existing RTL development flows. The input to the process is SystemC and the output is Verilog RTL that is then processed by all the major logic-synthesis tools and simulators. Forte provides complete methodology which includes integration and automation with those downstream tools to ease the path of adoption of Cynthesizer.

Q: What will you be focusing on at the Design Automation Conference this year?

We’ve widely been considered the industry standard for SystemC synthesis and this year we’re announcing the next generation of our Cynthesizer SystemC synthesis product – Cynthesizer 5.0.

Cynthesizer 5.0 is the culmination of several years worth of work to redesign our core synthesis platform from the ground up. We’ll be demonstrating the advantages of the new “C5” platform in terms ease-of-use, performance and quality of results.

Perhaps more importantly though, we are also introducing Cynthesizer Low Power, our low power synthesis product that utilizes the C5 platform and performs a number of low power optimizations directly in the Cynthesizer core – not as an RTL post-processing step.

We’re also rolling out our new ease-of-use products including a SystemC IDE called Cynthesizer Workbench and our new YouTube channel for customer education.

Q: Where can SemiWiki readers get more information?

We have a number of online resources to provide more information.

Our web site: www.ForteDS.com

Our YouTube channel, containing a number of instructional videos and demos:www.youtube.com/ForteDesignSystems

Our Facebook page:www.facebook.com/ForteDS

Our Blog: CynCity.ForteDS.com

And now our SemiWiki landing page:Forte on SemiWiki.com

Forte Design Systems™ is the #1 provider of electronic system-level (ESL) synthesis software, confirmed by Gary Smith EDA, provider of market intelligence for the global Electronic Design Automation (EDA) market. Forte’s software enables design at a higher level of abstraction and improves design results. Its innovative synthesis technologies and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. More than half of the top 20 worldwide semiconductor companies use Forte’s products in production today for ASIC, SoC and FPGA design. Forte is headquartered in San Jose, Calif., with additional offices in England, Japan, Korea and the United States. For more information, visit www.ForteDS.com.

lang: en_US

May 9, 2013June 17, 2021

Modern SoC designs require a placement- and routing-aware ECO solution to close timing

Modern SoC designs require a placement- and routing-aware ECO solution to close timing
by Jamie Chen on 05-09-2013 at 9:30 pm
Categories: EDA

As an applications engineer for over 15 years supporting physical design tools that enable implementation closure, I have seen the complexity of timing closure grow continuously from one process node to the next. At 28nm, the number of scenarios for timing sign-off has increased to the extent that is way beyond the number that a Place & Route tool can handle. Most designers turned to Static Timing Analysis (STA) tools for a solution. But the STA tools have two limitations:

STA tools usually run in a scenario-by-scenario fashion. For STA tools to generate ECOs that close timing for all scenarios, one would need to run multiple sessions at the same time, one session for each scenario. This requires the STA tools to be run simultaneously on multiple servers, with each server needing a license.
Current STA tools do not have or use the physical information. As a result, many ECO’s (Engineering Change Orders) generated by STA tools may end up being not implementable in the physical world due to placement and/or routing congestions.These limitations prompted for a new solution that can:
Simultaneously handle large number of scenarios without requiring large number of licenses/server machines
Understand the impact placement and routing have on those scenarios and hence implement ECO directive accordinglyThese requirements are critical to effectively and efficiently achieve timing closure.
Without these capabilities, designers are forced into not only a process that takes too many iterations and longer time to closure, and often have to accept lower chip performance for time to market.

In a recent customer engagement, I had to help the customer close timing on a design that was highly congested in both placement and routing. In addition, the design required timing closure on more than 100 sign-off scenarios. It would have taken multiple engineers and many weeks to close timing using an STA based methodology.

A key point to note is that not all routing congested areas are also placement congested, such as the channels between the macros at the top level of an SoC design. Hence, to effectively address timing violations, the tools and flow must understand both placement and routing congestion. Otherwise, one might cause new setup violations while fixing the hold violations due to detoured ECO routes. This is the primary reason why an STA based flow that is not placement and most importantly routing-aware takes many iterations to close timing.

We identified the congestion issues and used a placement and routing aware timing closure solution that could simultaneously handle all MMMC scenarios. Results: quicker timing closure with far fewer iterations!

At 20nm, a timing closure solution must be routing aware, because the additional requirements of double patterning and Vt implanting rules have a direct impact on timing and hence closure.

Welcome your comments and sharing your experiences with timing closure.

ICScape Inc. (Santa Clara, California) develops and markets solutions that accelerate SoC design closure. Its flagship products, ClockExplorer and TimingExplorer were released to the market in 2006 and 2009 respectively. They have been successfully used and taped-out in over 100 SoC designs. Other products from ICScape include PowerExplorer, RCExplorer and LibExplorer. It offers sales and technical support for its products in US, China, Japan, South Korea and Taiwan.

lang: en_US

May 9, 2013June 14, 2019

Are there enough FPGA tools?

Are there enough FPGA tools?
by Luke Miller on 05-09-2013 at 9:00 pm
Categories: FPGA, Xilinx

Sometimes I send my boy to grab me a tool and hours later he comes back with the wrong one. The patient man that I am, I calmly explain what I mean and then the world is right once more. Believe that do ya?

As you know the world is flooded with tools, tools and more tools. We all have our ruts and favorite flows and such but given the huge FPGA densities here and now and the future will no doubt bring more mixed signal devices what is the right set of tools?

I had a nice phone call with an EDA company this morning and we agree with this observation. People are scared of FPGAs, and HLS is not being embraced. Why? Of all the tools out there, in my small opinion HLS is the best tool of the last decade. I’m really curious what is stopping you? My guess is big company politics. Sometimes tool flows are set by people that do not do the job. Ahhh the process police, watch out they are corrupt.

The other tool observation is that now and beyond, for FPGAs we cannot settle for spin, re-spin like a 100 times over; especially in simulation. We make our test benches, we make our test vectors for hardware, we tweak our chip scope etc… There is much time wasted on doing close to the same things over and over. We must get better at it and need to do it once or twice. The tools need to intelligently handle requirements change, as the requirements are written by women therefore we are not sure what they mean. Can you believe I just wrote that? My old job would have me in front of HR as we speak, and I would have to fake listen. So I leave this blog open ended, and here is the question?

Say I want you to design a function, a SINE function, Taylor series expansion, floating point at 100 MHz, 20 clock latency, FIFO in/out. From start to finish what is the flow you would use? I’m thinking we would have many different answers. I’ll share mine, MATLAB, then Vivado HLS in about 5 minutes. Then simulate once in ModelSim. Looking back, my tools preferences are based on what I was forced to use by the man. Being on my own is allowing me to actually find the best flow and I know that will deviate some but this I know; the way I do things and you do things is going to change if we want to stay competitive.

The upside for FPGAs is they are staying around for a while. GPUs and CPUs cannot compete with the deterministic low latency solution that the FPGA offers. We FPGA users can control every bit, so that’s good news for you control freaks. So please comment below and share what flow you use.

lang: en_US

May 9, 2013June 14, 2019

Places Around the Austin Convention Center

Places Around the Austin Convention Center
by Paul McLellan on 05-09-2013 at 8:05 pm
Categories: Events

Jerry Philippe used to work for me at Compass and then very briefly we worked together at VaST. Today he works for Calypto in Austin. And it is the Austin part that is important because Jerry knows where the places are in any city to get good food and drink but Austin is his home.

Austin has an extraordinary number of restaurants and bars. But let’s start with places around the convention center. The first couple are open for lunch, the others are more like bars and steakhouses for dinner (steak seems to crop up a lot in Texas restaurants, is cattle a thing there?).

Swift’s Attic: Modern American small plates, sandwiches and more. 315 Congress Avenue at 3rd, suite 200. Open 11am to 2am.

Not holding to any particular cooking genre, but creative, whimsical and delicious. Not to be outdone the bar features 14 draft beers, 24 wines by the glass and cocktails all supplemented with an ice tap with 4 liquors able to be poured ice-cold instantly.

Sullivans: Sandwiches, steaks and stuff. 300 Colorado Street. Open 11.30am to 2am, Monday to Friday (and evenings at weekends).

(10 min walk from convention center located on Colorado and 3rd St.) is a vibrant neighborhood American Steakhouse featuring the finest steaks, seafood, hand-shaken martinis and live music. Comfortable fine dining in a lively atmosphere. Whether it’s for business, pleasure or both, we look forward to quickly becoming your favorite local steakhouse.

Elephant Room: Famous jazz bar, no food. 315 Congress Avenue (underneath Swift’s Attic). Usually no cover on weeknights. Happy hour 4-8pm. Walking distance.

Flemings: Steak and wine bar. 320 East 2nd Street.

(Behind convention center) For over ten years, Fleming’s Prime Steakhouse & Wine Bar has been the place to be in Austin for great food, amazing service and spectacular wine. Serving Midwest corn-fed USDA Prime beef, fresh seafood and our award-winning wine list, Fleming’s is the perfect destination for any occasion.

Eddie V’s: Pricey steak and seafood, so somewhere to get a C-level executive to take you out. Live Jazz. Not open for lunch. 315 E. 5th Street.

(2 block walk from convention center) Enjoy a robust and varied selection of fish and shellfish hand selected from the top catches of the day. Or indulge in our critically acclaimed aged steaks, broiled to perfection and lightly brushed with butter. Complemented, of course, by the ideal wine pairing, and completed with irresistible side dishes and desserts. All presented to you by a gracious, professional staff eager to serve.

Vince Young Steak House: Err…steak. Are we detecting a theme here. He used to be a pro footballer but Jerry assures me Vince’s steaks are better than his pro football record. 301 San Jacinto Blvd

(behind convention center) Vince Young Steakhouse is a chic, inviting and local Austin, Texas fine dining restaurant. We serve the finest steaks, wines and desserts in a downtown lively atmosphere with exceptional service. No matter what the occasion; a romantic dinner for two, an important business meeting or gathering your family around the table, at Vince Young Steakhouse, we look forward to providing you with an exceptional dining experience.

Kenichi: No steak (well maybe just a little, this is Texas), just great Japanese food and lots of variations of Sake. 419 Colorado St, just off Congress and 5th. Not open for lunch.

(walking distance of Convention Center) trendy sushi house with unique Texas style food. Kenichi prides itself on having the freshest seafood available in Austin to serve in all of its dishes. In addition to receiving recurring shipments of seafood from the coasts on a regular basis, Kenichi’s Executive Chef Shane Stark has utilized his love of fishing and the sea to cultivate relationships with Texas-based fisherman.

May 9, 2013June 14, 2019

Design IP round #2: after road-test, time for the race

Design IP round #2: after road-test, time for the race
by Eric Esteve on 05-09-2013 at 10:58 am
Categories: Cadence, EDA

Design IP, at least Interface IP, is about 15 years old, but the market was made of one large provider – Synopsys- with many small vendors around. Chip makers were not very comfortable with this picture, especially the Tier 1 considering that the risk (to see the big one being acquired by one of their direct competitor, say Samsung or Intel) was unacceptable. This was the picture in 2010: Synopsys leader on every Interface IP segment, Cadence leader in Verification IP, but only in VIP, and many small IP vendors acting like an electron cloud around Synopsys atom… Moreover, the market value of design IP was 5X the VIP market value, and this is still the case!

You have to keep in mind that building a design IP port-folio is far to be easy: ask Mentor Graphics why they had to give up in 2007, after 10 years of engineering effort. In 2010, Cadence has passed a clear message to the market, with Denali acquisition (for $300M +), but this message has been blurred when the company spoke about “EDA 360”. Design IP is a particular piece of the equation as it goes in a Chip which, in turn, goes to a wafer-fab, when Software, as important as it can be to release a product, is not as critic as a Design IP is.

The venue of Martin Lund (from Broadcom, known to deliver chips, not only paper, to the market) in Q2 2012 to take care of the “Silicon Realization Group” within Cadence has shuffled strong energy to cadence IP strategy. Martin has probably visited many IP vendors companies during 2012, then 2013 has been the time for finalization. Tensilica, provider of customizable DSP or CPU IP cores, has been the first in the list, being acquired by cadence in March 2013. Very interesting to notice, Simon Segars was quoted in the PR mentioning this acquisition… If you want to build a successful IP strategy, it’s probably better not to directly attack the undisputed leader, ARM Ltd.

Almost at the same time came the announcement that cadence was acquiring Cosmic Circuit, India based mixed-signal IP vendor, providing DAC and ADC, and Interface IP PHY supporting MIPI M-PHY and D-PHY and SuperSpeed USB PHY. If you look at the above picture, Cosmic brings the blue-boxes, that you will find in almost every SoC today. But that was not enough! Denali acquisition allowed supporting many more protocols Verification, but only two Design IP: DDRn Memory Controller and PCI Express.

Then came the first announcement during CDN-Live, on Tuesday this week, Evatronix acquisition. Box colors have changed in the meantime, but the principle stay the same: Evatronix acquisition brings the green colored boxes, USB 2.0 and USB 3.0 controllers, some MIPI controllers , eMMC and SDCard. You may have the impression that Martin Lund, above pictured, looks tired: the acquisition contract with Evatronix was signed during Sunday night, right on time for CDN-Live! According with Wosjiech Sakowski, Evatronix co-founder and President, the signature came after long hours –days – of negotiations.

But I keep very interesting acquisition related news, which was made public during CDN-Live as well, even if it was effective a few weeks ago: Cadence has bought, not a company, but an Engineering team. This 25 Engineers Canadian based team from PMC-Sierra is 100% specialized in SerDes design, and you can guess that they don’t limit to 5 Gbps PHY. Why is this news so strategic? Because PHY is strategic, as I already claimed in Semiwiki here.

Just remember that Synopsys had to buy a PCIe 8 Gbps PHY to MoSys last year to be able to support customers. This design team is probably capable to manage 25 Gbps SerDes (my guess). In this case, half a dozen IP sales from this team could generate Evatronix per year revenue, made of multiple dozens of controller IP sales. But that’s not the most important: this who manage properly the PHY IP business will manage to get higher market share of Integrated (PHY + Controller) Interface IP sales, now and for the future; especially in the future.

Eric Esteve from IPNEST

lang: en_US

May 9, 2013June 14, 2019

The Morphing of Intel’s Monopoly

The Morphing of Intel’s Monopoly
by Ed McKernan on 05-09-2013 at 12:01 am
Categories: Foundries, Intel Foundry, TSMC

It was a generation ago when Intel, less than three years old, created the three fundamental building blocks of the compute era: the DRAM, the EPROM and the Microprocessor, an incredible feat of innovation by any measure. Manufacturing yield, not power or performance determined success of failure and in the first two Continue reading “The Morphing of Intel’s Monopoly”

May 8, 2013June 14, 2019

GSA Awards…Nominate!

GSA Awards…Nominate!
by Paul McLellan on 05-08-2013 at 4:50 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

For 19 years GSA (presumably going back to the days when it was Fabless Semiconductor Association, FSA) has recognized public and private semiconductor companies. The awards are celebrated at a dinner. This year’s dinner is on Thursday December 12th at the Santa Clara Convention Center. The keynote speaker at the dinner is Cory Booker, the mayor of Newark NJ.

Nominations for the awards are now open.

Dr. Morris Chang Exemplary Leadership Award. The GSA’s most prestigious award recognizes individuals for their exceptional contributions to drive the development, innovation, growth and long-term opportunities for the semiconductor industry. Nominations will be accepted until June 3, 2013.
Best Financially Managed Semiconductor Company
Most Respected Private Semiconductor Company Award. Designed to identify the private company garnering the most respect from the industry . GSA’s Private Awards Committee provides a list of respectable private companies to be voted on by GSA membership. On-line voting takes place to allow GSA members to cast a ballot for the private semiconductor company that they most respect. (Nominations by June 28th)
Most Respected Public Semiconductor Company Awards
Outstanding Asia-Pacific (APAC) Semiconductor Company Award
Outstanding Europe, Middle-East, Africa (EMEA) Semiconductor Company Award (July 12th)
Start-Up to Watch Award. GSA’s Private Awards Committee, comprised of members of the Emerging Company CEO Council, venture capitalists and select serial entrepreneurs in the industry, selects up to two winners of the Start-up to Watch Award by identifying the semiconductor company(s) that demonstrates the potential to positively change its market or the semiconductor industry. (June 28th)

Public companies do not need to be nominated since they are assessed based on public financial data. But private companies and individuals do need to be nominated. Forms.

If you want to attend the dinner (either as an individual or as a company purchasing a whole table) then the details are here. The dinner is made possible by sponsor TSMC as well as some other general sponsors.

Full details of all the awards, including the small print (“must be a semiconductor company” etc) are on the GSA website here. This is also where you can find links to the nomination forms .

May 8, 2013June 14, 2019

IP Quality: Foundation of a Successful Ecosystem

IP Quality: Foundation of a Successful Ecosystem
by Eric Esteve on 05-08-2013 at 8:46 am
Categories: Foundries, IP, TSMC

Talking about Design IP (I mean successful Design IP) lead you to quickly pronounce the two magic key words: Quality and Ecosystem. Those who remember the IP emergence in the mid 90’s know very well why Quality has to be a prerequisite when dealing with Design IP, as they probably have paid the price of mediocre IP quality at that time. More recently, business analysts have realized that the foundation for a successful IP based business was linked to building a complete Ecosystem, just think about the 1000 ARM partners…

As a matter of fact, some of these partners are heavyweight, like Taiwan based TSMC, that any IP vendor would like to count within it IP Ecosystem. That’s why TSMC has created, back in 2000, the TSMC9000 program as one of the pillar of Open Integration Platform (OIP) ecosystem. TSMC9000 clearly defined goal is to check for, assess and audit the quality of Design IP part of OIP ecosystem. TSMC9000 is not only based on cleaver communication, but on a very rigorous process! Don’t forget that any of this Design IP function will end up into a very concrete piece of Silicon, an Integrated Circuit, and that both TSMC (who process it into Wafer Fab) and the Fabless customer who plan to sell it, expect this IC to run first time right. As an IP vendor, you submit to TSMC (in fact to “IP Portfolio, Design Infrastructure Division”) the functional IP you have developed, from USB PHY to DDR Memory Controller, LVDS I/O to DSP and many more. TSMC9000 Quality Assurance system consists to run successively:

DRC/LVS (if you submit Hard IP)
Data Consistency check
ESD tolerance verification
Design margin verification (Shmoo plot)
Then generate Silicon reports (on Test chips) and store production history when it’s relevant.

Your IP will hopefully be sold to customer, integrated into a design data base by this customer who will finally submit the final DB for Tape Out. At this stage, TSMC will use “IP Master” tool, running “Tape Out consistency checks” versus the previously generated data in IP9000 IP Quality.

You may wonder that TSMC9000 IP qualification process only applies to very complexes or very specific or “exotic” Design IP… In fact, if you take a look at the above picture, you realize that TSMC9000 apply to ALL the Libraries, Memories or IP, including Hard and Soft IP. How many IP would you guess? Are we talking about 500 Design IP, or 1000, maybe 2000? Just take a look at the statistics listed below…

There are no less than 8917 active IP coming from the IP Alliance for a total of almost 10, 000 IP in TSMC 9000! Another figure is surprising: almost 200 Design IP are being reviewed every month by TSMC. This means that TSMC has built a specific team 100% dedicated to run IP9000 QA Process, a 30 people team in charge of IP Port-Folio validation (and selection). As an IP vendor, you probably better understand why TSMC has to be highly selective when accepting new IP… Are you still in IP vendor shoes? Just look at the failed TSMC 9000 IP count: 1,452!!

Even if a dummy density violation or some Silicon corner out of specification can be accounted for a failure, out of these 1,452 IP, as high as 373 can generate potential fatal failure. Fatal simply means that a Tape Out including such IP would have led to a redesign. Thus, if you go now into Fabless shoes, you will just thank your foundry supplier for being so selective!

If you ever surfed on a foundry web site, you probably remember the “Bronze”, “Silver” and “Gold” denomination for Design IP. If you look at the above picture, these denominations look a little bit obsolete: before a Design Hard IP can be validated for volume production, it has to pass through no less than ten or more verification phases, before the Design IP can reach a high enough confidence level. If we consider advanced nodes, the Hard IP has to pass through 13 various checking phases, from DRC, LVS, ERC and Antenna checks up to Split Lot Silicon Assessment, testing results audits by TSMC test lab to finally go to production. In fact, Quality assessment is a never ending process, when the ASIC or ASSP is in volume production, the IC yield is continuously traced… probably up to the product End Of Life!
I didn’t know that Quality could be a fascinating topic (to be honest, I thought it was not), but we are working in such demanding industry that even Quality becomes part of the dream: I have today in my pocket a gaming station from the 2000’s, a phone from the 90’s, a color TV from the 80’s and a Supercomputer from the 70’s, all of these almost in a single chip!

Eric Esteve

lang: en_US