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Oasys Announces Floorplan Compiler

Oasys Announces Floorplan Compiler
by Paul McLellan on 05-19-2013 at 5:58 pm
Categories: EDA

Today Oasys announced the availability of Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. This is actually a repackaging of a capability that has always been in RealTime Designer, and in fact has been an important aspect of how well RealTime Designer has performed in benchmarks over the last four years. Until now, though, it has not been available as a separate tool.

However, now the design team can create a floorplan directly from the RTL that is aware of the design’s dataflow and also meets all the constraints for timing, power, area and routing congestion. The resulting floorplan can then be fed forward as initial guidance to the physical design teams.

Floorplan Compiler takes into account regions, fences, blockages and other physical guidance. The advanced editing tools make it easy to take an initially created floorplan from Oasys, make changes and then iterate getting better versions multiple times per day. One of the most time consuming tasks in SoC/ASIC design is getting a good quality floorplan. Oasys floorplan compiler reduces the time required for this task from a typical 4-6 weeks down to a few days.

The underlying approach of the RealTime synthesis engine is that it optimizes at the RTL level using a placement first methodology. No timing is undertaken without the cells being placed, since in a modern process most of the timing is related to placement and routing and not just the basic cell timing. When timing constraints are not met, then instead of just running gate-level optimizations, the algorithms return to the RTL level and re-sythesize a local area of the design using the improved knowledge. A sort of rip-up and re-synthesize. This approach results in huge capacity (the whole gate-level netlist does not need to be processed at once) and incredibly short run-times (gate level optimization is very expensive and avoiding it saves most of the time taken by traditional synthesis). For floorplanning, this infrastructure makes it straightforward to optimize RTL partitions (and change them iteratively) and automatically place macros, pins and pads to create a high quality floorplan driven by the constraints provided.

The input to Oasys RealTime Floorplan Compiler are the standard synthesis inputs (RTL, constraints, libraries) and the output is a standard floorplan DEF file which can either be fed into traditional synthesis tools or into place & route tools as an initial floorplan. So Floorplan Compiler drops seamlessly into existing flows.

More details on Floorplan Compiler are available here.

Oasys will be demonstrating Floorplan Compiler at DAC at booth 1231.

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Dassault DAC Assault

Dassault DAC Assault
by Paul McLellan on 05-19-2013 at 3:25 pm
Categories: Dassault Systemes, EDA

Dassault Systèmes is not a company entirely new to DAC, but with the acquisition of Matrix One (which had already acquired DesignSync) a few years ago and Tuscany Design Automation’s PinPoint last year they now have a richer portfolio to support various aspects of electronic design. By the way, Dassault is a French company so if you want to be correct you should pronounce it the French way, meaning the “lt” at the end is silent. So it is Dass-o not Dass-oat. Systèmes is pronounced slightly differently in French (that accent does mean something and the “es” at the end is silent) but I’ll let you off on that one. Even DS themselves drop the accent most of the time. Spot tests will be taking place on the DAC exhibit floor 😉

DS’s solutions do not directly perform design, rather they keep track of all the various views, ensure that requirements are captured and track if they are met, keep views synchronized, keep track of timing closure progress and so on. In some segments this is known as Product Lifecycle Management or PLM although in the IC design world I’ve never heard anyone use that term.

But DS remains a little bit of a well-kept secret in the industry. So come and visit booth #1625 to find out about innovative solutions to these growing challenges:

  • The latest in design collaboration with DesignSync for semiconductor design data management and Pinpoint for design intelligence
  • How simulation lifecycle management can ensure that product requirements are met throughout the entire design and development chain
  • An innovative development environment that ties together product, design, and manufacturing engineering and allows visibility from new product introduction through product delivery
  • A comprehensive IP Management solution, providing a single source of truth and targeting all aspects of IP governance

DS’s Pinpoint technology (the Tuscany product) provides a level of design intelligence that has been missing from semiconductor design flows:

  • Instant access to latest design data, including timing, power, layout, log files, reports, and more, without having to invoke physical design tools
  • An intuitive web enabled common platform for collaboration across sites and between RTL and physical designers
  • Full chip simultaneous visualizations of relevant timing, power, congestion, cell views, and physical layout

ENOVIA DesignSync and IP Management solutions provide a scalable and comprehensive IP management environment with role based use models and protection:

  • Single solution to manage internal and external IP
  • Links to design, process, industry schema, shared processes
  • Covers portfolio, part, document, supplier and knowledge management
  • Single source of truth for all IP parametric, license, warranty, compliance, technology and application information

Finally, DS’s Simulation Lifecycle Management solution drives product quality and performance for new products designed for market leadership:

  • Bridges the gap between product requirements, design and product verification and validation processes and disciplines
  • Improves team visibility, communication, and collaboration using a central repository and tool to manage product requirements
  • Provides a platform and infrastructure for a comprehensive V&V flow that allows for clear and accurate measurement and metrics reporting

Dassault Systèmes are at booth 1625 at DAC in Austin, first week of June.

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Supporting the Customer Is Everyone’s Job

Supporting the Customer Is Everyone’s Job
by Amit Varde on 05-19-2013 at 10:40 am
Categories: Cliosoft, EDA

EDA software is quite different from off-the-shelf software. In most cases, customer requirements are unique and depend on the proprietary and complex design process, environments and standards developed and/or evolved by semiconductor design teams over a number of years. EDA software ends up being heavily customized to conform to the customer’s standards and design flow.

With each customer design flow presenting unique challenges, EDA vendors must not only provide the software tools but also back them up with high quality and high touch support and services. This makes the Application Support Team a critical component for the success for the EDA vendor.

Support teams require extensive domain knowledge of various design environments and the skills to customize intricate requirements. They will sometimes need to pull in the development team to solve complex issues and provide solutions that users demand. One way to achieve top-level customer service is to build a culture where “supporting the customer” is a top priority in the company at all levels of management and engineering hierarchy. A side effect of this culture is that engineering managers and developers get to see how their software is actually used and deployed by the design teams, and get a much better understanding of the end user environment where tools are used. This helps the entire organization improve the quality of software and accomplish customer satisfaction.

Investing time and effort in support protocols is very consequential to the success of any EDA product.

  • A support website should be a one-stop-shop to answer a user’s technical questions. It should therefore be able to provide technical resources like release notes, downloads, constantly-updated FAQs, articles on customization, user discussion forums, demo videos and training in an easy-to-navigate portal. The more focused the resources, the less time that users and support teams spend on issues. Allowing users to subscribe to RSS feeds FAQs, release notes, etc. helps keep the user base active and informed of product features and developments.
  • The support portal should be integrated with a good ticketing system with active participation from customers, support engineers and development teams. Users should also be able to look at issues that their peers in the organization may have faced. This avoids unnecessary duplication and improved knowledge sharing within the organization, helping to provide faster resolution to issues and, in many cases, also helping them to optimize their design environments. Allowing tool developers to have easy access to the ticketing system and encouraging them to participate helps identify software deficiencies more quickly and to plan for new enhancements. It also allows support groups to plan tailored training session for customers.
  • “On demand collaboration” via phone and screen sharing tools is critical to resolving customer issues efficiently. Often, with critical issues, screen sharing allows support teams to be virtually onsite immediately and to quickly bring in other experts or even members of tool development team to resolve issues, if necessary.

Excellent technical support is a true win-win situation for the EDA vendor and their customers.
The simple key to becoming famous for customer service and support is a company-wide commitment to making customer needs a top priority. For ClioSoft, the result has been customer feedback such as this: http://www.cliosoft.com/support/index.php

Supporting the customer is really everyone’s job.

See Cliosoft at DAC:
http://www.cliosoft.com/dac/

Also Read

Cliosoft CEO on Design Collaboration Challenges!

Agilent ADS Integrated with ClioSoft

Data Management for Designers

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CEO Interview: Jason Xing of ICScape Inc.

CEO Interview: Jason Xing of ICScape Inc.
by Randy Smith on 05-19-2013 at 12:00 am
Categories: CEO Interviews, EDA

I recently had the opportunity to interview Jason Xing, Ph.D., CEO and President of ICScape, Inc. Below is a subset of the nearly two hour long interview.

How did you first become involved in EDA?
My EDA career started in the mid-90s when I started working on my PhD thesis at the University of Illinois in Urbana-Champaign. My thesis topic was on parallel algorithms for standard cell based placement. After graduation in 1997, I joined Sun Labs doing research on new physical design methodologies using concurrent logical and physical design. At that time, physical synthesis was becoming a critical need for high performance VLSI designs.

How did you end up at ICScape? How do you feel about the evolution of your role with ICScape?
After several years of research at Sun Labs, in 2001 I joined Sun’s internal physical design development team to lead the geometrical database design and router development, where I met Dr. Steve Yang. We talked often on the physical design issues and EDA tool limitations. We decided to start a company to develop effective tools for physical design. In 2004, I quit Sun, and started working on setting up ICScape Inc. In the early years of ICScape, I was the CTO and VP of Engineering in charge of the product architecture and development. After the products, TimingExplorer™ and ClockExplorer™ were developed and achieved good market traction, the board of directors requested me to take on the role of CEO and run ICScape. I saw this as a great opportunity and a challenge. It has opened a new chapter in my career.

What are the specific design challenges your customers are facing?
For large SoC designs, it takes too long and there are too many iteration to close timing due the fact that timing sign off and implementation tools are using different timing engines, creating a major correlation issue. Timing closure typically involves up to hundreds of corners and modes, and requires setup, hold, max. transition, and max. capacitance violations to be addressed. In today’s designs, thousands of timing violations are found by the sign off STA (static timing analysis) engine. Fixing them using STA’s timing engine or with the users’ custom scripts means that the placement and routing constraints and requirements are not taken into account at all. This is the reason for too many iterations. On the other hand, it is difficult for current P&R tools to address timing closure because they can handle only a few modes and corners at a time. In addition, their lack of timing correlation with signoff STA is a major hurdle against closure.

What are your plans for DAC this year? What is your goal for DAC?
Continue to promote our SoC design closure products, which include our flagship product TimingExplorer. This tool solves placement and routing aware timing ECOs, and is capable of handling all multi-corner, multui-mode (MCMM) scenarios together. Since the introduction of the company and its products at DAC last year, some of our products have received a high level of interest from potential customers. We have closed several high profile accounts and are in active evaluation with other companies. We want to continue the momentum and increase the customer base.

How does your company help with your customers’ design challenges?
Timing closure is a major issue for customers. TimingExplorer fully addresses the two major limitations of current tools and methods: 1) lack of timing correlation between STA and P&R tools and 2) an inability to simultaneously handle all MCMM timing scenarios. This is done by directly mapping timing graphs from the sign-off STA engine on to the built-in timing engine and leveraging a built-in P&R engine, capable of simultaneously handling all MCMM timing scenarios to generate ECO directives for the sign-off STA as well as the user’s P&R engine.
The results are better and faster timing closure using typically 2-4 iterations and cutting ECO time by 50%.

What are the tool flows your customers are using?
Major P&R and timing signoff flow. P&R flow include ICC and SoC Encounter EDI. Timing signoff flow tools include PrimeTime and ETS.

ICScape is currently aiding customers in timing closure and in the creation of clock tree synthesisconstraints, what adjacent areas do you think might make sense for ICScape to enter in the future?
We could and would like to do more in chip finishing and low power physical design solutions including low power clock trees, and dynamic and leakage power reduction.

To visit with ICScape at DAC, click here.

Also Read:

Atrenta CEO on RTL Signoff

Sanjiv Kaul is New CEO of Calypto

CEO Interview: Jens Andersen of Invarian

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#50DAC: Winning in Monte Carlo!

#50DAC: Winning in Monte Carlo!
by Daniel Nenni on 05-18-2013 at 4:00 pm
Categories: EDA, Solido

One of the places you will be able to find me at the Design Automation Conference (DAC) is on the speaker panel for a Monday Tutorial – Winning in Monte Carlo: Managing Simulations Under Variability and Reliability. Having worked closely with TSMC, GLOBALFOUNDRIES, Solido Design Automation, and some of the top fabless semiconductor companies, I have first hand experience with the increased variation at advanced process nodes and the increased SPICE simulation burden that results. Variation analysis and design software is absolutely being used by semiconductor companies and foundries to cut down on these SPICE simulations by intelligently figuring out what to simulate. This tutorial will give practical insight into causes of and solutions for variability and reliability. I highly recommend it.

Thanks to FinFETs and other process innovations, we are still shrinking devices. But it comes at a steep price: variability and reliability have become far worse, so effective design and verification is causing an explosion in simulations. First, Dan Nenni will do the introductions and present process variation content and analytics from SemiWiki.com. Presenter Prof. Georges Gielen from KU Leuven University will describe CAD and circuit techniques for variability and reliability. Next Yu Cao from Arizona State University will describe how at 20nm and new features from FinFETs, double patterning, interconnects, and other process innovations will require deep knowledge of variability and its relation to performance. More corners and statistical spreads will come into play, so advanced IC design tools will be needed to minimize design cycle times. Then, Trent McConaghy CTO of Solido Design Automation, will describe industrial techniques for fast PVT, 3-sigma, and high-sigma verification. Finally, Ting Ku, Director of Engineering at Nvidia, will describe a signal integrity case study using variation-aware design techniques.

Here is a preview of my intro slides:

Sources of Variation @ 28nm
•Random dopant fluctuation, RDF (from device Vt adjust implant)
•Metal line thickness variation (from variations in layout density, from the CMP polishing process)
•Via resistance variation (due to variation in barrier metal thickness filling the damascene trench + via)
•Gate line edge roughness, LER (localized gate channel variation)

Additional Sources of Variation @ 20nm
•Double patterning A/B mask misalignment, resulting in extraction variation between adjacent lines
•Much stronger focus on “preferred orientation” segments — “wrong-way” segments have a much greater litho variation, due to source-mask optimization litho data correction
•Introduction of “local MEOL interconnect” for active + gate contacts introduces new source of width/thickness metal variation — the MEOL is a large contributor to the gate-to-source and gate-to-drain coupling capacitances

Additional Sources of Variation @ 16nm
•FinFET-related variations… fin height tolerances, fin thickness tolerances, fin profile variation
•Relative magnitude of gate LER is larger
Fin sidewall roughness is a new phenomenon

Additional Sources of Variation @ 10nm?
•Triple- or quad-patterning –> mask mis-registration goes up… greater extraction variation
•Very restrictive layout design rules — e.g., NO wrong-way segments on lower metal layers… as a result, some variation could be mitigated?
•Metal line and via resistance tolerances go up… narrower metals imply a greater % of the damascene volume will be the barrier layers… greater % variation?
•Metal gate “grain boundary effects” (MGG) more prevalent… the grain size of the metal gate material is approaching Lgate… higher % variation in Rgate?
•New metal gate workfunction interfaces for device Vt’s…?

You can sign-up for the DAC tutorial here: http://www.dac.com/dac+2013+registration.aspx, or sign-up for a Solido software demo here: http://www.solidodesign.com/page/dac-2013-demo-signup/

lang: en_US

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SoC Optimization Using FPGA Prototyping

SoC Optimization Using FPGA Prototyping
by Daniel Payne on 05-18-2013 at 11:00 am
Categories: EDA

As an engineer I learn new concepts best by seeing a demonstration, in this case it was a demo of how to optimize SoC performance by using an ASIC prototyping debug process. SoC designers that use FPGAs to prototype their new ASIC often encounter debug issues, like:

  • Limited observability of internal nets required for debug, maybe only 1,000 nets for 1,000 clock cycles
  • Adding new internal probes requires a re-run of logic synthesis, causing delays of 8 or more hours
  • Partitioning RTL to fit into FPGAs automatically or manually can be error prone, or non-optimal

The demo on YouTube comes from the embedded instrumentation group at Tektronixand shows how their technology adds observability into your FPGA prototype that remove the three debug bottlenecks listed above. The product name for this technology is called Certus, and with it you can:

[LIST=1]

  • Get full RTL-level visibility during debug without rerunning logic synthesis.
  • View millions of clock cycles for debug.
  • See time-correlated debug data even if your SoC has multiple clock domains, and multiple FPGAs.

    Demo Steps
    An FPGA prototype was created using the Xilinx ML509 development board, and contains:

    • A 32 bit microprocessor, the SPARC V8
    • Ethernet MAC
    • JTAG port
    • Compact Flash
    • AMBA bus
    • DDR2 DRAM Controller, 256 MB of DRAM
    • SVGA output
    • Serial ports for keyboard and mouse
    • UART
    • LCD controller
    • PROM controller

    Performance Optimization
    The system level goal was to minimize the round trip time from issuing a Ping command, to when packets are received.

    To start this optimization a ping command is issued which starts the Ethernet traffic, and the connected router triggers the condition that we specified. Certus Analyzer captures about 6 seconds of realtime data from our SoC (millions of clock cycles), then presents it as VCD waveforms. Zooming into the waveform viewer we can see the trigger condition where the cursor points to the red line, and validate that the trigger address we requested is displayed as well:

    System-level values like the latency between transmit packet and receive packet can be debugged in great detail, allowing measurements down to each clock edge. With this type of debugging you can now start to optimize your SoC to reduce latency because you can fully see all RTL signals and see from the waveforms what the bottlenecks are in the system.

    Debugging State Machines
    Now that we know more about our Ethernet MAC signals, we next focus our attention to a new set of signals, like the state machine signals. With just a few clicks in Certus Analyzer you can change the group of signals and in a few seconds start to analyze state machine signals for the Receive FSM:

    Selected signals can be grouped together into a configuration, and for this design there were four configuration groups. You can quickly jump to a new configuration and immediately debug:

    The CPU Pipeline stage configuration is selected, and we trigger when the state goes to run:

    Summary

    ASIC prototyping with FPGA devices is a great way to debug your new SoC design and then optimize the hardware and software. The SoC debug process can be significantly improved if you have full RTL-level visibility with millions of clock cycles and can correlate across multiple clock domains and FPGAs. The Certus technology from Tektronix is unlike anything else out there.

    DAC
    To see Certus at DAC visit Booth #819, or for more info send an email to EIG-info@tektronix.com

    lang: en_US

    • Posted on

    5G – Reality or Fiction

    5G – Reality or Fiction
    by Pawan Fangaria on 05-17-2013 at 7:30 pm
    Categories: General

    Early in this week, I was reading news about Samsung announcing its breakthrough 5G mmWave technology. Well, this can bring fastest smart phone in the world which could enable several functions of day-to-day life and become revolutionary. The technology is not ready for commercial use, its building blocks seems to be working. There is an article by Ed Sutherland – Samsung unveils 5G mmWave tech for ‘tens of gigabits per second’ wireless downloads

    It has claimed downloads and uploads at the speed of “tens of gigabits per second”. Wow!! That appears like a fiction! A whole movie could be downloaded in seconds!! Below is an official snippet from the article –
    “Once commercialized, 5G mobile communications technology will be capable of ultra-high-speed data transmission up to several hundred times faster than even the 4G LTE-Advanced technology due for launch later this year.

    Samsung’s new technology will allow users to transmit massive data files including high quality digital movies practically without limitation.

    As a result, subscribers will be able to enjoy a wide range of services such as 3D movies and games, real-time streaming of ultra high-definition (UHD) content, and remote medical services.”

    It’s a wonder, even 4G is supposed to be tens of times faster than 3G. I want to ponder a bit on 5G technicalities before I talk about the commercial and business aspects of this important innovation. When do we call 5G a 5G? At least I do not know of any standard to define that. What should be the criteria? Of course, at the core of technology is a transmitter with 64 antennae transmitting more than 1 GB data per second. The test was conducted in a range of 2 KM over a very high frequency band of 28GHz; far away from the band used in cellular services today (4G works under 800 to 1800MHz). Capacity of data increases with higher frequency. In last December, a similar experiment was done by NTT DoCoMoin Japan with 24 antennae over a frequency of 11GHz. It’s a millimeter wave, works well in space for satellite, but can it penetrate physical world of trees and buildings we live in? Looking at the Samsungtest site and the way tests were done, it appears so.

    As usual, with every innovation, there comes plenty of bottlenecks and I am sure those will be overcome in due course of time (Samsung says, 5G can become commercially available by 2020). Obviously, other than antennae and frequency band, there are multiple technologies and components which will need to be assembled together to make it far reaching and available to people. Semiconductor has become an important and essential ingredient into every technology; not to mention it drives the smart phone business of today. Since DAC is around the corner, I was wondering whether there would be more announcements towards 5G and allied technologies related to 5G. Samsung is also among the exhibits; let’s see what’s more in store.

    Now coming back to whether it’s a reality or fiction. In my personal opinion, all major innovations have started with fiction which became realities. The first electric arc was invented by Humphry Davy in 1800. Much later in 1879 (in between several other experiments by other scientists were done), Thomas Alva Edition, after experimenting with several materials, discovered that a carbon filament could glow without burning in an oxygen free bulb for more than 40 hours. Later he invented materials lasting for more duration. The point is, once there is a spark; the ideas will keep generating to cash on that.

    In case of 5G, my view is that the idea has come much early in the phase, as 4G itself is yet to be widely realized. When 4G arrived, it appeared that 3G will not see the day, 4G will override. Now that 5G has seen the spark, it will become available, but when? Couple of questions come to mind –

    [LIST=1]

  • Is 2020 a realistic date for it to be commercially available?
  • Will all components of technology (I guess several mobile technology IPs) be ready by then?
  • 3G is able to satisfy the needs of video streaming, conferencing, live music and so on and then there is 4G. What more and unique services 5G can provide? How much people can and should spend on 5G? Both producers and consumers?
  • As we see in telecommunication, electronics, semiconductors…. economy of scale plays a big role. Considering that, can we say that 5G will override all others and can become available to all around the world at affordable prices?

    Of course, there can be many other questions; can we get answers to some of these inDAC 2013?

    • Posted on

    RTL Power Estimation at DAC

    RTL Power Estimation at DAC
    by Daniel Payne on 05-17-2013 at 7:22 pm
    Categories: Ansys, Inc., EDA

    If you design with ARMCores and need to estimate dynamic power early in the flow, then consider what STMicroelectronics has done with their high performance, power-efficient subsystems. Anne Merlande is a Processor Micro Architecture technical expert, and will be presenting in Booth #1346 at DACon June 4th, 2:00PM. Her topic is: STMicroelectronics: RTL Power Estimation on ARM Core Sub-systems. You have to register for this suite session.

    Continue reading “RTL Power Estimation at DAC”

    Posted on

    IC Design with No Clocks Used in a SMART Card

    IC Design with No Clocks Used in a SMART Card
    by Daniel Payne on 05-17-2013 at 5:21 pm
    Categories: General

    My IC design career started at Intel with DRAM chips, so I’m very familiar with clockless design because we used self-timed techniques to get maximum performance. I remember blogging about an asynchronous design company called Tiempo back in 2010, while blogging at Chip Design Magazine. A few weeks ago there was a press release that caught me eye: French Consortium Announces Development of a Clockless SMARTcard chip. Steve Svoboda is my contact at Tiempo and he sent me an email, which turned into a blog interview to satisfy my curiosity.


    Steve Svoboda, Tiempo

    Interview

    Q: Why did the partners choose a clockless design approach?

    The partners (Tiempo, Gemalto, CEA-Leti, Invia, Presto Engineering, and L Foundry) wanted to explore ways to generate the next level “breakthrough” in performance for contactless smartcards, while achieving equivalent or higher security. Tiempo proposed that using their technology to develop a clockless smartcard chip, the partners could realize a chip with substantially higher performance than other chips currently on the market, along with greater security and resistance to hacking, and monitoring attacks.

    Q: What benefits did clockless provide that the previous chip approach did not?

    In contactless smartcards, the chip is powered by the magnetic field strength received from the reader. This field strength varies with the cube of the reader-distance (making it extremely sensitive to the distance from the reader), as well as the orientation of the card relative to the reader (the card must be parallel to the reader for maximum field strength.)

    The clockless chip Tiempo developed for the ASMART project should run at substantially higher speeds than conventional chips on the market today, with equal or lower magnetic field strength from the reader. In addition, the speed of the clockless chip is able to vary dynamically and continuously as the magnetic field strength would vary.

    These technical advantages would enable OEMs using the chip to deliver contactless smartcards that process transactions faster, and more reliably (i.e. not requiring “reswipes” as often) than contactless smartcards currently on the market, without making any compromises on the security of executed transactions.

    Q: How long was this design project from concept to tape-out?

    ASMART is an ongoing multi-phase project, with delivery of progressively more advanced prototypes scheduled at the end of each phase. For security reasons, the effort/scope of the different phases in the project remains confidential. However the partners can say the design effort so far has never exceeded that for a conventional synchronous design (i.e., using a clockless approach has not added to the cost, labor effort, or schedule of the project.)

    Q: What were the design challenges, and how was each challenge met?

    The main design challenges were related to the “front-end”, i.e. modeling/synthesis, functional verification, and test.

    The Tiempo team modeled the entire digital portion of the chip in System Verilog, and then used Tiempo’s Asynchronous Circuit Compiler (“ACC”) synthesis tool to generate gates.

    Functional verification was performed with the SystemVerilog and gate-level models, using Synopsys VCS.
    Test was also challenging, as the design was entirely clockless. Tools for automatically inserting DFT for clockless designs don’t yet exist today, so Tiempo engineers had to rely on a handcrafted approach, heavily based on functional-test: in this circuit, test was almost entirely based on BIST.

    Notably, the clockless, delay-insensitive nature of the logic proved a big advantage during the backend stage, as timing-closure became much more simple/straightforward than would have been the case with a conventional-logic clocked design. Integration of the Digital with the Analog/RF portions is substantially easier due to the clockless nature of the digital logic (much reduced interference, and much smoother/more uniform power consumption.)

    Q: Which specific tools were used?

    Modeling – SystemVerilog
    Synthesis – Asynchronous Circuit Compiler (Tiempo)
    Verification – VCS (Synopsys)
    Place & Route – IC Compiler (Synopsys)

    Q: What did the design team learn along the way?

    The team learned:
    – how to apply a delay-insensitive, clockless design flow in the context of developing an entire SoC.
    – how clockless design makes backend timing-closure much easier than with equivalent synchronous logic.

    Summary
    It looks like Tiempo is finding it’s way in the world by becoming more of an IP company than an EDA company. They were able to create an EDA tool flow from tools that expected a clocked methodology, plus added their own for logic synthesis.

    lang: en_US

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    Are you going to the plug fest?

    Are you going to the plug fest?
    by Eric Esteve on 05-17-2013 at 10:16 am
    Categories: IP, Synopsys

    PCI Express 3.0 specification is 1000 pages long. Most of us, and most of the designers integrating PCIe gen-3 into their latest ASIC, FPGA or system will probably never read it completely, or even open it. In fact, they don’t need to read it completely, but they should care about one point, whether they buy an ASSP or a PCIe design IP: is this precise IP being certified? For the IP vendor, this certification can be obtained by submitting the freshly designed PCIe IP to a “Plug Fest”, or interoperability program organized by PCI Special Interest Group (PCI-SIG). Because PCI Express is defined as an Interface Protocol, the PCIe agent, Root Port (the equivalent of the Host in USB) or Endpoint (the Device equivalent), is supposed to be interfaced with any PCIe agent, Device or a Root Port respectively, not necessarily coming from the same design source, IP vendor or ASSP chip maker. During the Certification program, your PCIe IP will be plugged in front of various systems being used as reference, like Motherboards, and will have to pass a pre-defined operation test list. For an IP vendor, obtaining the PCI-SIG certification is the first step for successful market introduction, especially if you sale PCI Express Design IP.

    Synopsys has just announced that their PCI Express® 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance workshop for PCI Express 3.0. According with Synopsys, this means that “to achieve compliance, the DesignWare PHY and controller IP passed PCI-SIG’s three required Gold Tests: the electrical tests, the Protocol Test Card (PTC) and the PCIeCV software tests. In addition, the DesignWare PHY and controller IP demonstrated interoperability with more than 80 percent of the devices at the workshop, exceeding interoperability requirements.” For Synopsys customer being in the decision process for sourcing the PCIe PHY, Controller or Verification IP, knowing that these IP has obtained certification will dramatically increase the level of confidence into the product, and ease taking the decision. But not only, as the PCI-SIG certification is “associative” (think about your old algebra lesson!), the chip integrating this Design IP will be certified as well!

    Let me tell you a short story about plug fest. When PCI Express gen-1, the very first specification, has been issued in 2004, the market was still using PCI or PCI-X, both being parallel based interface protocol. PCIe gen-1 has introduced the bidirectional, dual simplex concept, supported by a SerDes based PHY, and the Controller was also based on something new in the PC space, the layered based protocol, including the Media Access Layer (MAC), the Transmission Link Layer (TLL) and the Application Layer (AL). Nevertheless, the PCI-SIG had to organize the very first plug-fest, as demonstrating interoperability was crucial to start a successful market introduction campaign.

    Guess who had designed the PCI Express Controller to be used as a reference? A small IP vendor named Cascade… that Synopsys bought almost immediately, ringing the start of a very successful PCIe IP sale decade, as you can see on the graphic below, as Synopsys has made almost $150 million in PCIe IP sales since Cascade acquisition. But if you read Semiwiki, you have seen this post and already know this story.

    Remark: this graphic has been extracted from the “PCIe IP Survey”, very recently updated by IPnest (the very last buyer is a well-known FPGA vendor, who has integrated SerDes supporting PCIe very early… and continue to do so!).

    Eric Esteve from IPNEST

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