Banner 800x100 0810
Semiconductor Expert Forum

Posted on

Challenges of Low Power Network-on-Chip Designs

Challenges of Low Power Network-on-Chip Designs
by Randy Smith on 08-05-2013 at 8:00 pm
Categories: IP, Sonics

Everyone understands that as we increasingly focus on the design of mobile devices, there is an increasing focus on low power. But, what is implied in designing for low-power? Designing for low power means we have to work with multiple power domains and multiple clock domains—making our design task more complex. We also must get these new mobile devices to market quickly, causing shorter design cycles. To accomplish this, more reusable IP blocks are typically utilized because they introduce fewer errors since these IP blocks are pre-verified. However, more IP blocks and more subsystems also bring more power domains in order to maximize the battery life of the end products.

[The diagram above shows the results of an industry survey regarding on-chip communications networks taken in October 2012 and commissioned by Sonics, Inc.]

With the increasing number of power and clock domains, there is a connection complexity which is growing exponentially. We need to connect all the different pieces of the design. This is difficult not just due the large number of functional blocks, but also the many unique combinations of power and clock domains. We are now hearing of designs with more than 20 power domains and more than 50 clock domains. Whereas, a set-top box ten years ago may have included a memory bus, peripheral bus, and some specialized buses for pipeline operations, these new designs must include a huge number of different connections.

To meet our design goals, we need to try for an optimal grouping of blocks as well as optimize the use of different connection styles. The connection styles include various standard interface protocols (e.g., OCP, AXI, or AHB), along with fabric choices such as routers, switches, and crossbar implementations. Managing the large numbers of connections of various types in a modern mobile design clearly creates a complex on-chip communications network (OCCN) design problem.

The primary goals in designing an on-chip network architecture for a chip in a mobile product now include:

(1) Meeting the performance goals of the design—frequency and latency;
(2) Optimizing grouping and choice of connection-type for the various domains; and
(3) Keeping the interconnect within the allowable wire congestion and area tolerances—by reducing the overall design effort using automation.

In selecting an on-chip network partner, consideration needs to be given to ensure that the vendor supports multiple fabric connection styles and a strong environment to analyze the network design choices that are made. This means looking beyond just the type of connection. For example, in some cases the designer can trade-off between ‘serializing’ versus ‘parallelization’ of the data—meaning wider or deeper channels. Of course, the design must consider many other complex trade-offs such as the number and use of virtual channels (a single physical connection that can have many logical connections).

The vendor that provides all this is Sonics, Inc. Sonics’ StudioXE™ development environment contains both graphical and command line tools to aid the user in the design process from architectural exploration to synthesis. The environment automates several design phases—saving the designer time by automating the creation of synthesis scripts, design constraints, timing analysis input preparation, and design-for-test management.

To help you meet your performance goals, Sonics has several on-chip networks available as design IP. Among these networks is SonicsGN™ (SGN), Sonics’ fourth-generation configurable on-chip network that includes native socket interfaces like AXI and OCP and uses a router-based fabric or ‘NoC’ (network-on-chip). SonicsGN enables the user to design advanced SoC communications networks by using a high-speed scalable fabric topology structure and is also the industry’s highest frequency NoC available today. The SGN architecture is particularly well suited for low-power designs by allowing for virtually an unlimited number of power, clock and voltage domains. The design tools provide the automation for these domains to be partitioned anywhere in the network, simplifying the SoC design task. In addition, SGN provides the signaling interface at each domain to allow a power manager unit to rapidly and reliably turn domains on and off. This level of control will save significant power over the traditional method of relying on software and the CPU.

For modern low-power design of mobile devices SGN is the type of network IP fabric that designers will need. Coupled with the other configurable connection in the portfolio, plus their StudioXE development environment, Sonics should be at the top of any designers list when it comes to solving mobile product design challenges.

Posted on

New Media and the Semiconductor Ecosystem!

New Media and the Semiconductor Ecosystem!
by Daniel Nenni on 08-04-2013 at 7:30 pm
Categories: General

Gary Smith did a nice write-up on the current state of electronics media. It’s posted on his Gary Smith EDAwebsite. Traditional media certainly is in transition and there is more change to come, definitely. Gary lists me as one of the heroes carrying the flag which is very nice of him to say. In reality though, he missed Paul McLellan and Daniel Payne, who are also heroes of EDA media.

A few years ago Paul, Daniel and I were simple bloggers writing when we had the time and inspiration. Daniel Payne’s DAC blogs document the history of DAC exhibitors and track their progress throughout the years. Paul’s collection of blogs in book form “EDA Graffiti” is the best read on EDA today. Hopefully my blogs on the fabless semiconductor ecosystem have been of benefit as well.

New media refers to on-demand access to content any time, anywhere, on any digital device, as well as interactive user feedback, creative participation. Another aspect of new media is the real-time generation of new, unregulated content.

To be clear, we are not editors, journalists, or analysts. We are bloggers, who, by definition, share our experience, observations, and opinions. By day we are consultants who help emerging technology companies with strategic business development, sales, and marketing activities. We also write white papers and business plans, moderate webinars and speak at conferences. At night we blog on SemiWiki which is very synergistic with our day jobs. I really like the term “New Media” as it best describes SemiWiki and what we are out to accomplish.

Its called crowd sourcing. Paul, Daniel, and I were joined by Eric Esteve and Don Dingee, and other bloggers who have something semiconductor to say. The SemiWiki forums are open to all members who would like a bully pulpit, and not surprisingly, the SemiWikicalendar of events is one of the highest traffic spots for those who want to engage with the semiconductor ecosystem.

SemiWiki uses a subscription based business model and currently has more than 40 subscribing companies. A SemiWiki subscription gets you our time and expertise on many aspects of your business. We help with messaging, branding, demand creation, and provide the resulting analytics to clearly document the new media ROI. Our subscribers are clearly listed in our legal / sponsor disclosure on the footer of each page per the FTC guide governing bloggers.

I feel that a subscription model is a more level playing field and much more ethical than selling temporary advertisement space to the highest bidder and not attaching a revenue disclosure to the content it “inspired”. Not all content on SemiWiki relates to subscriptions, which is why subscribers have dedicated landing pages for all inspired content.

As consultants, our reputations are our living so we are careful what we write. Our LinkedIn profiles are linked on the SemiWiki About page if you want to know more about our professional affiliations and work history. We do not do product endorsements. We do not do product testimonials. We are not shills. We write about technology and encourage our readers to investigate further and engage with the fabless semiconductor ecosystem. New media is all about transparency.

As of today, according to Google Analytics, 670,438 people have visited SemiWiki since January 2011. As of right now 483 registered members and 8,243 guests are on SemiWiki. The SemiWiki global Alexa Traffic Rank is 466,518, the U.S. traffic rank is 222,310, with 448 sites linking to SemiWiki. The founding father of EDA New Media, DeepChip.com, is ranked 1,384,829 global and 407,288 U.S. with 154 linking sites. Alexa is owned by Amazon so they know traffic. Interestingly, the FaceBook Alexa traffic rank is #1 global and #2 U.S., Google is #2 and #1, and Amazon is #6 and #5 respectively. Traditional media is all but dead, long live new media!

The other trend Gary pointed out is vendors hiring editors: Richard Goering works for Cadence, Michael Santarini works for Xilinx, Ron Wilson works for Altera, etc…. This is definitely a nail in the traditional media coffin and a big win for New Media, absolutely.

lang: en_US

Posted on

A Brief History of Docea Power

A Brief History of Docea Power
by Daniel Payne on 08-02-2013 at 2:55 pm
Categories: EDA



Founders

The founder, Ghislain Kaiser, spent about 10 years at STMicroelectronics, mainly in multimedia groups and for the wireless market. At this time, he was a power expert and tasked with making the chips use less power. The first thing he did was to look at what tools existed on the market. They wanted to use off the shelf tools but unfortunately they couldn’t find what they needed. He had a precise idea about what he wanted so he decided to leave ST and create his own company. Continue reading “A Brief History of Docea Power”

Posted on

Coke vs. Pepsi; Xilinx vs. Altera

Coke vs. Pepsi; Xilinx vs. Altera
by Luke Miller on 08-02-2013 at 10:00 am
Categories: FPGA, Xilinx

I have many thoughts on this topic, so forgive the word salad that may ensue. I have been thinking about Coca-Cola lately, partly because I bought an old coke machine (I’m one of those guys… pray for my wife). I am amazed that Coke which was founded in 1886, still has a secret recipe. I like that, but boy every time the web reveals the coke secret is out, I need to know. I’m such a snoop; there was coke news out a few years ago which showed a picture of the recipe. I think one guy is in jail for trying to steal it, can you imagine he really is in jail for trying to steal coke. No emails please.

I liken the Coke vs. Pepsi war to Xilinx vs. Altera. Daniel Nenni of Semi-Wiki said something very true in his blog titled ”Intel 14nm Delayed?”. Great article and yes we all are wondering if Altera is in trouble with that delay. Dan said “The semiconductor industry is so close knit it is very hard to keep a secret. Add in social media and it is near impossible.”

We know that to be true but I wonder how much of that affects the industry. I hope dear reader that you are loyal not only to your employer but to yourself and your God. Look around on LinkedIn and you can see the movement to/from Xilinx and Altera, AMD to/from NVIDIA etc… Are we only to believe that skills, leadership and aptitude are the only bits of talent transferred? We know better. Knowledge transfer even subconsciously is unavoidable, what are unavoidable are leaks from within. You know “Don’t say I said this but…” but we live in a ‘leaky age’ (that’s funny, and I now own that saying) where it is socially acceptable not to guard secrets and play word games or talk around them.

When workers left Pepsi to go work for Coke, does Coke taste like Pepsi? Nope, as Coke is sure in its product. Xilinx and Altera are sure in their product but more than ever, this next node is huge for many reasons. After both products yield (They will) what will be the market share picture? The hopes for each respective FPGA company will be to gain more of that share. What will gain that share? The obvious, DSP densities, Clock Speeds, Tools etc.. The not so obvious are the things that cannot be written about, those are the secrets of all the hardwork, time, and energy each company is pouring it’s heart into. It’s our responsibility to keep them secret. At some level it is fun when a huge game changer is announced and it’s one of those technology leaps that you are amazed at. Personally I’m a J.D. Rockefeller man; that is buying the competition, so if I owned Xilinx, I’d buy Altera. But I guess that is illegal now a days where our friendly government is making freedom illegal; not only monitors our internet usage, but sets the price of milk, corn, gas, owns the banks, and our health care system. Better keep that secret 😉

lang: en_US

Posted on

Apple Goes All Amazonian

Apple Goes All Amazonian
by Ed McKernan on 08-01-2013 at 4:00 pm
Categories: Uncategorized
3 Comments

In the world of Tech Goliaths, the seemingly low tech, not for profit Amazon continues to amaze investors with a high and rising stock price. More so than Google, Amazon is considered to have retail all wrapped up with the end game being sky-high warehouses and continuous truck rolls up and down our scenic neighborhoods. Walmart is considered finished, not today but eventually. What if Time Cook has finally come to his senses and decides that the way to make Apple much more valuable is by driving sales through the roof by dropping margins to the floor. It would be un-Steve Jobs like Continue reading “Apple Goes All Amazonian”

Posted on

Intel 14nm Delayed?

Intel 14nm Delayed?
by Daniel Nenni on 07-31-2013 at 10:45 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

One of the more interesting pieces of information I overheard at SEMICON West earlier this month was that Intel 14nm was delayed. This rumor came from the semiconductor equipment manufacturers and they would know. What I was told is that the Intel 14nm process has not left the OR development facility to be replicated in the OR and AZ fabs.

Process move-in is an important milestone to product launch of course. 14nm move-in was supposed to happen in Q3 but it did not. I got an update this week and was told it would “probably” not happen until Q1. The speculation is that it is a “qualification delay”. I expected to hear something about it during the Intel Q2 2013 conference call but per the transcript:

“14 nanometer on-track to enter production by the end of the year” EVP and CFO Stacy J. Smith

“We are on track to start production on our 14 nanometer process technology in the back half of this year. CEO Brian M. Krzanich

“As far as our 14 nanometer Core launch in our – just our general product launch, I think what we’ve said so far is, first half of 2014 and we’re not going to – we’re not ready to give any specifics beyond that.” CEO Brian M. Krzanich


Maybe they will address it in the Q3 conference call on October 15[SUP]th[/SUP]. What is Intel 14nm exactly and how does it compare to the other 14nm offerings? Good question.

In planar process technologies the 28nm or 20nm implies the minimum transistor gate length of 28nm or 20nm. Corresponding to that lithographic capability are two other critical dimensions: the “contacted gate pitch” and the “metal pitch” for the lowest, thinnest metal layers. (Higher metal layers will be thicker with less resistance which are more suitable for longer routes but will have a greater width+space design pitch.) Given that, the 22nm and 14nm FinFET process technologies are a bit of a misnomer.

Intel opted for single patterning at 22nm (80nm first metal pitch), while focusing on introducing FinFET’s. At 14nm, they will pursue a ‘full’ node shrink, in the sense that they will be using double patterning and a 64nm first metal pitch.

The foundries took a risk in pushing for a 64nm first metal pitch at 20nm planar, with the requisite double patterning lithography. Both TSMC and GF will be maintaining a 64nm DPT metal pitch with their 16/14nm offerings. To read more about DPT see the Double Patterning Exposed articles from Mentor Graphics. They know DPT, believe it.

So, Intel pursued FinFET’s as a top priority, rather than DPT, keeping 22nm costs and risk down. TSMC and GF went DPT first at 20nm with thinner metals on a 64nm pitch and will add FinFETs as a “half” node one year later. A metal pitch of 64nm will be common between Intel, TSMC, and GF at 16/14nm. Both approaches accomplish the same objective but one may turn out to be more time/cost efficient than the other, time will tell.

It will be interesting to see what happens next year. Will Intel’s Haswell hit full production in 2014? What about Altera 14nmm FPGAs? And the SoC version of the Haswell? Delays are common place on bleeding edge semiconductor technology. Some companies own up to being human, some do not, but silicon does not lie.

The semiconductor industry is so close knit it is very hard to keep a secret. Add in social media and it is near impossible. I personally have 16,272 Connections on LinkedIn, linking me to 18,582,711+ professionals. I don’t know everything semiconductor but I certainly know someone who knows. I will keep working on verifying this rumor so stay tuned to SemiWiki.

Also Read: Intel Really is Delaying 14nm….

Posted on

Xilinx picks another winner…

Xilinx picks another winner…
by Luke Miller on 07-31-2013 at 7:00 pm
Categories: FPGA, Xilinx

Just as important as block RAMs, IO and DSP48’s is what interconnect or fabric is going to be used when considering SoC FPGA designs. I think Xilinx has found the winning combination. What is paramount to the new SoC FPGA methodologies is not only the challenge of moving huge amounts of data around; we are now to consider data movement to/from ARM processors and its external memories like within the Xilinx Zynq series FPGAs.

Traditionally FPGA architects really do not want to use standard interfaces within the internal FPGA design. They just register or buffer data and move it to the next processing block in the design. But SoC designs, for the sake of design time, simplicity, integration and reuse will require a standard bus interface. Xilinx has chosen what I believe is a stellar path for bridging the data path gap of external memories like DDR, Programmable Logic within the FPGA and ARM processors. Advanced eXtensible Interface (AXI) Interconnect comes to the rescue. We simply just cannot hack together or write spaghetti code no longer. Did I say we? I meant me.

A great example of the AXI bus in use is in the Xilinx white paper XAPP792 “Designing High-Performance Video Systems with the Zynq-7000 All Programmable SoC”. By all means give this paper a read and you will see as in many of the Xilinx white papers they have done much work for the designer already, including very fine reference designs. AXI is very flexible in which Xilinx has an AXI lite variant which is easy on the resource usage and the streaming AXI core which is perfect for high speed real time applications such as streaming video and even RADAR. Since you are designing modules with AXI interfaces, reusable libraries can be developed. The crossbar functionality is where the AXI bus is the winner, think of it as a backplane fabric within a chip and it points to the future of silicon system interoperability ; Network On a Chip (NoC) , that is moving data to anywhere without a huge latency penalty.

Looking into XPP792, Xilinx has designed an ARM+PL (programmable logic)+AXI video framework (for free). We often take for granted what can be done in FPGAs and the mass amounts of free knowledge out there. Think back how long this video application would have taken to design back in the Virtex4/5 days. Probably many months for the seasoned FPGA designer. As FPGAs increase in density and SoC is the reality, standard interfaces are no longer an option but a must, and once again Xilinx has picked a winner with its partnership with ARM and it’s AXI bus.

lang: en_US

Posted on

Scan the horizon, P1687 takes us higher

Scan the horizon, P1687 takes us higher
by Don Dingee on 07-31-2013 at 6:00 pm
Categories: EDA, Siemens EDA

The tech standards cycle almost always goes like this: Problems or limits develop with the existing way of doing things. Innovators attempt to engineer solutions, usually many of them. Chaos ensues when customers figure out nothing new works with anything else. Competitors sit down and agree on a specification where things work together, then head off to re-implement.

Continue reading “Scan the horizon, P1687 takes us higher”

Posted on

Pre-verified, Integrated Sensor IP Subsystem?

Pre-verified, Integrated Sensor IP Subsystem?
by Eric Esteve on 07-31-2013 at 11:16 am
Categories: IP, Synopsys

Last year, I said that the launch of ARC based complete sound system IP by Synopsys ring the bell for the opening of a new IP market segment, the “Subsystem IP”. This week, Synopsys has announced the availability of the DesignWare® Sensor IP Subsystem, a complete and integrated hardware and software solution for sensor control applications. This announcement is a step beyond the sound system IP, as we are talking now about a subsystem IP able to process data from multiple sensors, can be digital and analog, using Host Accelerators on top of ARC EM4 microcontroller, and generate a single output, accessible from the main SoC CPU via the host interface. If we look at the Total Addressable Market for sensors, the figures looks incredible, as in 2017 there will be 30 Billion sensors shipped, or about four per single human being!

Fig. 1: Sensor Units Shipments 2009-2017 (Semico)

In fact, part of this TAM will be addressed by Standard IC sensor, and semiconductor suppliers like STM have already heavily invested into such product lines. But it is clear that, when OEM will need to lower the BOM cost, and reduce the number of chips in the system, or (and) reduce the overall system power consumption, integrating such a sensor subsystem into a larger SoC, like an Application Processor or a companion chip for smartphone, will be a must. The fully configurable subsystem consists of a DesignWare ARC[SUP]®[/SUP]EM4 32-bit processor, digital interfaces, analog-to-digital data converters (ADCs), hardware accelerators, a comprehensive software library of DSP functions and software I/O drivers.

Synopsys claim incredibly high gain, both in term of power and area. Like, for example, implementations as small as 0.01mm[SUP]2[/SUP], consuming less than 4uW/MHZ in a 28-nm process! I have mentioned wireless applications, in fact we can see from the Sensor Shipment forecast on figure 1 that this subsystem IP sensor may be used in many other segments: Consumer, Automotive, Computing or Industrial. This is illustrated by the quote from Robert Fortin, director of sensors business unit at Allegro Microsystems, LLC: “As the technology leader in magnetic sensor ICs for the automotive market, it is critical that Allegro acquires high-quality IP from a trusted provider such as Synopsys”. “Based on our experience, the DesignWare ARC 32-bit processor’s combination of high performance, small area and low power provides key advantages for sensor design over alternative solutions.”

Fig. 2: Integrated Sensor IP Subsystem

Considering the massive trend to system integration onto a single, or a couple of chips, delivering an hardware solution like a “LEGO” kit solution is not anymore sufficient. This solution need to be pre-verified, the design team integrating the hardware having to verify only the connectivity inside the SoC. As well, the software should be delivered, and be pre-verified too, and S/W DSP libraries be part of the delivery kit. To be successful, such a subsystem IP has to be highly configurable, the dedicated hardware and peripherals being tightly integrated (by the supplier, not the design team), in order to maximize both the sensor processing efficiency, and the SoC development time, that is the Time To Market. Because this solution tend to be really complete, extensive library of off-the-shelf software DSP functions, including mathematical, filtering, matrix/vector and decimation/interpolation, speeds application software development .

Let John Koeter, vice president of marketing for IP and systems at Synopsys, give the conclusion: “The industry is seeing significant proliferation of sensor-enabled devices in homes, cars and on-the-go. These devices require integrated sensor SoCs that deliver high performance, small area and low power consumption. Synopsys’ pre-verified, SoC-ready sensor subsystem provides designers with a higher level of hardware and software IP integration, enabling them to achieve their design goals faster and with significantly less risk.”

By Eric Esteve

lang: en_US

Posted on

IP: Make or Buy?

IP: Make or Buy?
by Paul McLellan on 07-30-2013 at 2:02 pm
Categories: Arasan, IP

A couple of weekends ago I moderated a panel session for the Chinese American Semiconductor Professional Association. No, I had no idea such an organization existed either (at least partially because I’m not Chinese). Dan Nenni was meant to be doing it but he went off to Las Vegas, so I ended up getting the job. On a Saturday no less. It was on the topic of IP: Make or Buy, Ingredients for Success in System-on-Chip.

The panel was a good mix of people from different slots in the IP ecosystem:

  • Yonghua Song of Marvell (a user of IP)
  • Andy Haines of Arasan (a supplier of IP)
  • Will Chen of Finnegan, Henderson, Farabow, Garrett & Dunner (a lawyer mostly concerned with patent issues in semiconductor IP)
  • Yi-Hung Chee of Intel (mostly a company that develops most of its own IP)

Since I was moderating the session I couldn’t really take notes so I’ll focus on Andy Haines’s position since it was actually a reasonably good summary of the industry. Funnily enough I first met Andy when I interviewed at VLSI Technology since he was the EDA marketing guy, so that is a long time ago (and different hair color for us both).

He is focused on the mobile space and the overall trend, although clearly nothing absolute, is for people to buy more IP and build less themselves. Companies that are early adopters of each new process node, such as Qualcomm, build more of their own IP and license less, at least partially because at the point they need the IP it hasn’t been developed or reached a point of maturity that they are confident using it.


However, the real action in smartphones, despite all the press excitement, is not so much at the high end which is a mature market largely in replacement mode. Instead it is in the mid and low range of smartphones where future growth is expected to be strongest. Processor vendors are targeting less power-hungry powerful cores at this market, which has smaller screens and lower computational requirements. However, the peripheral interfaces are pretty much the same (maybe fewer of them in any given phone). Flash is a standard. USB is a standard. DDRx are standards. There are different versions of the standards but you can’t just take a standard and change the performance and the power in any arbitrary way just because the market in India (say) can make do with slower USB.

In fact these standards are not very standard in the sense that they are changing fast. This fact, on its own, makes the challenge of keeping internally developed IP up to date. You can’t just use it again on next year’s chip since some new wrinkles have been added to the standard, but backward compatibility to all the old devices remains important.

But everyone who is not trying to get into 20nm the moment it opens for HVM faces the key question:Why would you build your own IP if there is a good solution available for purchase?

IP these days is not just the RTL or layout that you need. On its own that is not too useful. There is Verification IP (VIP). There are hardware validation platforms. There are device drivers and software stacks. There are not just digital controllers but analog PHYs that interface to signals coming from the world outside the SoC. Plus there is the commitment that as the standards evolve this whole portfolio of views of the IP will evolve and keep up.

All of this means that the answer to the key question is pretty much that you buy IP if you can, and build it if you can’t, either because it is something specific to your own company or process (if you are Intel for example) or because you need the IP faster than the IP industry can deliver it.

Foundries are engaging earlier and earlier with IP suppliers to make sure that even on the most advanced processes, IP is available when the process is ready, and has already been silicon tested in early shuttles before volume production starts. TSMC’s OIP is the most obvious example (this involves EDA flows too, but this was an IP panel).

If IP is not ready in time for the foundry, the most leading edge companies may design their own. But everyone else will just have to wait. It is not simple to design (say) a DDR controller and its PHY and most design teams don’t have the expertise in house even if they wanted to take the make as opposed to the buy route.

So the trend in IP is clear. More is (and is going to be) purchased and less is going to be done in house.

CASPA website is here.