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What Mentor Said at ITC

What Mentor Said at ITC
by Beth Martin on 09-26-2013 at 4:47 pm
Categories: EDA

At the ITC test conference in early September, Mentor made three announcements. ITC is a big event for Mentor’s test group, and where they usually roll out their new tools and capabilities. The indefatigable Steve Pateras was captured on film describing them.

I’ve summarize Mentor’s three announcements and added links to resources.

Hybrid compression ATPG/LBIST, which is useful for testing high-reliability and safety-critical ICs, for instance in automotive and medical areas. This is a newer technology that re-uses the same scan, clocking, and other test logic to apply both deterministic and random test patterns. See the new whitepaper“Improve Logic Test with a Hybrid ATPG/BIST Solution” (requires registration). They announcedthat Renesas adopted Mentor’s hybrid TK/LBIST solution to satisfy the in-system test requirements mandated by the ISO 26262 automotive quality standard.

An IJTAG (P1687) ecosystem. IJTAG is the spiffy new standard for control and test of IP, which is billed as a real plug-n-play IP integration standard. Last year, Mentor announced their Tessent IJTAG tool that automates the support of the standard. See the Tessent IJTAG datasheetand a whitepaper, “Automated Test Creation for Mixed Signal IP using IJTAG.” The announcementwas that that they worked with Asset Intertech to ensure interoperability between Tessent IJTAG and Asset’s ScanWorks IJTAG solution, allowing engineers to access the operational and diagnostic features of all IP blocks in the design from a top-level interface. This greatly simplifies the job of integrating the hundreds of IP blocks in a typical system, and represents a large step towards creating an IJTAG ecosystem between EDA, IP providers and hardward/software debug tools.


The transistor-level ATPG that they call Cell-Aware test has lots of published industry data showing improved test quality for very-low DPM applications, including automotive, medical, aerospace…really anyone who wants fewer failing devices making it to the field. They have a great web seminar on Cell-Aware test (registration required), and a Cell-Aware Test datasheet. Their announcement is that Open-Silicon is using Cell-Aware test meet demand for very low DPM by detecting defects within cells.

More articles by Beth Martin…

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The US Executive Forum 2013

The US Executive Forum 2013
by Daniel Nenni on 09-26-2013 at 10:00 am
Categories: Global Semiconductor Alliance, Semiconductor Services

The US Executive Forum hosted by the Global Semiconductor Alliance was held last night at the beautiful Rosewood Sand Hill Hotel in Menlo Park. We all have memorable events in our professional lives and this is one of mine, absolutely. The audience was filled with semiconductor executives from around the world who chatted freely at lunch and during the breaks. At the end of the night my pocket was filled with business cards and my mind was filled with friendly faces to remember. I may forget names but never a face.

When I first started writing I jokingly said I blogged for food. After that the lunch offers and forum invitations poured in. At last count I have attended 23 events this year and I still have many more on my calendar. Engaging with the fabless semiconductor ecosystem face to face is everything. It’s what you know AND who you know, absolutely. My business model is different on this event however. If you want to know the details you have to buy me lunch.

Dr. Rice shared her views on technology, the global economy, and conflicts around the world. Dr. Rice also reminded us of something that we should never forget: America is the only country that you can immigrate to and become an American. You can’t immigrate to Japan and become Japanese or Germany and become German, right? This is definitely something to be proud of and something to protect.

The most memorable session was the panel moderated by Aart de Geus with the CEO’s of Altera, Micron, and Marvell plus the President and CSO of Samsung.

This Panel Discussion will spotlight CEOs from leading semiconductor companies as they discuss amongst other things, the toughest challenges facing our industry today and what reforms can be made to address those challenges.

And indeed it did. I wrote a blog a while back suggesting that Aart run for Governor and I stand by that. This panel was one of the best I have seen. Again, buy me lunch and I will discuss it in detail but let me just say this…. WOW! Aart asked some very compelling questions and did not accept non-answers. I was front row center and the audience Q&A was also a WOW!

To give credit where credit is due, the GSA really hit this one out of the park. If you are not already engaged with the GSA here is how you can get started. In addition to the corporate website, you can follow the GSA on LinkedInHERE. Better yet, you can join one of the LinkedIn groups and engage GSA members directly:

These groups are moderated and populated by industry professionals. Ask questions and you will get answers. Also check their calendar of events HERE, a YouTube channel with clips from past events HERE, and the GSA landing page on SemiWiki HERE with expert coverage by Dr. Paul McLellan and myself.

The Global Semiconductor Alliance (GSA) mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe. www.gsaglobal.org

lang: en_US

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Dan Niles: Tapering and the Global Economy

Dan Niles: Tapering and the Global Economy
by Paul McLellan on 09-25-2013 at 5:21 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

Yesterday was Dan Niles quarterly review that he does for GSA. As always he starts from the big picture of the world economy and works his way to a semiconductor forecast. The focus of this quarter was whether the world economy is strong enough for the US to “taper” and reduce the amount of quantitative easing (aka flooding the US market with liquidity).

The US economy is in OK shape, not great. Unemployment is still high. Household wealth is improving, but it is very unevenly distributed. The stock market is up 150% and housing is up a lot from the bottom. But only relatively well off people have those assets and what everyone else needs is jobs. Given the amount of stimulus, GDP growth at 1.4% is pretty anemic.

The other big challenge is that for 30 years we have lived in an environment where interest rates only went down. It is a forgiving environment since any over-borrowing can at least be refinanced after a few years at a lower rate. We are not in that environment any more, and in fact interest rates have gone up about 1% in the last few months. The 10-year bond is now 2.7%, it was below 2% earlier in the year.

The zero interest rate policies in US, Europe and Japan have driven money into other markets with higher interest rates such as China and India. Unwinding the stimulus will pull this money back out again. These markets are in poor shape. For example, India has a falling currency, inflation above 10%, in an environment where food makes up over 50% of expenditures. Brazil has had riots driven by 7% inflation, central bank tightening, currency falling, slow growth. Russia has had a 5th consecutive quarter of slowing GDP growth and inflation is at 7%. China is in better shape but it is running a deficit now and has lots of bad debt issues.


So getting to semiconductor. Growth has been anemic to non-existent for the last 3 years tracking poor GDP growth almost everywhere.


Capex in semiconductor has been fairly restrained for the last couple of years which is good since the industry has not build a huge amount of over-capacity. The consolidation in the DRAM has also led to firmer prices.

There is big spending in communications (wireless networks) due to new entrants in some markets, upgrading to new technologies such as LTE. But computing is in horrible shape with inventories way above new orders, and it will contract in double digits this year and next. Even tablets and high-end smartphones are seeing some of the slowdown (sales misses at Apple and Samsung, for example). Automotive is coming back although it is still down from where it ran in the early 2000s, but cars get old and eventually need to be replaced, and new cars have much more electronic content.


Any bright spots? Low end smartphones, especially in China. New gaming consoles (Xbox one, PS4) for the first time in 7 years. Dan reckons semiconductor demand forecasts are high relative to GDP growth, mainly due to unjustified optimism. Automotive, especially in US. Industrial is recovering finally.

The presentation and audio is on the GSA website here.

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Hybrid Memory Cube Shipping

Hybrid Memory Cube Shipping
by Paul McLellan on 09-25-2013 at 4:37 pm
Categories: Foundries

Today Micron announced that it is shipping 2GB Hybrid Memory Cube (HMC) samples. The HMC is actually 5 stacked die connected with through-silicon-vias (TSVs). The bottom die is a logic chip and is actually manufactured for Micron in an IBM 32nm process (and doesn’t have any TSVs). The other 4 die are 4Gb DRAM die manufactured by Micron themselves with TSVs to for vertical communication. The target market is next generation routers and high performance servers which need memory with very high bandwidth and low power. The HMC can deliver 160GB/s of bandwidth at a power saving compared to normal DRAM of up to 70%.

I talked to Mike Black who is technology strategist for Micron. He said that the work started about 6 years ago when they decided to look at advances in technology since they knew they would want to stack die but to do so required mastering not just making TSVs but creating a whole manufacturing chain for thinning the wafers (without breaking them), bonding everything. Plus the decision to do a system architecture with a powerful logic chip, much more powerful than the type of logic that can be built on a DRAM wafer line.

I think that the announcement today is probably somewhat arbitrary since Micron have been shipping HSC to some partners already. Full production is the second half of 2014.

I think the announcement is interesting for two reasons. One is that the HMC is an interesting device in and of itself. The basic interface is not proprietary to Micron and is defined by the HMC Consortium. Besides Micron, Samsung and SK Hynix are contributors (which covers pretty much the whole DRAM market these days) as are Altera, Xilinx and ARM.


But perhaps even more important for those of us that follow the semiconductor industry in general is that this is a comparatively high volume part using TSVs, so one of the first 3D chips. Of course many people know that Xilinx has been shipping very high end FPGAs using a 2.5D approach on a silicon interposer. But this is not a high volume device and has a price point in the tens of thousands of dollars apparently. Micron are not saying what the price point of the HMC is, but it is clearly a performance, power, cost-of-ownership type of sale meaning that it will cost a lot more than just buying the same amount of DRAM in conventional form.

Analysts that follow the 3D chip numbers seem to think that use of TSV is going to grow from 1% to 10% by 2017. Since the semiconductor market is roughly $400B that is $40B in 3D chips. Micron reckon their internal numbers are in line with that, at least for the memory markets where they are involved.

Memory turns out to be an ideal pipe-cleaner for 3D since it has redundancy, error correcting codes (ECC), and in this incarnation has a powerful logic chip that can, for example, reconfigure the memory to cope with an open TSV. Also, DRAM doesn’t have the acute power and thermal issues of, say, microprocessors so an HMC is more tolerant of problems and doesn’t stress every aspect of the technology simultaneously.

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Intel 14nm versus Samsung 14nm

Intel 14nm versus Samsung 14nm
by Daniel Nenni on 09-25-2013 at 4:15 am
Categories: Foundries, Intel Foundry

The legend of Intel being two process nodes ahead of the rest of the industry is quickly coming to an end. To come to terms with this you need to do an apple to apple comparison which is what I will do right here, right now.

First and foremost let’s compare SoC silicon delivery since SoCs are driving the semiconductor industry and will continue to do so for years to come. In regards to microprocessors Intel is a monopoly and I don’t see that changing, ever. For this comparison I will use a smartphone SoC because apparently Intel has not yet figured out how to make an SoC that fits both phones and tablets like the rest of the industry (sarcasm).

In regards to processes, I’m talking about 14nm. Which 14nm process is better technically? I don’t think we will ever get agreement on that so let’s just say that Samsung and Intel will have something equivalent. As you read in Samsung 28nm Beats Intel 22nm, Samsung definitely has the process technology to challenge Intel. In regards to 14nm wafer cost I give that to Samsung hands down. Remember, Samsung is the number one memory maker and they know how to minimize wafer costs. Samsung also has displays, memory, and other products in the smartphone BOM. Additionally, Samsung is the number one smartphone/tablet systems company so they could easily give away 14nm wafers for free and not even notice it in their financials.

According to Intel sources, Morganfield, the first Intel 14nm smartphone SoC, will be delivered in the first half of 2015. According to the semiconductor equipment manufacturers Intel is having problems with variability at 14nm so this could easily slip. Intel did not do double patterning at 22nm so new process steps have been introduced. The more process steps, the more times you touch a wafer, the higher the variability, simple as that. And that is your Intel F.U.D. for today.

According to my trusted sources the top fabless companies are designing to 14nm right now. The 1.0 (production) version of the PDKs (process design kits) are now available and 14nm tape-outs will happen in Q4 2013, which means production silicon in the first half of 2015. Since 14nm is a half node of 20nm I do not see any F.U.D. here. The foundries used the same metal fabric for 20nm and 14nm with double patterning so they have seen and solved the variability issues. 20nm silicon is out now and will be in production the first half of 2014, absolutely.

Why did I use Samsung 14nm instead of TSMC or Globalfoundries? Technically they are equivalent, I just thought I would take less grief since I have been more critical of Samsung since they became a foundry. Personally I favor TSMC and GF as pure-play foundries since they do not compete with customers, or get sued by them. (Oh snap).

Tonight I’m at the GSA Semiconductor Executive Forum featuring Dr. Condoleezza Rice and semiconductor luminaries from around the world. Next Tuesday I will be at the TSMC Open Innovation Ecosystem Forum networking with 1,000+ fabless semiconductor professionals. If you ask the right questions at these events you will get the answers you need to be an “internationally recognized industry expert” like myself. I have also been called an “industry luminary” which has a nice ring to it too. Just don’t call me a “thought leader” because that sounds like some kind of creepy mind control thing. Of course my blogs do sometimes make people sleepy…….. you are getting sleepy….. Okay now quack like a duck.

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Another Major Consolidation in Semiconductor Space!

Another Major Consolidation in Semiconductor Space!
by Pawan Fangaria on 09-25-2013 at 4:00 am
Categories: Foundries


This time it is between the suppliers of semiconductor manufacturing equipments. And they are among the top ranked global peers. Applied Materials Inc., holding the numero uno position in sales of chip manufacturing equipments in 2012, agreed to acquire Tokyo Electron Ltd, the third in that ranking. Gary Dickerson of Applied Materials will be the CEO and Tetsuro Higashi of Tokyo Electron will be the Chairman of the combined entity. Details of the merger which is primarily on stock swap basis can be looked at http://www.bloomberg.com/news/2013-09-24/applied-materials-shares-slip-as-sales-miss-estimates.html

[TABLE] border=”1″
|-
! class=”blocksubhead” style=”width: 63px” ! 2012
Rank
! class=”blocksubhead” style=”width: 63px” ! 2011
Rank
! class=”blocksubhead” style=”width: 300px” ! Company
! class=”blocksubhead” style=”width: 90px” ! 2012 Revenue
! class=”blocksubhead” style=”width: 114px” ! 2012 Market Share (%)
! class=”blocksubhead” style=”width: 90px” ! 2011
Revenue
! class=”blocksubhead” style=”width: 108px” ! 2011-2012
Growth (%)
|-
! class=”blocksubhead” style=”width: 63px” ! 1
! class=”blocksubhead” style=”width: 63px” ! 2
! class=”blocksubhead” style=”width: 300px” ! Applied Materials
! class=”blocksubhead” style=”width: 90px” ! 5,513
! class=”blocksubhead” style=”width: 114px” ! 14.4
! class=”blocksubhead” style=”width: 90px” ! 5,877
! class=”blocksubhead” style=”width: 108px” ! -6.2
|-
! class=”blocksubhead” style=”width: 63px” ! 2
! class=”blocksubhead” style=”width: 63px” ! 1
! class=”blocksubhead” style=”width: 300px” ! ASML
! class=”blocksubhead” style=”width: 90px” ! 4,887
! class=”blocksubhead” style=”width: 114px” ! 12.8
! class=”blocksubhead” style=”width: 90px” ! 6,790
! class=”blocksubhead” style=”width: 108px” ! -28.0
|-
! class=”blocksubhead” style=”width: 63px” ! 3
! class=”blocksubhead” style=”width: 63px” ! 3
! class=”blocksubhead” style=”width: 300px” ! Tokyo Electron
! class=”blocksubhead” style=”width: 90px” ! 4,219
! class=”blocksubhead” style=”width: 114px” ! 11.1
! class=”blocksubhead” style=”width: 90px” ! 5,098
! class=”blocksubhead” style=”width: 108px” ! -17.2
|-
! class=”blocksubhead” style=”width: 63px” ! 4
! class=”blocksubhead” style=”width: 63px” ! 5
! class=”blocksubhead” style=”width: 300px” ! Lam Research
! class=”blocksubhead” style=”width: 90px” ! 2,835
! class=”blocksubhead” style=”width: 114px” ! 7.4
! class=”blocksubhead” style=”width: 90px” ! 2,314
! class=”blocksubhead” style=”width: 108px” ! 22.5
|-
! class=”blocksubhead” style=”width: 63px” ! 5
! class=”blocksubhead” style=”width: 63px” ! 4
! class=”blocksubhead” style=”width: 300px” ! KLA-Tencor
! class=”blocksubhead” style=”width: 90px” ! 2,464
! class=”blocksubhead” style=”width: 114px” ! 6.5
! class=”blocksubhead” style=”width: 90px” ! 2,507
! class=”blocksubhead” style=”width: 108px” ! -1.7
|-
! class=”blocksubhead” style=”width: 63px” ! 6
! class=”blocksubhead” style=”width: 63px” ! 6
! class=”blocksubhead” style=”width: 300px” ! Dainippon Screen
! class=”blocksubhead” style=”width: 90px” ! 1,484
! class=”blocksubhead” style=”width: 114px” ! 3.9
! class=”blocksubhead” style=”width: 90px” ! 1,810
! class=”blocksubhead” style=”width: 108px” ! -18.0
|-
! class=”blocksubhead” style=”width: 63px” ! 7
! class=”blocksubhead” style=”width: 63px” ! 9
! class=”blocksubhead” style=”width: 300px” ! Advantest
! class=”blocksubhead” style=”width: 90px” ! 1,423
! class=”blocksubhead” style=”width: 114px” ! 3.7
! class=”blocksubhead” style=”width: 90px” ! 1,162
! class=”blocksubhead” style=”width: 108px” ! 22.5
|-
! class=”blocksubhead” style=”width: 63px” ! 8
! class=”blocksubhead” style=”width: 63px” ! 11
! class=”blocksubhead” style=”width: 300px” ! Hitachi High-Technologies
! class=”blocksubhead” style=”width: 90px” ! 1,138
! class=”blocksubhead” style=”width: 114px” ! 3.0
! class=”blocksubhead” style=”width: 90px” ! 986
! class=”blocksubhead” style=”width: 108px” ! 15.4
|-
! class=”blocksubhead” style=”width: 63px” ! 9
! class=”blocksubhead” style=”width: 63px” ! 7
! class=”blocksubhead” style=”width: 300px” ! Nikon
! class=”blocksubhead” style=”width: 90px” ! 1,007
! class=”blocksubhead” style=”width: 114px” ! 2.6
! class=”blocksubhead” style=”width: 90px” ! 1,378
! class=”blocksubhead” style=”width: 108px” ! -27.0
|-
! class=”blocksubhead” style=”width: 63px” ! 10
! class=”blocksubhead” style=”width: 63px” ! 8
! class=”blocksubhead” style=”width: 300px” ! ASM International
! class=”blocksubhead” style=”width: 90px” ! 965
! class=”blocksubhead” style=”width: 114px” ! 2.5
! class=”blocksubhead” style=”width: 90px” ! 1,332
! class=”blocksubhead” style=”width: 108px” ! -27.5
|-

As per Gartner data, we can clearly see from the table, growth % was rather negative for both the giants, a burgeoning -17% for Tokyo Electron. As both are struggling, naturally, this merger may help sharing the burden and creation of a bigger giant of about $29B market value. That will leave all the other players in the market far behind. However, it remains to be seen, how the joint entity complements each other to create a larger economic value, thus helping the combined company as well as the macro-economy. Nevertheless, it is a joining of two global forces on opposite hemispheres, which is bound to bring global synergy in semiconductor equipment business.

In recent economic down-turn it has been observed that most of these companies experienced upward cost pressures in developing more sophisticated machines to cater to shrinking technology nodes, and at the same time, reduced outlay from semiconductor manufacturers on spending for production equipments. Also, semiconductor production equipment buyers’ market is more or less consolidated among Intel, TSMC, Samsung and a few in that category. Naturally, that invites mergers to manage cost (by complementing and eliminating overlaps) and increase capital and revenue, provided there is a right fit.

It’s learned that Applied Materials and Tokyo Electron do not have much overlap and after completion of merger, together they can save ~$250M of cost in the first year and ~$500M by third year. However, it must also be noted that there are other competitors in the same space they are in. Also, it remains to be seen whether any antitrust issue arises out of this as this is a merger of major forces which may lead to concentration of economic power? Considering the current economic situation of this business, I guess not.

So, what do we infer from this story? Will there be more mergers in this space? I guess, yes, because others, who are left significantly behind, may need to join in order to provide a healthy competition to this combined entity. Comments welcome!

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SystemVerilog Assertions and Functional Coverage

SystemVerilog Assertions and Functional Coverage
by Daniel Payne on 09-24-2013 at 8:26 pm
Categories: EDA

Ashok Mehtahas designed processors at DEC and Intel, managed ASIC vendor relationships, verified networks SoCs, directed engineers at AMCC, and used SystemVerilog since it’s inception. He recently authored a book: SystemVerilog Assertions and Functional Coverage. The book is available in both hardcover and Kindle formats at Amazon.

Continue reading “SystemVerilog Assertions and Functional Coverage”

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But I Never Have Seen a Synchronizer Failure

But I Never Have Seen a Synchronizer Failure
by Jerry Cox on 09-24-2013 at 8:00 am
Categories: EDA

You may say, “Why should I worry about synchronizer failures when I have never seen one fail in a product?” Perhaps you feel that the dual-rank synchronizer used by many designers makes your design safe. Furthermore, those chips that have occasional unexpected failures never show any forensic evidence of synchronizer failures. Why worry?

There are contemporary cases and have been cases of synchronizer failure over the years. In fact, there have been many more than can be listed because firms designing digital systems are reluctant to call attention to their failures and because the infrequent and evanescent nature of these failures makes them hard to locate and describe. A few cases are listed here. To indicate the time span of these documented cases, let’s look at the first and last.

ARPAnet (1971): The Honeywell DDP 516 was used at a switching node in the original ARPA network, but in early tests it failed randomly and intermittently within hours or days. Persistent efforts to capture the symptoms were unsuccessful. Eventually, Severo Ornstein diagnosed the problem based on his prior experience with metastability. He then remedied it by halving the synchronizer clock rate (effectively doubling the resolution time). Honeywell did not accept this solution so each DDP 516 had to be modified before installation in the original experimental network.

Technion (May 2013): Scientists at the Technion in Israel reported on a case of metastability in a commercial 40nm SoC that failed randomly after fabrication. Normally, there would have been no forensic evidence that metastability was the cause of these failures. However, by use of infrared emission microscopy they identified a spot on the chip that correlated with the failure events in both time and location. The spot contained a synchronizer with a transient hot state that confirmed its role in the failures. Because the system employed coherent clock domains, the synchronizer MTBF was sensitive to the ratio of frequencies used in the two clock domains to be synchronized. The original, unfortunate choice of this ratio led to the failures and a more favorable choice improved the MTBF by two orders of magnitude. For the application at hand, this was an acceptable solution, but it was a highly expensive and time-consuming way to resolve the problem.

Another difficulty in reporting metastability failures is their infrequency. A Poisson process models the failure rate well, as demonstrated by the correlation between simulations and measurements in silicon. Suppose a product has a failure rate such that there is 50% chance that a problem will be detected in tests that that have a 30-day duration. Further, suppose that no failure happened to be detected during that test period. If product life is 10 years and 10,000 times as many products are to be sold as were tested the expected number of failures would be over a million. Many would be benign, but in safety-critical systems some could lead to fatal results. Even if the probability of failure during test is orders of magnitude less than 50%, the multipliers associated with the longer life and greater numbers in service can make the failure risk significant.
These considerations make it clear that physical tests of products after fabrication are necessary, but insufficient. Only simulations of synchronizer performance, best done before fabrication, can verify the lifetime safety of a multi-synchronous system. This conclusion is of increased importance as synchronizer performance becomes increasingly dependent upon process, voltage and temperature conditions and more highly variable within and among chips.

lang: en_US

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Xilinx’s Vivado HLS Will Float Your FPGA

Xilinx’s Vivado HLS Will Float Your FPGA
by Luke Miller on 09-23-2013 at 8:30 pm
Categories: FPGA, Xilinx

Very rarely does the FPGA designer, especially with respect to RADAR, think of the FPGA as a floating point processor. Just to be sure I asked my 6 year old and she agreed. But you know what, the Xilinx FPGAs float. Go try it, order some up and fill up the tub.

Anyways I purpose a duel to the avid VHDL coder. I want you to design me a Sine(x) function in VHDL, you provide X and the output will be the angle in radians. It must have the answer within 32, 150MHz clocks and have single precision floating point. It also needs to be pipelined, thus after the 32 clocks, the data will continually be produced provided there is an input every clock cycle which will keep the pipe full.

So how long would that take you? Well I did this very experiment and used Xilinx’s Vivado HLS and was done in about 10 minutes and that includes my son’s diaper change. I used the Taylor Series expansion out to the 13[SUP]th[/SUP] term. I removed all the factorial divides by using LUT’s to store the 1/3!, 1/5! … terms. What we are left with is the very simple code below:

What’s even grander is I did not have to run like a 100 RTL simulations to verify my design. Why? Because since the input to HLS is C/C++, you are running an executable that completes in a second to verify your math. Think about it, why do you run an RTL simulation for a module you design? You need to verify the math, the latency and boundary conditions. It is in iterative process. So is the HLS tool but you move much faster as the time between code tweaks is much faster in the C/C++ domain than RTL simulation domain. Here is how we did with respect to performance and device usage:

In HLS you’re mainly trading off FPGA device area, clock speed and latency. You no longer have to wait for MAP to complete to see device usage and Fmax. Think of that next time you are sizing FPGAs for your next proposal. The C/C++ you write can be added to a library and reused again and again. Now some of you may be asking, why don’t I just use a SIN(X) function in math.h? Well that works too, and that would only take 10 seconds to design using Xilinx’s Vivado HLS, but the latency will be 48 clocks. We needed to hand code the C function because I needed a pipelined, 32 clock solution. Go download a free trial at Xilinx to play with Vivado HLS today! You won’t regret it…

lang: en_US

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A Brief History of Silvaco

A Brief History of Silvaco
by Daniel Nenni on 09-23-2013 at 5:00 pm
Categories: EDA

Silvaco is the leading supplier of TCAD software, and a major supplier of EDA software for circuit simulation and design of analog, mixed-signal and RF integrated circuits.

The company was founded in 1984 by Dr. Ivan Pesic. The initial product, Utmost, quickly became the industry standard for parameter extraction, device characterization and modeling. It was followed in 1985 by SmartSpice, bringing Silvaco into the SPICE circuit simulation market. SmartSpice was later complimented by a family of circuit simulation products for analog, mixed-signal, and RF.


In 1987 Silvaco entered into the TCAD market and by 1992 had become the dominant TCAD supplier with the Athena process simulator and Atlas device simulator. These would later evolve into a complete family of 2D and 3D process, device and stress simulation products.

In 1997 Silvaco entered the analog IC CAD market with a suite of EDA tools for schematic capture, layout, physical verification (DRC, LVS and LPE) and parasitic extraction. In the same year Silvaco also began offering its tools for 3D physics-based interconnect modeling for passive components and interconnect parasitics.

In 2004, Silvaco entered the digital market, offering tools for cell/core library characterization, place and route, and Verilog simulation.

In 2006 Silvaco began to offer foundry-specific PDKs to enable designers to streamline their design flows all the way to fabrication. This began with the TSMC 0.18um process and has since grown to over ninety PDKs for eighteen foundries, and the number of supported PDKs continues to grow.

In October 2012, after an extensive battle, Dr. Pesic succumbed to cancer. Ownership of Silvaco remains in the Pesic family, with Dr. Pesic’s son, Iliya Pesic, now Chairman of the Board. David Halliday, a veteran with over twenty years of experience at Silvaco, has been appointed interim CEO. The company continues to move forward and is a proactive member of the EDA and TCAD business communities through such industry associations as Si2, SEMATECH, CMC, and GSA.

The company has always been privately held, financially strong, and debt-free, growing steadily on retained earnings to become the largest privately-held EDA company.

In addition to its headquarters in Santa Clara, California, Silvaco maintains US sales and support offices in Boston, Massachusetts, and Austin, Texas. Silvaco also has international sales and support offices in Japan, Korea, Taiwan, Singapore, and the United Kingdom. In addition, Silvaco employs local distributors in China, India and Malaysia.

Silvaco’s broad customer base includes leading foundries, fabless semiconductor companies, integrated device manufacturers, universities, research institutions and IC design houses.

Silvaco’s mission is to remain the leading TCAD supplier while becoming the leading EDA supplier delivering best-in-class tools, complete design tool flows, expert technical support, and professional services.

Silvaco has a proven track record of providing leading edge and innovative solutions and will continue to build on its success having all the attributes required to provide best-in-class tools for the ever more challenging requirements imposed by future generations of semiconductor devices and technologies.

Silvaco is determined to remain independent, financially stable and debt free to enable them to be a long term premier alternative to the ‘old guard’ EDA companies. Silvaco will focus on providing excellent tools and outstanding support to continue to grow its already extensive, established and loyal customer base.