The SoC designs of today are much more complex than ever in terms of number of clocks, IPs, levels of hierarchies, several modes of operations, different types of validations and checks for growing number of constraints at various stages in the design flow. As a semiconductor design evolves through several stages from RTL to layout, the constraints may change. A consistency check on the changing constraints is desired to ascertain the intent to move in the right direction. Again there may be missing constraints or incorrect constraints that must be reported in order to guide the designers to take appropriate action during the design development.

Knowing that Atrentahas a constraint management system in the SpyGlass platform that works from RTL to GDSII, I contacted Manish Goel, R&D Senior Director at Atrenta and to learn more about this system. Manish provided a detailed description about the constraint management system which is integrated into the overall SpyGlass solution framework for faster design closure. Here is the conversation –

Q: Manish, SpyGlass has a good constraint management system. Can you elaborate on its main components?

A: Yes, we have a constraint management system which is tightly integrated with the SpyGlass platform and it checks timing constraints, generates new constraints where required, verifies exceptions and manages all constraints through the complete design cycle from RTL to post-synthesis, pre-layout and post-layout stages. It checks consistency of SDC, exceptions, hierarchical constraints etc. against the design. It also removes any redundancy, identifies missing constraints, and provides guidance for cleaning delay constraints and clock definitions. The missing constraints can be automatically generated by the system. To manage the consistency in constraints, equivalence between different levels of the design and corresponding SDCs is checked. It is possible to analyze multiple modes. The tool can merge the multiple modes into a single mode. And during exception verification, false paths (FP) and multi-cycle-paths (MCP) can be verified formally, as well as based on timing. Also assertions can be generated for additional coverage.

Q: How are the constraints generated automatically? Generally RTL should come with constraints defined?

A: It is not that all constraints are generated afresh. Constraints can come from previously existing IPs or design blocks. The SpyGlass Constraints solution checks for missing constraints in the new design, reports them and generates them. For example, it can detect flip-flops (FF) not driven by any clock and it can generate a clock for them. Similarly, it can identify multiplexed inputs, clock domain crossing (CDC)and generate false path constraints at those crossings. It generates all kind of FPs including synchronous, asynchronous and quasi-static. And then it checks for correctness of all the constraints. SDC is generated incrementally as the design progresses. And that can be done through standard templates available with the initial seed file. The constraints can be identified, created and values added through intelligent wizards that can guide designers to keep the SDC correct by construction.

Q: O.K. when you talk about the constraint management, what do you exactly mean? How is the equivalence checked? How are the modes merged?

A: The constraint management provides maximum efficiency as the design evolves from RTL to layout through synthesis and P&R stages with minimum risk. See the SpyGlass constraints methodologyflow diagram above; it takes an RTL block as input along with the SDC, which can be partial. The existing constraints are checked for their correctness and completeness, the missing constraints are generated and exceptions verified (at all the stages). At this stage, multi-mode analysis is done for coverage check. At the synthesis stage, constraints are checked for synthesis readiness and functional intent is verified to match with the design intent. Also, as the gate netlist is available, the equivalence between the RTL and gate level constraints is checked. Similarly, at the floorplanning and the P&R stage, constraints are checked for STA (Static Timing Analysis) and for P&R readiness. Again, it is important to check that the functional intent matches with the design intent. At the P&R stage multi-mode analysis and merging starts. At the chip integration stage, various levels of SDC equivalence (top level vs. block level, pre-DFT vs. post-DFT, restructured RTL) are checked; there are three flavours – i) same design, changed SDCs; ii) changed designs; changed SDCs; iii) top level, block level, should have impact on timing in the same way. The complete multi-mode analysis, coverage and merging takes place at the chip integration stage. Various aspects such as constraint promotion, clocks converging on a mux etc. are taken into account.

In a typical scenario of SoCs, 70-80 modes of operations can be seen and it can be very taxing on the time to test all the modes. So, at the post-routing stage, the modes are analysed for merging and they are reduced in number. Again equivalence checking is done before and after mode-merging.

Q: How is this system differentiated from the other offerings?

A: As we talked just now, SpyGlass Constraints provides a complete integrated solution which has flexible SDC generation, formal exception verification (without needing test vectors), complete checking of SDC, multi-mode analysis and merging and a comprehensive debug system in place. There are about 300 rules covering all aspects of timing. We have patented the SDC equivalence checking. There is a unique MCP verification engine, formal clock waveform and domain verification, hierarchical methodology to support IPs and large SoCs. There are various options for most of the operations to keep the system flexible; for example, one can validate all modes of constraints in a single run and view reports per mode. This system is in production use with a large customer base since more than 6 years.

Q: How many large designs have been analysed through this system?

A: Many large designs have been taken through the system. A few customers have SDC sizes of the order of 5 to 6 GB with millions of lines of constraints and the design has hundreds of IPs. It’s not possible for designers to manage such large constraints files without the help of automated tools.

Q: Thanks Manish, that’s a great perspective you have given. One last question on the use of an existing SDC – there could be redundant legacy constraints in that, how confident would the SpyGlass Constraints tool be to remove those?

A: The tool does not remove them by itself, but it will provide all clues about the redundancy or obsoleteness of such constraints which can be safely removed. Imagine, a decision the designer finds difficult to make, the tool greatly assists in making that decision. That’s the kind of knowledge power the overall system provides.

I really enjoyed talking to Manish and learning about the intricate details of the SpyGlass Constraints solution. Considering various automated procedures, tools and techniques, flexible operations that the system employs, I can see that it definitely boosts designers’ productivity to a large extent with faster convergence of design – quicker synthesis, faster timing closure at the back-end and other stages.

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