SemiWiki – Page 818 – The Open Forum for Semiconductor Professionals

January 14, 2014August 22, 2024

Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC

Technology Challenges: Intel, IBM, Xilinx, GlobalFoundries, IMEC
by Paul McLellan on 01-14-2014 at 7:00 pm
Categories: ESD Alliance, Foundries, FPGA, GlobalFoundries, Intel Foundry, Semiconductor Services, Xilinx

I spent the day at the SEMI Industry Strategy Symposium in Half Moon Bay. The early part of the day was devoted to technology challenges. Obviously everyone did not say exactly the same things, and had a little bit of a different spin depending on what business they are in. But there was a lot of commonality between Intel, IBM, Xilinx and GlobalFoundries. There were also presentations by the Global450mm Consortium and from Handel Jones of IBS. I will cover what they said in separate blogs later in the week.

Firstly, everyone pretty much agrees that there are no insurmountable technical challenges getting to 7nm. We know how to do it. Or at least we know what we have to do to get there, and it is engineering rather than basic research.

However, everyone agrees there are economic challenges in the sense that the costs of wafers are going up so fast that they overwhelm the savings that we get from increased scaling and as a result the cost per transistor is at best flat or at worse rising. Of course we get lots of other good things from the new process generations, such as reduced power, increased circuit complexity, increased performance. But, as I’ve said many times before, we don’t get a reduction in cost. If you are cost sensitive then 28nm still looks like the best process if you can get away without needing the features that only come from 20nm and below. Many of the speakers expressed confidence that the cost challenges would be addressed and we would get back on the nirvana of Moore’s Law but there was little hard data to back this up.

There was a healthy skepticism about EUV lithography. The source light is currently around 50W and 250W is required for it to be economic to use. Defect density on masks (remember these are actually multi-layer mirrors) is about 100 per mask and needs to be under 10 to make it feasible to take corrective measures.

Everyone agreed that stacking technologies of all kinds that allow us to get into the 3rd dimension will be increasingly important. Memory stacks, organic interposers, glass interposers, silicon interposers, and true 3D SoC (where a whole design is partitioned onto multiple die).

Michael Mayberry of Intel talked about Delivering Complexity to the Leading Edge. His basic premise was that we have to suck up the complexity in order to deliver simple user experiences. For example, a modern process (I think he was talking about 14nm) there are a billion transistors per square centimete (or 100 billion memory bits) and that requires 60 billion features across the design process and, in turn, with the complex RET needed for lithography, that is a trillion mask features across the mask set.

The big challenges are:

granularity (when you can count the atoms everything is granular)
size is limited by electrical behavior
voltage scaling limited by mobility
interconnect limits performance

Bryan Rice of GlobalFoundries talked about The Foundry Answer to Technology, Cost and Moore Scaling. His list of challenges was:

device architectures and scaling: FDSOI, FinFETs, nanowires, III-V materials
litho/EUV: cost, multipattern immersion, EUV power source, tool availability
packaging: normal economics are dead, value proposition moving to PPC, alternatives
450mm: G450 Consortium, driven by immersion initally, EUV later

Ivo Bolsen discussed Programmable Platforms Essential to Leverage Further Logic Scaling. He talked less about process details but did talk a lot about 3D packaging where Xilinx is one of the leaders with a family of interposer-based parts already in production. But his bigger point was that the building blocks need to get bigger and, increasingly systems need to be designed in a hardware/software neutral way and automatically put into the fabric. His bet is OpenCL which allows designs to be compiled into code that runs in the normal software eocsystem (ARM etc) and accelerators that are automatically created in the FPGA fabric to handle the algorithms where power or performance mean that it cannot simply be implemented in software.

An Steegen of IMEC talked about Scalling Beyond 10nm. She ran through so many technologies where IMEC is doing research, some of which I had never heard of such as spin wave devices. But her big point was that there are three types of scaling going on: lithography enabled scaling, materials and device architecture scaling, and 3D enabled scaling.

Jon Casey of IBM focused on big data, System Scaling Technologies and Opportunities for Future IT Workloads and Systems. His big point was that a huge amount of power is dissipated just moving data around. Systems needed to get smaller so that less power was wasted and data could move faster and this means stacking chips, interposers and memory stacks (IBM is partner with Micron on the HMC). This is what he termed volumetric scaling.

So a huge amount of overlap. I’m still not convinced that we have any idea how to get back on the cost curve, or that EUV is going to work. But I’m pretty certain that 2014 and 2015 is going to be the year of 3D.

Things to do in Denver when you’re 64-bit

Things to do in Denver when you’re 64-bit
by Don Dingee on 01-14-2014 at 4:45 pm
Categories: Arm, IP

When Apple announced last September their A7 chip had gone 64-bit, the congregation immediately swooned, but analysts reacted skeptically: “So what? Phones don’t need more memory, and there are no 64-bit apps.” Even pundits miss once in a while, and now the topic is how the chip industry is headed for 64-bit.

Continue reading “Things to do in Denver when you’re 64-bit”

January 14, 2014

Why SOI is the Future Technology of Semiconductor

Why SOI is the Future Technology of Semiconductor
by Eric Esteve on 01-14-2014 at 8:34 am
Categories: FD-SOI, Foundries, STMicroelectronics

No doubt that FDSOI generate high interest these days and I found a very interesting contribution from Zvi Or-Bach, President and CEO of MonolithIC 3D, Inc. Zvi has accepted to share his wrap-up from IEDM, in a blog for Semiwiki readers. If you remember the long discussion we had in Semiwiki about cost comparison, some comments were posted Continue reading “Why SOI is the Future Technology of Semiconductor”

January 13, 2014

Xilinx, the University of FPGA

Xilinx, the University of FPGA
by Luke Miller on 01-13-2014 at 8:00 pm
Categories: FPGA, Xilinx

More than ever, FPGA training is the key to success. Which is why Xilinx, provides free, no charge video’s that can speak to the seasoned FPGA designer or to the interested community. These Videos are not like your high school graduation taped by Uncle Frank. These are detailed, professionally edited Xilinx Videos that will give you an education and a taste for Xilinx FPGAs that you would have thought would eat into expensive training budgets. Something in the engineer’s soul lights up when the word free is spoken!

Do not let me confuse you with the facts, but these videos are to supplement training. But you know as well as I do, in this day in age, training unfortunately is getting fickle. Usually after the coffee club, and water cooler budget, the training budgets are the next in line to be challenged. In the meantime, it is up to you to stay current, which means, even going to a ‘lunch and learn’, I know. The other name for that is you train on your own time. My friend, I therefore would like to point you into this direction, to this valuable link on Xilinx:

Xilinx Free Video Courses

While there is no shortage of Xilinx FPGA hacker videos (you can find me building a 1953 Nixie Tube Speedometer) they do not always have the correct foundation that Xilinx is going to provide. This is obvious but Xilinx as the designer of World Class Programmable Devices is going to have the best and most accurate content. Once you have watched the videos, start poking around for more videos from other sources and then learn the tricks of the trade after the foundation is laid.

So I suggest, Mr. Dad or Mrs. Mom, Grab the family and it’s time for family movie night! What engineer would not want to share this time with his or her family? The kids are always asking, ‘What do you do at work?’ We’ll now’s your chance to wow them! OK, this is a bit of fiction, but may I recommend some of my favorite Videos from the Xilinx Video Library, and they are… Wait, know what would really be cool, is if Xilinx used its own technology to stream and compress these videos and then up covert the stream to a 4k display. Anyways the video list, drum roll…

The heart of most Xilinx FPGA Designs, the DSP and how to get your design done and signed off faster than ever!
Accelerating DSP design productivity with Xilinx

Ever wonder how Xilinx FPGAs support the automotive industry? This is an Oscar Contender.
Automotive market segment overview

Zynq, is nothing short of a huge success. This video answers the following question:
Why Zynq?

This short video highlights the overall challenges faced by the industry and how traditional solutions are addressing them, and why a new category of devices such as Zynq is needed. It will also briefly review the overall Zynq-7000 platform offering and the values that these devices bring to designers.

In the time to come we can expect videos featuring 20nm UltraScale and then 16nm. Go make your popcorn, extra butter and get ready!

Special Interest Group for HSPICE at DesignCon in Two Weeks

Special Interest Group for HSPICE at DesignCon in Two Weeks
by Daniel Payne on 01-13-2014 at 8:00 pm
Categories: EDA, Synopsys

DesignCon brings together engineers from around the world that are interested in IC design, package design and board design, plus the signal integrity issues of creating high-speed systems. In just two weeks there’s a Special Interest Group(SIG) just for users of HSPICE in their tool flow, and it meets for three hours during dinner in the evening from 6PM to 9PM on Tuesday, January 28th. I’ve blogged about this event in past years:

2013 – Modeling TSV, IBIS-AMI and SERDES with HSPICE
2012 – HSPICE Users Talking about Their Circuit Simulation Experience
2012 – ” “, Part 2
2011 – DesgnCon 2011 Trip Reports

The SPICE world moves quickly, so Synopsys is busy adding new features and improvements each year, plus at this SIG you get to hear from real users of HSPICE, not the marketing droids. There are 13 EDA partners that create tools that use HSPICE for analysis, and you can stop by and chat with their AEs to find out how the integrations work.

Topics

You can expect to see at least four presentations covering topics like:

Signal integrity analysis
Power integrity analysis
Designing multi-gigabit serial links
New HSPICE features and improvements

You can even approach an HSPICE developer or manager and nag them about adding your favorite new feature. There’s nothing like a direct request to get engineering thinking about what’s important to add in the next release.

Registration

You need to register for this event online here. If you cannot make it to DesignCon this year, then stay tuned because I’ll have a link to a video recording of the HPSICE SIG and blog about it. Stay until the very end of the presentations and get a chance to win a prize, typically something cool like a tablet.

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January 13, 2014

MakerSpace at CES, Atmel inside

MakerSpace at CES, Atmel inside
by Paul McLellan on 01-13-2014 at 4:12 pm
Categories: Foundries

The DIY Maker Movement has been using Atmel-powered 3D printers like MakerBot and RepRap for some time now. However, 3D printing has clearly entered a new and important stage in a number of spaces including the medical sphere, architectural arena and science lab. 3D printing is now at that crossover point where it is going from being something primarily driven by hobbyists to true commercial manufacturing. The 3D printing industry is on track to be worth a stunning $3B by 2016. It reminds me of the state of the PC industry in the mid 1970s when it was switching from hobbyists (Apple I) to real computers doing real work (Apple II, driven largely by VisiCalc, the first spreadsheet). Just recently I read about a 3D printer being used to make prosthetic hands and other such parts, real work for sure.

At CES this year, Atmel had various technology zones. The MakerSpace in particular attracted a lot of attention with Arduino boards, 3D printers and other Atmel-powered devices. This just goes to illustrate how mainstream the Maker Movement has become. Atmel has typically focused on the microcontrollers and components inside many consumer devices, a role that puts them squarely in CES territory. They also provide the processor inside most Arduino boards, connecting them closely with the world of making. Atmel is staying firmly connected to Makers.

As Salvador Rodriguez of the LA times said:“While the Internet gave users the ability to have instant access to information, 3D printers will give users the ability to instantly create objects. In the future, users may be able to print shoes that are tailored to the exact size of their feet, among many possibilities. They may also be able to buy products directly from online retailers and print them out immediately, rather than wait for the item to ship.”

The capability to manufacture complex parts in comparatively low volumes means that entrepreneurs can do more than build software/web companies but can make physical things. The cost of creating prototypes using 3D printing technology lowers the barrier a lot, and even low volume manufacturing is scalable. The cost of getting a product into high volume manufacturing can be postponed until it is a sure-fire success. It is not even necessary to own all the technology in-house. Boutique manufacturing operations have come into existence across the U.S. and Asia that offer low-cost options for building small batches of new products.

This is echoed by MakerBot CEO Bre Pettis:“If you had an idea and wanted to get it out into the world, you used have to be a tycoon in an industry. Now you just need an idea and the willingness to fail until it works.”

See Atmel’s video diary at CES here.

GSA Silicon Summit

GSA Silicon Summit
by Paul McLellan on 01-13-2014 at 2:50 pm
Categories: Global Semiconductor Alliance, Semiconductor Services

Every year the GSA holds the GSA Silicon Summit. This year it is on April 10th at the Computer History Museum. It runs from 9am until 2.15pm. This year the focus is mostly on technologies other than simply scaling semiconductor technology. The meeting is divided into 3 sessions, each of which starts with a presentation and then is followed by a panel session. The participants are still being finalized but the topics can be announced.

The first session is on Implications of Nanoscale Manufacturing. Joe Sawicki of Mentor will moderate. The session will open with an overview detailing the challenges of continued gate scaling, as well as the industry’s exploration of alternative materials and processes in the fabrication of nanoscale structures and the resulting applications that may be enabled. A panel discussion will follow to address some of the challenges involved in implementing alternative CMOS solutions as well as recent advancements made in nanoscale engineering.

The second session is on Innovation in a Heterogeneous Integration Era. The session will open with an overview on how manufacturing and packaging innovation driven by heterogeneous integration is fueling new opportunities and helping manufacturers propel such visions as the IoT and Sensory Swarms. A panel discussion will follow and explore the current and future advances of integrating digital, RF, analog/mixed-signal, memory and sensors in close proximity to achieve increased performance from a scaling, material and process perspective.

The Internet of Things (IoT) is one of those terms that means different things to different people, but given that the devices are likely to be extremely low power, low cost and contain a selection of sensors, it is clear that this is very different from the smartphone business. The integration is likely to be using innovative packaging rather than simply doing everything at 16nm.

The third session is on Enabling a 2.5D Ecosystem. Holding great promise for enabling heterogeneous integration and reducing design complexity, this session will provide an overview on where the industry stands in terms of developing and commercializing 2.5D technology and what remains to be done. A panel discussion will follow and address the use case for utilizing 2.5D technology, as well as the business needs within the supply chain in order to ignite 2.5D adoption and market growth, changing it if possible, from a nascent alternative to a mature option.

I think 2014 will turn out to be the year that 3D chips become real, at least in two forms: stacked memory and 2.5D interposer-based designs. At the end of last year Micron announced that the Hybrid Memory Cube will ship in production volumes this year, and Xilinx announced a family of FPGAs that are manufactured using interposer technology. Talking to EDA companies, there are obviously several other pilot programs at their customers. The general feeling at the 3D conference in Burlingame in December was that once these sorts of products ship in volume so that several million units have been manufactured, then the costs will come down a lot and this form of integration will become very attractive.

How to Develop Accurate Yet High Performance Models

How to Develop Accurate Yet High Performance Models
by Pawan Fangaria on 01-13-2014 at 12:00 pm
Categories: Arm, EDA

In today’s environment of semiconductor design, SoCs are crammed with various IPs with multiple functionalities and processors integrated together. In such an event it has become necessary to model the system and verify on Virtual Platform before getting into actual design and fabrication. And that requires modelling of each block at the required level of abstraction. Even to re-use an IP or existing design block needs its modelling in the context of the new design in which it is to be used.

Ideally, it may be desired that a model should be fast enough (as software run) at the Programmers View (PV) level modelled at LT (Loosely Timed) or UT (Untimed) level of abstraction. However, as we move towards actual hardware of the system, timing accuracy sets in, ultimately leading to CA (Cycle Accurate)level of abstraction which decreases the performance by orders of magnitude compared to that of programmers view. In practical situations we need both types of models depending on the accuracy level required for particular blocks. AT (Approximately Timed) models are less prevalent because they are neither 100% accurate nor as fast as LT models and require considerable cost of development and maintenance. In comparison, LT models can be easily developed by mapping functionality into software and CA models can be easily translated from RTL implementation.

Now the real question is how to get the best out of both ends of spectrum, LT and CA? CA models will slow down LT models, hence limiting the overall speed of the Virtual Prototype. But there is a way out; I am delighted to see this novel approach developed by Carbonand ARM where they exploit the accuracy of CA and speed of PV models and enable them to complement each other as required by the system in Virtual Prototype.

[PV and CA Integrated Platform]

In the above arrangement, it’s very convenient for a designer to execute the system in LT mode up to a point (such as booting of an OS) and then change to CA mode for tasks which require more accuracy. This requires each model to have some check point (CP) facility which can be utilized to do the swap between LT and CA mode of execution. ARM Fast Model system provides Cycle Accurate Debug Interface (CADI) and ARM ESL APIs which can be used to create such CPs. Any type of model can use ARM ESL APIs to make this kind of swapping possible at the CP. Since there are differences in execution of LT and CA models, testing of the swap functionality can only be done by creating multiple random CPs and continuing the program execution from these CPs until the program completion and looking at the end result.

[Partitioning the platform between LT and CA for speed and accuracy]

Above is an example of the PV and CA integrated platform in which ARM Mali[SUP]TM[/SUP] GPUwas Carbonized (by using Carbon Model Studio) and linked together an ARM Fast Model representation of the system. Variations of this exact setup have been deployed at multiple semiconductor design houses. The processor/memory subsystem is sufficient to boot the Linux OS and get to a prompt within 15-20 seconds irrespective of GPU being present or not. The speed goes down when CA model becomes active in processing graphics frames, each frame taking approximately 90 seconds. On the other hand, the hardware prototype, although was much quicker in frame processing, took about 15 minutes to boot Linux, i.e. by the time Linux was booted, the Virtual Prototype had already processed about 10 frames.

[Applying check points (CPs) in swap enabled platform]

A swap-enabled LT system runs like any other Virtual Prototype, however it can be changed to 100% CA at any point of interest. Typically software breakpoints are chosen, such as start of various driver codes inside the OS kernel as shown in the above picture. A single Fast Model run can create multiple CPs, which can then be simulated and debugged (with detailed hardware and software interactions in 100% accurate environment) independently in parallel by different personnel. The results from these runs can be used to analyse performance, power etc.

Swap capability from ARM Fast Models to Carbonized ARM models is in existence and active use at numerous design companies. The functionality is readily available for ARM Cortex-A15, Cortex-A9 and Cortex-A7 processors along with their peripheral models.

It’s a great innovative approach to optimize virtual prototyping with a single virtual prototype debugging software at fast speed and at the same time having capability to execute at 100% accuracy, as required for architectural exploration, firmware development and system debug. Bill Neifert, CTO, Founder at Carbon Design Systems and Rob Kaye, Technical Specialist at ARM has described this process in great detail along with some more future work in their whitepaper posted at Carbon website. It’s a great read for system designers and IP developers.

Migrating SOCs from 8051 to 32-bits

Migrating SOCs from 8051 to 32-bits
by Daniel Nenni on 01-12-2014 at 10:00 pm
Categories: Andes Technology, IP

The 8051 processor has been widely used in many embedded applications over the past 30 years. While the 8051 core is small and simple-to-use, the newest generation of consumer electronics being developed today often require more than the 8051 MCU can reasonably deliver. New SOC applications such as flash drives, power management chips, sensors controllers, IoT devices, and many others can benefit significantly from a more capable processor. The newest embedded applications are demanding more performance, significantly less power consumption, more programmability, and more numeric precision than the legacy 8051 is able to provide.

Webinar:
Migrating-SOCs-from-8051-to-32-bits
Wed, Jan 22, 2014 10:00 AM – 11:00 AM PST

Estimated Length:
40 Minutes + 10 Minutes Q&A

Who Should Attend:
SoC and ASIC architects, designers, and managers who are developing embedded MCU-based systems and are interested in improving performance, reducing power consumption, and reducing costs.

Attendees Will Learn:

The tradeoffs of different embedded MCU IP cores
The performance and power bottlenecks for MCU-based systems
Andes FlashFetch and secure MCU design technologies
The complete embedded MCU design solution from Andes.

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| align=”left” valign=”top” style=”background-color: #ddebd6; padding: 7px; font-family: Arial,Helvetica,sans-serif; font-size: 12px; color: #5a5a5a” | Presenter: Dr. Emerson Hsiao
Director, Field Application Engineering
Dr. Hsiao has an extensive background in the ASIC and IP industry. Prior to Andes, he worked at Kilopass Technology as the VP of Marketing. Dr. Hsiao previously held the General Manager position for Faraday Technology USA, where he spent several years in field application in various locations including Taiwan, Japan and USA. Dr. Hsiao worked at UC Santa Barbara as a visiting scholar prior to Faraday. He received his Ph.D in Electrical Engineering from National Taiwan University.
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| align=”left” valign=”top” style=”background-color: #ddebd6; padding: 7px; font-family: Arial,Helvetica,sans-serif; font-size: 12px; color: #5a5a5a” | Moderator:Dan Ganousis
North America Business Development
Dan is a veteran of the EDA and semiconductor IP industries having served as an executive at Mentor Graphics, VeriBest, Viewlogic, Innoveda, Arithmatica, Forte Design, Cyclos Semiconductor, and most recently Oasys Design. Dan spent the first 15 years of his career designing microprocessors and ASICs at Zilog, NCR, DEC, and Solbourne Computer. Dan currently is a consultant for Andes Technology USA assisting in business development in North America. Dan received his B.S. in Electrical Engineering from Rensselaer Polytechnic Institute in Troy, NY.
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After registering, you will receive a confirmation email containing information about joining the webinar.

lang: en_US

Andes Technology, one of EE Times’ Silicon 60: Hot Startups to Watch, has introduced a new embedded MCU product line to tackle these new design requirements. In this webinar, we will discuss many of the bottlenecks that designers will face for increasing performance and reducing power consumption in a typical 8051-based system – and about 32-bit alternatives. A novel low-power solution will be introduced using AndesFlashFetch™ technology. A secure MCU system for embedded code protection will also be described. Attendees will learn how to use the complete Andes embedded MCU ecosystem including a graphical IDE, rich operating system and application software stack, easy-to-use debugging tools, and convenient in-circuit evaluation platforms.

January 12, 2014

Sidense Beats Kilopass in Court Again!

Sidense Beats Kilopass in Court Again!
by Daniel Nenni on 01-12-2014 at 12:00 am
Categories: IP, Sidense

The technology headlines in 2013 were often stolen by frivolous legal actions that made little or no sense to me at all. Patent Trolling is at an all-time high inside the fabless semiconductor ecosystem and as a result litigation reform is coming to Silicon Valley, believe it.

Currently working its way through the legislative process is the Innovation Act (H.R. 3309), the major provisions of this bill are:

Require specificity in patent lawsuits
Make patent ownership more transparent
Make losing plaintiffs pay legal fees
Delay discovery to control costs
Protect end users of the products in question

Not so coincidentally the U.S. Court of Appeals for the Federal Circuit in Washington ordered a judge to analyze whether Kilopass Technology Inc. should pay legal fees incurred by Sidense Corp.

“Too many patent owners are bringing claims that are meritless and then settling for a nuisance value with the expectation their claims would never be tested,” said Edward Reines, a lawyer with Weil, Gotshal & Manges LLP in Redwood Shores, California, who also teaches at Stanford Law School. “The intrepid defendant who fights and wins ends up not being compensated for their fees.”

As the story goes, in May of 2010 Kilopass took legal action against Sidense Corp for infringement of Kilopass’ 1T antifuse technology. Kilopass and Sidense design programmable non-volatile memory (NVM). The patent in question describes two “doped semiconductor regions” that define a channel. The comparable Sidense NVM employs a single doped semiconductor with a shallow trench isolation insulator. In April 2013 the case was resolved by judgment of non-infringement on Kilopass’ patent claims and its dismissal, with prejudice, of all remaining claims against Sidense.

Unfortunately, during the case it was discovered that Kilopass was advised against legal action stating that Sidense had redesigned the memory cells in question but they filed anyway. Three years and millions of dollars in legal fees later (money that could have been used for research and development) the lawyers will continue to argue and generate even more billable hours determining if Kilopass should pay legal costs and how much that will be.

It said the court must consider “whether Kilopass acted in bad faith in light of the totality of the circumstances” even if there’s no specific evidence of wrongdoing, Circuit Judge Kathleen O’Malley wrote.

Federal appeals court: ‘Patent trolls’ should foot legal …
Patent Suit Losers Should Pay Legal Costs More Often, Court Says

The press had a field day with this which suggests to me that change is coming, absolutely. The articles I made it through are listed above but there are dozens more if you Google around a bit. Sidense and Kilopass both have records of this legal adventure on their websites as well. The Sidense site is more up to date since they won of course:

http://www.kilopass.com/news-events/litigation-update/
https://www.sidense.com/news-a-events/press-releases/2014.html