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We Need One MILLION Design Starts!

We Need One MILLION Design Starts!
by Daniel Nenni on 06-01-2014 at 5:03 am

Design starts are the lifeblood of the semiconductor industry. It’s not just the design start itself, it’s the innovation that goes with it. As the semiconductor industry consolidates and the cost of modern semiconductor design increases you have to ask yourself: Where are the next generation of design starts going to come from?

Look at the postings on the SemiWiki Jobs Forum, the fabless semiconductor ecosystem is struggling to fill jobs. Since breaking ground on Fab 8 in 2009 GlobalFoundries has created approximately 2,000 jobs and that number is expected to grow by approximately another 1,000 employees for a total of about 3,000 new jobs by the end of 2014. Qualcomm has over 600 openings and even though Intel’s business is in decline they have more than 1,000 openings. So you have to ask yourself: Where are the next generation of semiconductor professionals going to come from?

The answer of course is the Universities and it is my belief that Silicon Cloud Internationaland the Internet of Things will lead the way:


SCI establishes secure cloud computing centers for universities and research institutions across the world. SCI’s initial focus is on providing turn-key design-to-manufacturing workflows for semiconductor design.

At the SCI booth, you will see several demo stations – unlike any other demo stations you have seen before! A diminutive Chrome box client is all that is needed to connect to powerful remote servers to perform real life design tasks on large circuits. Other than a demo on the main features of the system, you will also see:

SCI’s private cloud and thin client architecture and their unique security model for semiconductor eco-system providers and users

SCI’s chip design environment set up and workflow management capabilities

An online and interactive IC design training package developed by North Carolina State University

A couple of SCI’s partners, Plunify and Optic2Connect will be demonstrating their capabilities using the SCI cloud

Students from UCLA and Nanyang Technological University (Singapore) will be demonstrating and discussing their design work, running in the SCI cloud. The students’ demos are at the University Booth.

SCI founders will be on hand to demonstrate and discuss the attributes of the system. This includes:

  • Mojy Chian, CEO, previously SVP of Design Enablement at GlobalFoundries
  • Marc Edwards, CTO, previously with Nimbis, Synopsys and Cisco
  • Joe Lee, VP of Engineering, a 30 year IBM IC design veteran

We invite you to visit us at Booth #209C to see how you can be a part of this semiconductor design enablement transformation!

Silicon Cloud Internationalwas started in 2012 and incorporated in July 2013 in Singapore by veterans of the semiconductor industry. The founders of SCI recognized the benefits of modern cloud computing technology for semiconductor design. The cloud is inevitable and the benefits of cloud-based IC design infrastructure are ubiquitously recognized including, unburdening the user from the cost and complexity of setting up IC design infrastructure, efficient and scalable use of EDA tools and computing hardware (pay-as-you-go), global knowledge sharing and IC design training, and global and collaborative IC design.

However, data and IP security and managing a very wide IC design eco-system have prohibited the launch of an IC design infrastructure in the cloud. Silicon Cloud International provides a unique and unprecedented technology for security, data tempering, and IP downloading.

SCI’s market deployment has initially focused on Asia Pacific and the Middle East regions (Malaysia, Singapore, Abu Dhabi, and Pakistan). Future plans for additional SCI Cloud data centers include Vietnam, Brazil, Germany, China, and the US.

More Articles by Daniel Nenni…..

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Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS

Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS
by Daniel Payne on 05-31-2014 at 9:20 pm

My former co-worker, Kenneth Bakalar at Mentor Graphics is an expert in AMS modeling languages and UPFmethodology, so he recently teamed up with Eric Jeandeau to author an interesting white paper: Interpreting UPF for a Mixed-Signal Design Under Test. This white paper is based on a presentation made at DVCon earlier this year. The basic idea presented in this 16 page paper is that modern SoCs use lots of power-management techniques to power-down and power-up blocks in the quest to conserve power, and that you should be able to model the effects of this in a UPF-based simulation flow.

You start out with a digital design and it’s UPF file. Next, you will swap out a digital block for an AMS model where the new electrical ports correspond directly to the previous digital block ports. The AMS model contains extra electrical ports that will supply power to the analog sub-circuit within the model. Each analog power supply connected to the ports will get synchronized with the actual power state of the UPF power domain for this instance.

As digital signals are connected to electrical nets, it’s required that a signal connect element be inserted to enable communication between digital and analog realms. Here’s a diagram showing a signal connect element:


General model of a power sensitive, bidirectional signal connect element

Connect Elements

Coding examples in VHDL-AMS for electrical to real, and electrical to logic are shown below. If the input analog voltage changes by as much as the tt parameter (1mV), then a new digital value is driven on outp. There’s also a check on the power state, and if either power net is OFF, then the output is driven to voff.


VHDL-AMS entity for an electrical to real (A2D) connect element


VHDL-AMS architecture for an electrical to logic (A2D) connect element

Connect elements are also written for a logical to electrical (D2A).

When connecting UPF power to analog pins we really want the power/ground pair to be dynamically responsive to the controls described by UPF. The technical solution to this is inserting a power to electrical element (P2E), and here’s the code example written in VHDL-AMS:


VHDL-AMS model for a P2E

This P2E model will convert digital input upfin of supply_net_type into an analog voltage, and upfin indicates if the digital power port is powered up or down. The power state control both the voltage and impedance of the branch from vdd to vds, which is then used by the analog blocks. The rise and fall times are also coded.

The converse of P2E is called E2P, and this connect element is interposed between electrical to power.

The good news is that the engineers at Mentor have implemented all of these connect elements and supported methodology into the Questa ADMS mixed-signal simulator. An example of how connect elements are used is shown in a mixed-signal design under test, called YDUT:


Example design under test with a testbench

AOT_TEST is the top-level and is defined in SPICE, while the XTOP subcircuit is also in SPICE, finally YDUT is the digital Verilog design under test. Verilog instance YSTIM controls all four of the UPF power domains:

The timing for the power domains is coded in the testbench stimulus, and here’s the timing diagram:

Multiple tests were written to control each power domain, and here we see that power domain pd_top turns on at 100 us, and two outputs then become active:

Summary

It is possible in a UPF design to model the power characteristics by adding SPICE, VHDL-AMS or Verilog-AMS models. Mentor’s Questa ADMS simulator has been extended with two new methods:

[LIST=1]

  • Providing UPF-controlled, SPICE-level power to AMS instances as needed
  • Defining signal connect elements that are aware of power state of each UPF power domain.

    If you’re visiting DAC this week, then stop by booth #1733 and ask about Questa ADMS.

    lang: en_US


  • Don’t Eat Rubber Chicken in the Best Food City in the World

    Don’t Eat Rubber Chicken in the Best Food City in the World
    by Paul McLellan on 05-31-2014 at 8:55 am

    You are going to DAC next week. And you don’t want to eat a Moscone Center rubber chicken Caesar salad for lunch. But you lack local knowledge. So here are some places within a 10 minute walk (these are just places I like. Nobody is paying me to recommend them).

    The food court in the San Francisco Center on Market Street between 4th and 5th Street. This is to normal mall foodcourts the same way San Francisco Airport food is to normal airports. It’s actually good. There are two food courts, but far and away the best is the one at the 4th street end of the building. Go in the first entrance you come to walking along Market Street and go down the escalator. It has an amazing selection of ethnic food (Vietnamese, Korean, Thai, Japanese, Mexican, gourmet burgers, Vegan Chinese…is that even a thing?).

    Indian: Chaat Cafe on the corner of 3rd Street and Folsom. The Tandoori mixed grill is a particularly good bargain if you have a crowd, a lot of meat for not many rupees.

    Thai: Osha on another corner of 3rd Street and Folsom.

    Mexican: Chevy’s on corner of 3rd Street and Howard Street. A chain but a good one. Everything is fresh.

    Brew pub and tapas (yes, both, really): Thirsty Bear on Howard between 3rd and 2nd Streets.

    Pizza: California Pizza Kitchen on 3rd between Mission and Market Streets.

    Chinese: Henry’s Hunan on Natoma Street just off New Montgomery Street. Don’t miss Diana’s Special Meat Pie.

    All these places are a 5 or 10 minute walk from Moscone. Enjoy.

    The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.



    DAC is Next Week!

    DAC is Next Week!
    by Paul McLellan on 05-31-2014 at 3:03 am

    DAC starts on Sunday. If you are in San Francisco on Sunday then the first event is the normal welcome reception. This is the ultimate networking event in EDA. It is in the Intercontinental Hotel about a block from the convention center and runs from 5.30 to 7pm. This is preceded by Gary Smith’s traditional kickoff from 5pm to 5.30pm. If you miss it on Sunday it is repeated in the Pavilion on the show-floor early on Monday morning. Dan and I will both be there on Sunday night.

    It probably hasn’t escaped your notice that Dan Nenni and John Cooley don’t have a great relationship. But I’m totally agnostic on it. Cooley’s DAC guide is out and you should totally print it out and use it to guide yourself around the show-floor. It is here. I’m not going to claim that John’s opinions are accurate on everything, he has his biases of course, but I’m willing to bet he has put more thought into what to see at DAC than you have. You have no time, right? We have guides to various companies on SemiWiki, in much more detail, but as a comprehensive guide to DAC you cannot beat John’s guide. So read the SemiWiki guides which have a ton of detail and use John’s guide for the big picture and to fill in the gaps.

    The biggest event of the whole show, better even than the keynotes, is (OK I’m biased) the Tuesday night cocktail party sponsored by SemiWiki and eSilicon where you can get a free copy of “Fabless” the best book ever written (OK, the only book ever written) about the semiconductor industry’s transition from IDM to foundries, the growth of TSMC, EDA’s importance in the ecosystem and more. The book signing and DAC evening is 6-7pm in the Esplanade Foyer. I’ll be there. You should be too (and you don’t have to sign a thousand books).

    Talking of keynotes, Cliff Hou of TSMC is giving the keynote on Monday. It is a slightly weird time so don’t miss it just because you are pre-occupied (hilarious, our CMS doesn’t recognize pre-occupied but suggests pee-occupied as an acceptable alternative. I’m not going there, make up your own joke). It is at 3.25pm in Ballroom 102.

    DAC has two special additional areas of focus this year. IP and automotive. There are special tracks, special panels and so on. Did you know that 30% of the value of a modern car these days is in electronics. Think about it? What recent development in cars (Tesla, hybrids, engine-control ABS, navigation…) is not really just adding electronics to the metal. Delphi used to tell me that GM spun out the wrong bit, they should have kept the electronics and outsourced the metal-bashing. But they went bankrupt due to inherited pension obligations, so not exactly a convincing case.


    More articles by Paul McLellan…


    Context Aware Library Models for Improved Static Analysis Accuracy

    Context Aware Library Models for Improved Static Analysis Accuracy
    by Daniel Nenni on 05-30-2014 at 10:00 pm

    Digital semiconductor design flows predominantly use library models (typically verilog and liberty formats) for static analyses. Design sizes continue to grow and geometry continues to shrink. Demand for superior performance continue to increase. Accuracy of the library models has become more critical than ever before to enable the optimum design performance, power and noise. A library cell can be instantiated in a variety of different design context and different instances might perform differently. The idea of “one model fits all instances”, with no knowledge of design context, is a source of gap between the actual characteristics of a cell vs. those represented by the library model. A library model that is too conservative leads to over design whereas a progressive models leads to correlation issues. The EDA vendors have been struggling to provide library cell models that can represent all possible usage scenarios. At the same time traditional approaches are reaching their limits and proving to be insufficient to meet today’s design requirements.

    Before we go into more details of what is lacking in library characterization softwares currently available from various EDA vendors (vs. what do today’s designers ideally need from their EDA vendors), it will be worthwhile to understand the bridge these library models create between static and dynamic analysis methods.

    Dynamic analysis methods do actual simulation of the design to measure the functionality and various characteristics with high accuracy. Dynamic analysis methods however are heavy users of the compute resources and take long run times.

    Static analysis methods on the other hand are inherently faster, since they avoid dynamic simulation. Instead, they use library models of the cells created by dynamic simulation. Static analysis is used for exhaustive and conservative analysis of one design metric (static timing, noise, power etc.) with no regard to design’s other metrics.

    Some advantages of static analysis are:

    • It exhaustively covers the whole design.
    • It has ability to perform multiple modes in the same session.
    • It is many orders of magnitude faster than dynamic analysis.

    Some of the disadvantages of static analysis are:

    • It may lead to false negatives for improperly constrained designs.
    • Static results are conservative, meaning it may flag a false problem such as negative slack because of a false-path for static timing analysis.


    Modern characterization softwares pay no attention to the design context i.e. how the cells are used in the design. Ignoring the design context while creating library models, is the prime source of inaccuracy in the models that eventually leads to miscorrelation and other inaccuracies in static analysis flows. There are a number of subtle nuances (parameter and methods) that a characterization software should be aware of – as depicted in Fig1.

    The ideal solution is to create/interpolate models on the fly on a need basis by timing, power, noise and other analysis software. Analysis software has complete knowledge of the context it is operating in. Analysis software spawns characterization API with correct set of inputs derived from design context. Characterization API, in turn, creates and returns model for every unit during timing, power and noise analysis.

    In an ideal world, this solution works perfect. However, in the world of limited resources, it runs into issues including performance degradation by many orders, large compute resources requirement, large number of software license required, and lack of incentive to analysis software providers to adopt this methodology- just to name a few. Figure 2 depicts this perfect (but highly impractical) flow with analysis, characterization and simulation, generating models with real design context.

    I was impressed by Paripath’s library characterization platform that produces CAM(Context Aware Model) models that not only meets today’s designers’ accuracy needs but also uses massive distributed processing to efficiently conquer the run-time and capacity challenges. The main concept behind their solution is to allow the characterization software to study a representative design and collect set of parameters/methods suitable to design type, constraints and technology node among others. Armed with design context information, Pa!path’s characterization software uses circuit analysis and simulation to generate models as depicted in Figure 3. These models not only have knowledge of what is inside the cell, they are also aware of the context they’ll be used during static analysis methods.

    Paripath’s characterization software armed with design context information is capable of generating models that are context aware. Context aware models are best equipped to address difference in philosophy and technology of dynamic analysis and static analysis methods. These context aware models aid to provide true design sign-off with good correlation of static analysis to circuit simulation. Context aware models help designers avoid the over- and under-design of designs reducing costs and saving time from design schedules.

    Written by Rohit Sharma

    lang: en_US


    Google Robot Cars are Coming!

    Google Robot Cars are Coming!
    by Daniel Nenni on 05-30-2014 at 10:30 am

    Paul McLellan and I attended the 2014 Embedded Vision Summit in Silicon Valley this week. The most interesting session for me was on the new Google car that was announced earlier in the week. But first, to set the stage, let’s look at a new study by the National Highway Traffic Safety Administration (NHTSA) that shows motor vehicle crashes had an $871 billion economic and societal impact on U.S. Citizens, which is the equivalent of 1.9 percent of the $14.96 trillion Gross Domestic Product (GDP) in 2010.

    NHTSA’s new study, The Economic and Societal Impact of Motor Vehicle Crashes, 2010 cites several behavioral factors as contributing to the huge price-tag of roadway crashes based on the 32,999 fatalities, 3.9 million non-fatal injuries, and 24 million damaged vehicles that took place in 2010. Key findings include:

    • Drunk Driving: Crashes caused by drivers under the influence of alcohol accounted for 18 percent of the total economic loss due to motor vehicle crashes and cost the nation $49 billion, an average cost of $158 for every person in the U.S.
    • Speeding: Crashes involving a speeding vehicle traveling over the posted speed limit or too fast for conditions accounted for 21 percent of the total economic loss and cost the nation $59 billion in 2010, an average cost of $191 for every person in the U.S. Including lost quality of life, these crashes were responsible for $210 billion or 24 percent of the overall societal harm caused by motor vehicle crashes.
    • Distraction: Crashes involving a distracted driver accounted for 17 percent of the total economic loss and cost the nation $46 billion in 2010, an average cost of $148 for every person in the U.S. Including lost quality of life, these crashes were responsible for $129 billion or 15 percent of the overall societal harm caused by motor vehicle crashes.
    • Pedestrians and Bicyclists: Crashes involving pedestrians and bicyclists accounted for 7 percent of the total economic loss and cost the nation $19 billion in 2010. Including lost quality of life, these crashes were responsible for $90 billion or 10 percent of the overall societal harm caused by motor vehicle crashes.

    The safety issue is near and dear to my heart as I was run down while riding my bike by a distracted driver and left for dead on the side of the road. Thankfully first responders happened by shortly thereafter and I lived to ride again.

    The thing I love about Google is that they thrive on disrupting Big Industry and make quite a large amount of money in doing so. They certainly changed the search and the advertising industry similar to the way ARM brought Intel to its knees with low power/low cost processors enabling the mobile devices that have displaced traditional PCs. Apple is also one of my favorite disrupters.

    The Google presenter was Nathaniel Fairfield. Nathaniel has a PhD from Carnegie Mellon University. Carnegie Mellon is known for robotics which is what we are really talking about here. Paul or I will write about this in more detail when the slides are available but this infographic is a good start:

    More Articles by Daniel Nenni…..


    Sidense NVM IP clears TSMC9000 at 28nm

    Sidense NVM IP clears TSMC9000 at 28nm
    by Don Dingee on 05-29-2014 at 7:00 pm

    Maybe I’ve spent too many years whiffing solder flux fumes and absorbing doses of X-band radiation in anechoic chambers, but I’m a firm believer in the axiom: “Give me enough engineers, and I can get 10 of anything to work right, once.” We have to make this … fit into this … using only this stuff … is what legends are made of. Continue reading “Sidense NVM IP clears TSMC9000 at 28nm”


    SemiWiki Exceeds One Million Users!

    SemiWiki Exceeds One Million Users!
    by Daniel Nenni on 05-29-2014 at 11:00 am

    SemiWiki was launched on January 1[SUP]st[/SUP] 2011 and according to Google Analytics we have officially exceeded one million users (unique visitors). I really don’t know what to say but, WOW, that is a LOT of people reading SemiWiki articles, wikis, and forums (there are now 13,464 posts on SemiWiki).

    According to Alexa.com SemiWiki is ranked as the 130,975[SUP]th[/SUP] most popular website in the world and 34,758[SUP]th[/SUP] in the United States (Google is #1, FaceBook is #2). That is simply amazing to me, I would have never imagined that large of an audience when I started a WordPress blog five years ago. Crowdsourcing really does work!

    It was slow going when SemiWiki first started. In the first three months (Q1 2011) we only had 20,608 users but by the end of the year we had 170,501, so that was good pretty, right? My WordPress site “Silicon Valley Blog” had about 10,000 readers at its peak. SemiWiki ended 2012 with 459,608 and at the end of 2013 we had 829,408. Since other websites in our industry don’t publish their user numbers I will assume we are doing a pretty good job.

    According to Alexa.com we still have a long way to go to catch EETimes which is rated the 30,949[SUP]th[/SUP] most popular website in the world and 18,160[SUP]th[/SUP] in the United States. It really is an apples to oranges comparison since EETimes is a network of websites but it serves as a good benchmark for future growth, absolutely.

    In the other Alexa metrics however SemiWiki does quite well:

    How engaged are visitors to semiwiki.com?

    • Bounce Rate 36.00%
    • Daily Pageviews per Visitor 5.40
    • Daily Time on Site 10:33

    How engaged are visitors to eetimes.com?

    • Bounce Rate 67.60%
    • Daily Pageviews per Visitor 1.77
    • Daily Time on Site 2:15

    If you are interested in learning more about SemiWiki or New Media in general I would be happy to share my thoughts with you. We can have a formal discussion on “Managing New Media” or we can just meet over coffee and chat about it. If you are not in Silicon Valley I’m a big fan of Skype and constructive criticism is always welcome.

    The biggest difference between SemiWiki and other industry websites is that we all have day jobs. We are semiconductor professionals and consultants who enjoy writing and communicating the value proposition of the fabless semiconductor ecosystem. Please see our LinkedIn profiles to learn more about us as individuals:

    If you want to be successful with SemiWiki you need to give us two things: Access and honesty. As semiconductor professionals our time is limited and since we trade on our reputations honesty is an absolute requirement. As bloggers we share our experience, opinions, and observations so you may not always agree with what we write but you should however see value either way.

    The most important thing you should consider about New Media and SemiWiki specifically is going for the long game versus the short one. Don’t just jump in and out of our lives with news releases. Work with us, develop relationships, and integrate SemiWiki into your long term communications strategy, absolutely.

    More Articles by Daniel Nenni…..

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    TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC

    TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC
    by Paul McLellan on 05-28-2014 at 8:11 pm

    What is TSMC doing at DAC?

    The biggest event is presumably Cliff Hou’s DAC keynote on Monday at 3.25pm Industry Opportunities in the Sub-10nm Era. And he also wrote the foreword to Fabless, the book that Dan Nenni and I have written and where you can get a signed copy on Tuesday evening at the reception.

    There is an IP workshop Driving Quality to the Desktop of the DAC Engineer which takes place on Sunday from 1-5pm in room 202 in the Moscone Center. This is presented by Steven Chen and Lluis Paris.

    TSMC is participating in two panels. The first is on the IP track and is in room 101. Lluis Paris is moderating the topic of IP Quality. There is also a pavilion panel on Connecting Everything: Architecting the Internet of Things,Dan K is on the panel.

    There are lots of presentations with TSMC’s partners, too many to mention.

    TSMC themselves are on booth 1801. They will be talking a lot about IP quality. Have you noticed TSMC are very big on IP quality? They started just using software tools such as Spyglass for evaluating quality but they have now created a silicon validation lab in Taiwan to take it to the next level.


    So the top level message is:

    • 20nm Complete

      • In mass production
      • Everything qualified and validated on customer designs
    • 16nm FinFET Complete

      • V1.0 Certification completed
      • IP silicon validated and available
      • Interface IP in silicon validation now
      • 16nm FinFET will be ready by end of year


    One new thing you might not have heard is that there is a new 28HPC process offering. Spice corners have been tightened and there is a new signoff methodology. There is also a new high-efficiency 7-track library.

    OIP is thriving. It has been running for over 12 years. The portfolio is impressive with over 7000 titles from 40 different IP vendors.


    Overview of activities is here. Theater schedule on the booth is here.

    Once again, TSMC’s booth is #1801.


    More articles by Paul McLellan…


    How About a Quality-Aware IP Design Flow

    How About a Quality-Aware IP Design Flow
    by Daniel Payne on 05-28-2014 at 6:18 pm

    In the EDA world we use hyphens quite often to describe our technical approaches, like: DFM-aware, Power-aware, Variation-aware. I just read a white papertoday on the topic of Quality-Aware IP Design Flows, written by Fractal Technologies. If your group creates IP or re-uses IP, then there’s always the question about the readiness or quality of each IP block. Shown below is a flow of how cell libraries and larger IP blocks get created by an IP vendor and then used by an SoC designer, along with the checking and validation processes necessary to ensure high quality and reduce re-spins.

    Incoming IP Inspection

    An incoming IP inspection QA tool should detect any incompatibilities on new IP for your present design flow or self-consistency within the IP blocks. The earlier that you uncover an inconsistency with IP the better, because you don’t want to find an IP block issue during tape-out because of the amount of effort required to re-validate your entire SoC design. Semiconductor IP has many assets that require checking:

    • Databases
    • File formats
    • Design views (logical, physical, simulation, etc.)

    The QA tool from Fractal Technologies that provides a GUI-based approach to incoming IP inspection is called Crossfire, and it has a matrix of possible checks for each IP database and file format. Any violations or mismatches may then be graphically highlighted. You can even waive any irrelevant view-mismatches for your particular SoC project as needed in order to reduce the amount of information reported.

    Background IP Checking

    As cell libraries and IP blocks are used within an SoC project, you should be running IP checks again in context, however they can now be run in the background instead of having to use a GUI. You only need to know if there’s been any mismatch and where it arises.


    Automated development and characterization flow, all steps are push-button, QA should also be push-button

    The Crossfire tool also supports background operation through the use of a Setup API, where you have dedicated checking scripts written in your favorite language (Python, Tcl, Perl) that can automatically find recently changed databases and then run the required checks. You can integrate QA validation within your design repository, so any views that change in your working copy will run the Crossfire checks when the repository commit procedure runs. With this background IP checking approach you can later view any of the QA validation results using the Crossfire Diagnose tool.

    With this background IP checking approach the SoC designers don’t have to perform any manual steps to ensure that QA checking is happening. Only when an automated check fails, does the designer need to take any action and quickly pinpoint the source of the failure using Crossfire Diagnose.

    Summary

    Library and IP QA checks can be run both interactively and in batch modes to ensure the highest design quality, and shortest time to market with the Crossfire tool. If you’re visiting DAC in San Francisco next week, then stop by to see Fractal Technologies at booth #507.

    lang: en_US