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June 25, 2014

Xilinx has the Power Advantage over Altera

Xilinx has the Power Advantage over Altera
by Luke Miller on 06-25-2014 at 6:00 am
Categories: FPGA, Xilinx

I thought I write about one of the most important subjects in FPGAs, that is power. Power of course is not just based on node size, and it is funny why so many people are concerned about node size. If not just as important is the architectural decisions that drive down power. Do you really care if your part is 16nm or 14nm? Or do you care more about power, performance etc…

Core voltages continue to drop, and serial data rates are going up… way up. Standards, so called, like JESD204b and Hybrid Memory Cube solve many board routing nightmares and power issues BUT chew up an awful lot of GT lanes. I’m not complaining, I hate DDR but this migration highlights the leadership of Xilinx’s Gigabit Transceivers. Xilinx just finished publishing a white paper on the power advantages at their 20nm/16nm node. “Power Reduction in Next-Generation UltraScale Architecture”.

These power reductions are being realized today on real hardware by real customers. They configure and even work. Xilinx’s power performance is not only at 20nm, but below are some nice 28nm charts of how Xilinx does against the ‘competitor’. I wonder who that is?

Back to the serial interfaces that I was all wound up about. The above shows a 4 channel design, At 28 gb/s, Xilinx is running about 800mw and Altera at 1000mw. Yes this is the same node compare, 28nm. Ok, so you say big deal lukey dukey, I don’t care about 200mw. Ok, how about your design that uses 64 lanes for Hybrid Memory cube and another 32 for JESD204b? Power differences just for transceivers begins to add up. We approximately would have 19.2 Watts for Xilinx, and Altera 24 watts. So Xilinx here is 5 watts better. All the green folk just cheered.

Most designers start early in the design cycle having the goal of about being complete when the silicon rolls of the line. That means the quality of tools, specifically the models that yield the power need to be accurate. Interested in seeing how well Xilinx does in model to hardware correlation with respect to power? That is how accurate are the power estimator tools?

Xilinx is rock solid once again. Using the ‘competitors’ tools may leave you with a design that no worky because you no cooley. This is huge and it points to execution once again. The difference is Xilinx set’s design goals and achieves them. The competitor, waits for hardware to come back and then begins to write the data sheet. Like I said earlier, node is not that important. Power, performance and of course tools all lead to a quality of result that only Xilinx can deliver and can be relied upon.

OK, let’s put this all together at the system level shall we?

What more can I say? I always do wonder this, why in the world are you using Altera? I wrote about 28nm power for the most part, and the power separation will only continue coupled with accurate powering modeling from Xilinx. Makes me wonder what type of design you are going to have at 20nm?

lang: en_US

June 24, 2014June 14, 2019

Wally Rhines at #51DAC: EDA Grows From Solving New Problems

Wally Rhines gave the keynote at DAC in 2004. One of the things that he pointed out ten years ago was that EDA revenue for any given market segment is pretty much flat once the initial growth phase has taken place and the market has been established. Incremental EDA revenue only comes from delivering new capabilities. Historically these have largely been in new area.

EDA started with custom layout, then added PCB, then ASIC, then COT and so on. Each new market grew EDA but the older markets remained flat. For example PCB revenue grew to a certain size and has remained pretty much that size every since.

At DAC this year Wally presented an update ten years on as where the current and future growth areas for EDA are.

Traditional EDA is flat and over the 2001-2013 period, the growth has all come from new areas: DFM has had a CAGR of 27% over the period, ESL of 11%, formal 10%, emulation 6% and so on. These new areas have risen from a relatively small base in 2001 and are now on their own represent $1.5B of revenue to put on top of the nearly $3B of traditional EDA.

Increasingly the incremental EDA revenue is not coming from completely new markets but from adding completely new capabilities to the traditional tools. So front end design has been flat but adding ESL, formal, power, signal integrity and emulation has led to a CAGR of 9.2% for front end over the last few years compared to 3.1% over the whole 2001-2013 period.

There are new challenges and new opportunities at 10/7/5nm: FinFETs require tools to deal with process complexity, thermal and stress. The lack of EUV requires capabilities to handle directed self-alignment, double and triple patterning and density balancing. These will be one basis for growth in the next few years.

Historically, EDA semiconductor revenue per transistor and EDA revenue per transistor have decreased at around 30% per year. The first is simply Moore’s law and the second reflects EDA revenue having been 2% of semiconductor revenue for at least 20 years. One big question, of course, is whether this will continue or whether the graphs we have all seen showing cost per transistor increasing reflect our future.

The basic thesis is that EDA grows from solving new problems. Some of these problems are in existing EDA markets, with incremental capability like ESL or formal. Some come from supplying traditional tools but into new markets, such as selling RET capability to foundries (who historically have not had enormous EDA budgets) or selling emulation to software developers. And some from new markets such as embedded software, cyber-security or automotive subsystems. Although the term is overhyped right now, this is growth from the internet of things, which will require security, embedded software, wireless communication, subsystems and more.

So with all of these things, new capabilities, access to new budgets, completely new markets, then Wally believes that the future of EDA is rosy. After all, given that EDA only grows from solving new problems, the fact that there are plenty of new problems is a driver for the whole EDA industry.

Wally’s full presentation is HERE.

ESL Tool Update from #51DAC

ESL Tool Update from #51DAC
by Daniel Payne on 06-24-2014 at 4:13 pm
Categories: EDA

As promised in my May 27th blog, I visited an ESL company at DAC three weeks ago that introduced two new tools:

Thermal Profiler
Power Intelligence

Continue reading “ESL Tool Update from #51DAC”

June 24, 2014

Internet of Things (IoT) Startup Showcase @ SEMICON West!

Internet of Things (IoT) Startup Showcase @ SEMICON West!
by Daniel Nenni on 06-24-2014 at 3:00 pm
Categories: ESD Alliance, Semiconductor Services

It’s hard to believe that SEMICON West is upon us once again at the Moscone Center in San Francisco. This is the premier semiconductor conference for cutting-edge equipment, processes, and materials, to solutions to today’s design and manufacturing challenges. Remember, it’s not what you know (because we all know everything already), it’s who you know and SEMICON West connects you to the people, products, and technologies advancing the future of microelectronics! Even if you are familiar with SEMICON West you may want to visit the FAQ for a refresher.

This year one of my favorite topics will be explored during anInternet of Things (IoT) Startup Showcase. If you do attend please introduce yourself, it would be a pleasure to meet you! I will be wearing my trademark blue SemiWiki polo shirt. It’s just like the Steve Jobs turtleneck thing only different.

An SK Telecom Americas Innopartners Program
Thursday, July 10, 2014
1:30pm-3:30pm

This Session brought to you by:
With 30 billion connected devices expected by 2020, the Internet of Things (IoT) is changing the way we work and live. But in order for the IoT to spring to life, innovations at the core technology level are essential. SKTA Innopartners Innovation Accelerator will showcase six innovative new IoT technology startups with onstage presentations covering four target market segments including; semiconductor and systems, telecom, enterprise/datacenter solutions, smart device related, and healthcare devices/bioinformatics. A networking “meet and greet” with industry executives and VCs will also precede the session.

SK telecom Americas is the business development and venture capital arm of SK telecom, Korea’s largest wireless operator and a global technology leader, and has worked with some of the brightest minds in VC and angel investing – and some of the biggest technology companies in Silicon Valley – to design a novel and new funding model. SKTA Innovation Accelerator seeds and accelerates core technology startups to create and manage the essential data center. The Innovation Accelerator matches entrepreneurs with industry leading strategic partners and provides initial funding up to $1M as a combination of working capital, state-of-the-art facilities, development tools and professional services (e.g. legal and financial). Entrepreneurs concentrate on developing their technologies, while strategic partners and venture capitalists access lower-risk investment.

[TABLE]
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| Welcome, Opening Remarks
Angel Orrantia
Business Development Director
Innovation Accelerator
SKTA Innopartners
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| 1:40pm-2:00pm
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| Lumiode Light Engines – Daylight Visible Microdisplays for Augmented Reality

Abid Hussain Biography
Vice President of Marketing
Arrayent
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| Closing Remarks
Angel Orrantia
Business Development Director
Innovation Accelerator
SKTA Innopartners
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Please check back frequently for updates and more information as agendas develop and speakers are announced.

SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

lang: en_US

June 24, 2014

Is SOI Really Less Expensive?

Is SOI Really Less Expensive?
by Scotten Jones on 06-24-2014 at 8:00 am
Categories: Foundries, TechInsights

Introduction
There have been some claims made recently that planar Fully Depleted Silicon On Insulator (FDSOI) is less expensive than bulk planar processes and FinFETs at various nodes. Some of these claims suggest that FinFETs in particular are significantly more expensive. My company, IC Knowledge LLC produces the most widely used IC cost modeling software in the semiconductor industry. Recently we have developed a new version of our Strategic Cost Model that is particularly well suited for cost comparison between bulk, FDSOI (planar) and FinFETs (both on bulk and SOI). In the rest of this article I will presents some results from these comparisons.

Assumptions
One of the key objectives of this analysis is to make the comparison between the different process variants as direct a comparison as possible. Our model uses detailed process flows for each process and we have tailored the process flows to reflect the requirements of the different processes while keeping as many process details the same as possible. Specifically:

We have used an M1 half-pitch of 48nm for the 28nm node, 38nm for the 20nm node and 32nm for the 14nm node for all processes.
Each process has 10 metal layers with layers 1 through 4 at 1x, 5 and 6 at 2x, 7 and 8 at 4x and 9 and 10 at 8x the M1 dimension.
STI/Fin, gate, contact and silicide (where used) are all 1x layers (STI/Fin is 0.75x and gate is 1.3x for FinFETs).
All processes add local interconnect (1x layer) and MIM capacitors at 20nm.
All processes include mask set amortization with the same exposures per reticle.
All calculations are for a 300mm wafer fab running 30,000 wafers per month located in the United States. The fab is always assumed to be a new greenfield fab.
All processes support 3 threshold voltages.
All processes assume the same yield loss per mask.
At processes use the same multi-patterning schemes at each node.

28nm Bulk Versus 28nm FDSOI
The first case we examined is a 28nm bulk planar process modeled after TSMC versus a 28nm FDSOI planar process modeled after ST Micro. The following table summarizes the two processes:

The costs in the table are all normalized to the total cost of the bulk 28nm process being 100%.
As we can see from the table, the FDSOI process has a higher starting wafer cost but a simpler process and the net final result is a slightly lower overall wafer cost.

20nm Bulk Versus FDSOI Versus FinFET
For the second case we looked at a 20nm bulk planar modeled after TSMC, versus a 20nm FDSOI planar process modeled after ST Micro. The following table summarizes the two processes.

The costs in the table are all normalized to the total cost of the 20nm bulk planar being 100%.
From the second table we can see that the cost for the bulk planar process and FDSOI process are virtually identical. The FDSOI planar process once again has a higher starting wafer cost but the simper and lower cost process offsets the starting wafer cost.

14nm FDSOI Planar Versus FinFET on Bulk and FinFET on SOI
For the final case we will look at a 14nm FDSOI Planar process modeled after the ST Micro process and compare it to a FinFET on bulk process modeled after TSMC and a FinFET on SOI process modeled after IBM. The following table summarizes the three processes.

The costs in this table are all normalized to bulk FinFET total cost being 100%. From the third table we can see that when the same assumption set is used across all processes, FinFETs on bulk are 6% less expensive than planar FDSOI and 3% more expensive than FinFETs on SOI.

Discussion
At both 28nm and 20nm we find that planar FDSOI is roughly comparable to bulk planar processes in cost. In both cases planar FDSOI should produce a significant advantage over bulk planar in performance and or power consumption making planar FDSOI a very attractive option for 28nm and 20nm.

At 14nm we find that when making comparable yield assumptions for planar FDSOI and FinFETs on both bulk and SOI, that FinFETs are the least expensive process although only by a small amount. The current results are in contrast to some previous work that found FinFETs to be significantly more expensive than planar FDSOI at the same node. We believe the key driver of the differences in results is very unfavorable yield assumptions for FinFET processing used in the previous work. We furthermore believe that mature FinFET process yields have already been achieved by Intel and will soon be achieved by others and that such process yields will be in the high ninety percent range making yield a non-differentiating factor between the processes.

To-date, the majority of the logic producers have chosen FinFETs on bulk for the 14nm (16nm for TSMC) generation. From this analysis it does not appear that cost is a significant differentiator between these three process options. IBM is the only company known to be pursuing FinFETs on SOI at 14nm driven by IBM’s embedded DRAM on SOI technology. Once again cost is not a differentiator based on this work.

Conclusion
Using the same yield per mask layer assumptions for both planar FDSOI and FinFETs it has been shown that the costs for planar FDSOI and FinFETs on bulk or SOI are all comparable at the 14nm node. Decisions on which process to pursue are therefore expected to be driven by factors other than cost.

lang: en_US

June 23, 2014

The “Key” to Reality

The “Key” to Reality
by Bill Boldt on 06-23-2014 at 9:00 pm
Categories: Foundries

If we wanted to reduce the definition of authentication to its most Zen-like simplicity, we could say authentication is “keeping things real.” To keep something real you need to have some sort of confirmation of its identity, as confirmation is the key (so to speak).
Continue reading “The “Key” to Reality”

June 23, 2014

Cliff Hou’s DAC Keynote

Cliff Hou’s DAC Keynote
by Paul McLellan on 06-23-2014 at 10:21 am
Categories: Foundries, TSMC

Cliff Hou had two major appearances at DAC this year. He gave the opening day keynote…and he wrote the forward to Dan and my bookFabless: the Transformation of the Semiconductor Industry which about 1500 lucky people got a copy of courtesy of several companies, most notably eSilicon who sponsored the Tuesday evening post-conference party where we signed several hundred copies. You can still get a copy if you missed out, just click on the book cover on the top left hand side of the front page of SemiWiki.

Cliff’s keynote was about the future challenges of getting to 10nm and beyond. 14/16nm (they are basically the same despite the different numbers) are pretty much a done deal. Not yet in volume production but on track to get there later this year.

Cliff started by talking about mobile which is what drives semiconductor leading edge processes. Design innovation drives process innovation which enables more design innovation. As a result we have product innovation. It seems like we have always had smartphones but in fact the iPhone only came along 7 years ago. Up until then we had dumbphones although some marketing guy at Nokia cleverly called them feature phones to make them seem…almost smart.

Of course every process generation things get harder. Double patterning, FinFETs, multiple-patterning and so on. The big challenge is that as we approach 10nm, everything becomes more costly and so the economic driver that has been behind the semiconductor industry for the last few decades is weakening. It seems clear that the technical challenges can be overcome but at what cost?

There are two different sets of challenges getting to each new process node: the process issues, mostly around lithography, and the ecosystem issues.

lithography: continue to scale 193nm immersion
device: continue to deliver 25-30% speed gain at the same or reduced power
interconnect: address escalating parasitics
production: ramp volume in time to meet end-customer demand
shortened development runway to meet product windows

Design and technology co-optimization used to be fairly straighforward. The best local optimum was also the best overall optimum: shortest wire length the best, best gate-density the best area scaling, best technology also best cost. But these rules don’t hold any more. Everything has to be co-optimized from process, EDA tools and IP. If one of these is not up in time then the designs cannot be completed and the fab will not be filled as soon as capacity is available. And given the cost of a fab at $5-8B then a fab that is not full costs a huge amount in depreciation.

The time to get to market is speeding up too. First test chip, first PDK, first shuttle, volume production, the big milestones on a new node are getting compressed. At 10nm, Cliff reckons they will be roughly half the time they had at 28nm. The cost of bringing the process up and building the fabs to run it makes it imperative to start recovering the cost as soon as possible.

Bottom line: this all requires much closer collaboration between all the partners to make everything work in a timely manner. This is the key to unlock 10nm and beyond and turn the vision into reality.

The Secret Essence of an IoT Design

The Secret Essence of an IoT Design
by Pawan Fangaria on 06-23-2014 at 7:00 am
Categories: EDA

Today the semiconductor industry along with electronics industry is looking up to capitalize from massive expansion foreseen in IoT (Internet of Things) domain. In simple terms we can consider IoT as connectivity between machines which can communicate with each other and work as programmed. In localized applications such as factory automation which may require one-way communication with dedicated private network, the machine-to-machine connectivity can be easier with lesser complexity. But what happens when in the real world of IoT the devices are exposed to public network and are needed to make intelligent decisions while maintaining proper security? How can a patient in India be monitored from a specialized medical institute in USA under adequate privacy? The simple machine-to-machine model is no more adequate. Integrated software platforms are required which can enable development and integration of code from various heterogeneous sources to build intelligent devices which can have secure connections through autonomous network insertion and are capable of making decisions with bi-directional communication. And the platforms must be extensible to accommodate upcoming protocols of connectivity, security and other needs as the world of IoT is in expansion mode. Also, an efficient power management is needed for devices as many of them are placed in remote areas and they operate on battery.

The software to maintain connectivity, security and power, if considered in true sense of IoT can be very complex. In IoT world, devices can be dynamically added or removed from the network; the resource discovery and service announcements are done autonomously. The zero configuration networking protocols such as mDNS (multicast Domain Name System) and DNS-SD (DNS-based Service Directory) support such services without needing any central server, thus enabling scalability in the IoT networks. The architectures such as REST (Representational State Transfer) should be leveraged to maintain separation between client and server that ease in network scalability and improve performance and security.

As IoT devices support bi-directional data and can be connected on dispersed public networks through a horde of connectivity options such as Bluetooth, Wi-Fi, ZigBee and so on, they are highly susceptible to unscrupulous attacks. In order to protect the IoT system and devices, all kinds of security threats (active and passive) must be detected, neutralized and corrected. Various checkpoints such as encryption, authentication, and source of data before its transmission must be employed. The protocol OCSP (Online Certificate Status Protocol) streamlines the client side resources required for x.509 certificate verification. The TLS (Transport Layer Security) which uses AES-256 (Advanced Encryption Standard) and 3DES can be used to provide high level of encryption required for IoT devices. Also MAC (Message Authentication Code) is used to ensure integrity of the message without any alteration during transmission.

Power management is another issue for IoT devices which must consider all avenues of power saving. Fortunately, there are several methods (e.g. DVFS, sleep and idle modes, clock gating, hibernate etc.) and low power technologies available to optimize power; however the underlying software must be designed to gain full advantages of these techniques.

So, coming to the core question, what must be the essence of an IoT design which can keep it running by fulfilling all the above needs amid several complexities? It’s the real-time operating system and software on top of it which works behind the scene and enables the IoT devices to work flawlessly and intelligently as desired under various networking and security protocols without any security breach. I like the Nucleus RTOS provided by Mentor Graphics which is an ideal full-featured underlying RTOS framework for an integrated IoT solution.

Nucleus is a widely deployed and scalable 3KB microkernel based RTOS designed for today’s IoT world. It supports an array of networking and security protocols with high performance connectivity and integrated power management system. It fits nicely into a memory constrained MCU-based device, and yet provides the functionality required for IoT systems.

The connectivity options include widely available Wi-Fi, Bluetooth, BLE (Bluetooth low energy), USB 2.0/3.0 for IPv4/IPv6 based networks and so on. The architecture is extensible to include additional software protocols as required. A full featured IPv4/IPv6 stack with over 50 protocols and support for zero-configuration networking that includes mDNS and DNS-SD is available for networking.

The security is provided for data in storage as well as in transmission. While in storage, the data can be encrypted and password protected. The security during transmission includes TLS/SSL with encryption options including AES-256, 3DES, DES, RC4 and many others. OCSP authentication and Hash functions are available to ensure message integrity without any alteration.

An extensive Power Management Framework available in Nucleus lets the IoT devices operate under various low-power modes through intuitive API calls. A complex device can be transitioned into hibernate or standby mode by safely turning off peripherals, moving code into non-volatile memory and changing the operating point of the device.

A complete underlying RTOS like Nucleus can offer software developers and design architects a versatile framework for developing IoT devices and systems that can work unabated with their full potential in public network and real life situations. Andrew Caples, Senior Product Marketing Manager at Mentor has described in great detail about the requirements of IoT and Nucleus in his whitepaper posted at Mentor’s website. It’s a nice read.

Intel Invests in the Fabless Ecosystem!

Intel Invests in the Fabless Ecosystem!
by Daniel Nenni on 06-22-2014 at 11:00 am
Categories: Ansys, Inc., Cadence, EDA, Intel Foundry, Siemens EDA, Synopsys

During my illustrious career one of the most useful axioms that I use just about everyday day is: “Understand what people say but also understand why they are saying it.” This certainly applies to press releases so let’s take a look at what Intel unleashed during #51DAC (in alphabetical order):

ANSYS And Intel Collaborate To Deliver Power, EM And Reliability Sign-Off Reference Flow For Customers Of Intel Custom Foundry –

Cadence and Intel Collaborate to Enable a 14nm Tri-gate Design Platform for Customers of Intel Custom Foundry –

Mentor Graphics Tools Fully Enabled on Intel’s 14nm Processes for Customers of Intel Custom Foundry –

Synopsys and Intel Collaborate to Enable 14-nm Tri-Gate Design Platform for Use by Customers of Intel Custom Foundry–

Building a fabless design ecosystem is a very difficult thing. TSMC has been doing it for 25 years which resulted in the Grand Alliance we have today. As the #1 pure-play foundry, ecosystem partners swarm TSMC. The big challenge is silicon validation which is what the TSMC OIP is all about. As the #1 consumer of EDA tools, Intel has a distinct advantage since they write some very big checks. Close to half a billion dollars a year I am told. Samsung is in a similar position, being one of ARM’s biggest customers Samsung foundry definitely has the IP advantage. Samsung also writes some very big partner checks.

When GlobalFoundries got started, they wrote some really big checks to EDA and IP vendors as well. In fact, they were some of the largest single orders for partners I have seen. If I remember correctly Virage Logic got $6M, all for the greater good of the fabless semiconductor ecosystem, absolutely.

Big ecosystem checks do not necessarily mean big wafer orders though so we will have to wait and see. It certainly is a step in the right direction and it tells me that Intel will be back for 10nm foundry business, even more agressivley than 14nm. The 10nm ecosystem press releases will be coming next. It’s a four horse race so let’s see who wins the 10nm PR derby.

I also think it is interesting to see the embedded quotes. Since these four press releases came out within minutes of each other it makes speculating even more fun.

“A close collaboration between Intel Custom Foundry and ANSYS on reliability verification reference flow for 22nm and 14nm enables our customers to efficiently deliver more robust and reliable designs for next-generation electronic products,” said Venkat Immaneni, senior director, Foundry Design Kit Enablement, Intel Custom Foundry. “This platform enables our customers to use an industry-leading power, EM and reliability sign-off solution on our design platforms.”

“Our collaboration with Cadence on tools and low power memory interface IP will allow our customers to take advantage of Intel’s 14nm design platform and design differentiated products for their markets,” said Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry. “We are working together to ensure joint success of our customers.”

“We are very happy to be working with Mentor Graphics to ensure that a full suite of simulation and verification solutions are in place and optimized for our 14nm processes,” said Venkat Immaneni, Senior Director of Foundry Design Kit Enablement at Intel Custom Foundry. “This means our mutual customers can use the tools they have in place and are comfortable with, while taking advantage of Intel’s process leadership.”

“The combination of Intel’s 14-nm Tri-Gate process technology and Synopsys tools, memory and interface IP enables designers to create industry-leading SoCs for their target markets,” said Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry. “By building on our successful collaboration on Intel’s 22-nm design platform, we have been able to seamlessly extend the solution to our 14-nm process technology.”

Before I give my expert speculation of the quotes maybe you can offer yours?

ARC EM DSP supports Always-on Devices

ARC EM DSP supports Always-on Devices
by Eric Esteve on 06-22-2014 at 3:01 am
Categories: IP, Synopsys

The ARC EM family is the low-power, embedded and low footprint processor part of the larger ARC processor. To target the ultra low-power markets like wearable and IoT, Synopsys has added DSP capabilities to EM5D and EM7D. To be specific, these cores are optimized for ultra low-power control and DSP, thanks to:

Energy-efficient 3-stage RISC pipeline
Unified single cycle 32×32 MUL/MAC unit
Energy-efficient signal processing of voice/speech, audio and sensor data
Operating Floating Point Unit (FPU)

Thus, the EM5D and EM7D cores are especially suited to always-on voice activated and sensor processing applications. The dynamic power consumption of the ARC EM processors can be as low as 3 uW/MHz, particularly well-suited for wearable devices and battery powered applications.

But users are demanding IoT and wearable devices with longer battery life, this is not surprising, and at the same time expect more complex features and better user interface, requiring higher levels of signal processing… and lower power consumption!

As you can see on the picture below, the ARCv2DSP instruction set architecture (with over 100 DSP instruction) is separated with the parallel 3-stage pipeline, counting 32×32 MUL/MAC unit, square root, divide and butterfly acceleration, as well as various size (2 x 32b/40b or 1 x 64b/72b) accumulators. To cope with customer demand for flexibility, DSP features are configurable, and can be tailored to suit the application. But we have to remember that the power consumption is the most critical feature, thus ARC EM5D and ARC EM7D benefit from enhanced (8 states) sleep modes. Synopsys is claiming 7 uW/MHz power specifications for a core running up to 530 MHz on 40nm LP and delivering 1.77 DMIPS/MHz (or 3.41 CoreMarks per Mhz).

Synopsys propose an evaluation of the power consumption of ARC EM5D (using an RTL simulation including both logic and memory dynamic power) running Sensory’s Power Sound Detection from the TrulyHandsfree Voice control technology and consuming 4 uW, comparing with Competition A (maybe Tensilica?) at 17 uW and Competition B (maybe CEVA?) at 20 uW. Impressive! I can’t guarantee that these data from Synopsys’s competitors are the latest available, neither who is who, even if I am almost sure that A and B are Tensilica and CEVA, or reverse.

Another interesting benchmark from Synopsys: the Power Performance Area (PPA) comparison of the EM5D (the ARC core with DSP capabilities) with:

ARM Cortex-M4
MIPS icroAptiv
Tensilica mini108
ARM 968

When interpreting this diagram, you have to remember that you are an engineer, but I think the picture is also accessible to non-engineers. The performance is expressed by the top circle, in total DMIPS, on the Y axis. The power, in mW is the right edge of the circle, on the X axis. And the (Silicon) area is the diameter of the circle. Thanks to the selected competitors, you may compare the circle area (even if there is a geometric amplification, as area is function of the square of the diameter…), as all the competitor’s products exhibit a larger area.

As with any benchmark, the result will depend of the selected competitors, and the selected technology. A larger area on 65LP technology could have a negligible impact on 28nm technology, for example… Nevertheless, these benchmark result qualify the ARC EM DSP enhanced family for addressing IoT and wearable markets, requiring ultra low-power and signal processing capabilities, optimized for signal processing of always-on voice/speech, audio and sensor data applications. The ARC MetaWare toolkit complement this H/W offer, providing rich DSP software library and C/C++ Compiler.

From Eric Esteve from IPNEST