With use cases expanding, the meaning of “automotive qualified” semiconductors is changing. What we’re now hearing about now is beyond the AEC-Q100 Grade 0 upper end of 150°C, while still meeting other reliability, retention, and security requirements. What does hypergrade mean for complex digital chip designs moving forward? Continue reading “Get ready for hypergrade in automotive”
More on the Practical Uses of Automation
There’s a good article in the March issue of the Communications of the ACM which follows a theme I commented in my “One, Two Many” post. But the CACM article has a better title: “Automation should be like Iron Man, not Ultron”.
For anyone who hasn’t seen the movies, Iron Man is a man (Tony Stark) who has built a suit to enhance his abilities. Ultron is an automaton, made in a similar form to the Iron Man suit but not requiring a human operator. Of course the CACM article doesn’t use the movie as an argument – that would be silly. What the author (Tom Limoncelli) does is to talk about different classes of automation and why one class may ultimately prove superior to the others.
The leftover principle
This is the first class – automate the easy stuff and leave the hard stuff to the humans. A problem with this is that what’s leftover gets progressively harder and within the abilities of only a small number of people. Also we develop skills to solve harder problems while we are solving easier problems. Take away the easy problems and our general problem-solving skills deteriorate. In the limit, this is the Ultron approach. There’s another problem he didn’t mention. The economics of solving easy problems are not very attractive because we don’t assign much value to solving easy problems. Of course as the problems get harder they should gain value, but difficulty is in the eye of the beholder. Ultimately this path is self-defeating because it makes obsolescent the things (us) it is supposed to be helping and even then with questionable rate of return for solution builders, at least in the early stages.
The compensatory principle
In the second class, you separate what is best done by machines (repetitive, data-driven tasks, requiring 24-7 operation, dangerous tasks, tasks requiring more than human strength or precision, …) from what is best done by humans (improvisation, flexibility, adaptability, judgment, …). Man and machine compensate for each others respective weaknesses. This should be a good guide in principle though it seems that many, perhaps most tasks do not break down so cleanly into these two categories, as is clear when you consider recent progress in vision automation. This area has seen a lot of success but progress extends less clearly to complex action consequences. Braking to avoid hitting an object is comparatively easy but if there isn’t sufficient stopping distance, choosing from the next set of options (collide anyway at lower speed, turn to avoid, thus possibly hitting something else, ..) may not always be so easy to rank-order. This path is useful case-by-case but but doesn’t provide a larger guiding philosophy.
The complementarity principle
In this final class in the article, you look at automation as a way to complement us, to extend what we can do, not a way to replace us (unless whatever you do is easily automated). In other words, automation should be more like Iron Man, not Ultron. The author brings up an interesting value for this approach, illustrated by a system he and others created to take a (hardware) system out of a cloud, send it for repair and later recommission the repaired system back into the cloud. In this case, the automation was treated as an extension to the team, working in areas it was told to work, avoiding systems it was told to leave alone and filing problem tickets where it became confused and did not know how to proceed. Over time the team learned and refined the system and were dealing with less cases manually, but never fully disengaged – they continued to learn as they refined the system and perhaps (my view) could only asymptotically move towards full automation.
For tasks on an assembly line, whether in a factory or an office, you don’t need an Iron Man, you need an Ultron. But this automation chips away only at the lower rungs of labor, as has always been the case (there really is nothing truly new under the sun). For anything higher up, we need more Iron Man suits, not more Ultrons.
You can access the CACM article HERE. Sorry you have to have a subscription or you have to buy the article.
A Better Way for Analog Designers to Perform Variation Analysis
The impact of process variation at advanced nodes is increasing — no surprise there. In recent years, the principal design emphasis to better reflect this variation has been the adoption of two new methodologies: (1) advanced on-chip variation (AOCV, as well as POCV/LVF) for digital static timing analysis, and (2) advanced statistical analysis and Monte Carlo methods, including high-sigma Monte Carlo analysis.
High-sigma Monte Carlo has been adopted for applications where circuit performance and reliability requirements necessitate results beyond a traditional 3-sigma yield. Although high-sigma Monte Carlo methods are most often used in memory array analysis, a growing proportion of analog designers are also using high-sigma Monte Carlo verification to meet their customers’ performance and yield requirements. Whereas memory circuits require 6-sigma analysis to estimate the failure rate and confirm a suitable yield for the vast number of bitcells integrated on-die, analog designs require 6-sigma analysis to achieve the extreme reliability and yield requirements necessary for products upon which human life depends or where extreme environmental conditions are present — such as medical and automotive applications.
The team at Solido Design Automation has focused on optimization of Monte Carlo methodologies, with sophisticated algorithms to provide process variation analysis results that are both accurate and efficient. Their parameter sampling approaches cover two regions: (1) the 3-sigma region, where historically analog designers have concentrated the majority of their statistical simulation efforts, and (2) the high-sigma region, which has become more accessible to designers of all types in recent years due to advanced technology like Solido’s High-Sigma Monte Carlo. Solido’s high-sigma approach minimizes the number of Monte Carlo circuit simulations required to provide extreme statistical distribution data, which having specific testcase parameter detail for design exploration and optimization.
I recently spoke with members of the Solido team about features in the latest Version 4 release of Variation Designer. For memory designers, one of the key enhancements in this release is the Hierarchical Monte Carlo support for high-sigma array analysis — a brief summary of that discussion is available here.
Then, the Solido team discussed another new feature in Variation Designer — Statistical PVT.
They highlighted, “Digital library IP designers are used to dealing with process variation in terms of a fast/slow global corner, at best-case/worst-case voltage and temperature conditions. The (correlated) local variation around that global definition is used to verify setup/hold timing checks and array yield. Yet, that method won’t suffice for analog IP designers, whose designs can’t reliably be bounded by fixed fast/slow corners. What is a ‘fast’ gain, or a ‘slow’ bandwidth? Analog designers need design-specific, technology-specific, measurement-specific corners that correctly capture the bounds of their circuit specifications.”
Solido’s Variation Designer now offers Statistical PVT, in which fixed digital corners are supplanted by accurate analog statistical corners. Unlike the traditional approach of simulating combinations of fixed process, voltage, and temperature conditions and then also running Monte Carlo simulation, Statistical PVT combines Monte Carlo and PVT simulation to extract design-specific statistical corners and verify those across voltage, temperature, and other environmental conditions. This results in a more accurate and efficient analog variation analysis. (Actually, the “temperature inversion” characteristic of FET devices at advanced nodes increasingly impacts digital circuit performance, as well — Statistical PVT may not be solely of interest to analog designers.)
The figure below illustrates a setup screenshot from the application, which includes an extended sampling space for Spice simulations.
Analog IP typically incorporates a diverse set of additional on-chip components — e.g., R’s, C’s, diodes. In addition to applying variation to digital FF/SS MOS corners, Statistical PVT determines design-specific, technology-specific, and measurement-specific variation corners for the desired yield using variation models for each of these components. The following figure highlights how important it is to consider (passive) component variation, as well as device parameters. Considering only MOS devices fails to capture the possible variation present when other elements are included.
The sample sampling expertise used in the Solido HSMC methods is applied to an alternate method in Statistical PVT, to derive results representative of the 3-sigma performance with a reduced set of Monte Carlo simulations. For analog IP, the circuit simulation measurement specifications are vastly different than memory or cell library statistical characterization — e.g., gain, bandwidth, phase margin, duty cycle. The Solido team reminded me that their sampling optimization methodology is agnostic — “if you can measure it, we can analyze it” is their credo.
A key facet to statistical analysis is the evaluation and debug of post-simulation results.
The figure above illustrates the post-simulation user interface for a number of analog specification measurements. Note that the Solido results are not an extrapolation of a model or a brute-force exploration of the entire PVT space, but rather a specific set of simulation testcase parameters for the designer to examine in detail. Design optimization requires this testcase parameter detail, to help identify the circuit elements (and parasitics) to address. Although the description above uses an analog block for illustration, Statistical PVT is certainly applicable to RF circuits, too.
Key to analog IP design productivity is the Design History results view in Variation Designer, to provide the required perspective on the iterative optimization progress. The figure below illustrates the Design History user interface for a set of Statistical PVT runs and their corresponding revisions.
With an increasing breadth of application markets for advanced semiconductor processes — e.g., automotive, mil/aero, medical (and health-related IoT devices) — the SoC reliability requirements are demanding. Analog/RF IP validation requires a comparable simulation solution to High-Sigma Monte Carlo, as array and cell library designs have successfully applied. Solido’s Statistical PVT application within Variation Designer fits that need.
For more information on Statistical PVT in Variation Designer, please follow this link.
-chipguy
Is Elon Musk from the Future?
One of the more annoying (ie. delightful) things about Tesla Motors is the way the company casually disrupts long established auto industry business models. Whether it is vehicle sales and service or overcoming EV range anxiety or using your car to as an extension of the power grid or letting your car drive itself.
The latest twist from Tesla, revealed in Tesla owner posts on Facebook, is a one-month free trial of Autopilot mode. The function is enabled within 30 seconds if you choose to take it.
Tesla began making cars in 2014 with the Autopilot capability built in. The feature was available as part of a convenience package with emergency braking and side collision avoidance. For $2,500 at the time of purchase, the Model S owner could add active cruise control and automatic highway steering.
Tesla buyers not choosing the option at the time of purchase can activate it later for $3,000. But Tesla has gone one step further with the free trial. The simplicity of the offer disguises its mind-blowing possibilities and the tragic implications for traditional auto makers.
Mind-blowing possibilities
With the Autopilot free trial Tesla is demonstrating what advanced driver assist technology analysts have been pointing out for quite some time.
Camera-based sensors on cars can be used for multiple purposes including everything from detecting driver inattention to enabling collision avoidance, lane keeping, blind spot detection, self-parking, all-around views of the vehicle, emergency braking and adaptive cruise control.
Once the sensors, including radar and sonar, have been added to the car at the factory the process of turning on features may not even require a software “download.” It may only require an update to deliver the latest algorithms along with a “switch” to activate the software which is already on-board in the car.
The power of the free trial strategy for safety features lies in the ability to tease and delight customers with safety features that might not normally be selected at the original vehicle purchase. Many of these features require demonstration, something the average car buyer these days simply doesn’t make time for. But as a free trial, Tesla has opened the door to pushing and promoting safety enhancements long after the original sale of the car.
The insurance-related opportunities are endless here. Sponsored safety anyone? “Download or turn on this safety feature and we’ll give you a discount on your insurance.” “Collision avoidance brought to you by State Farm and Mobileye.” “Ten percent off your premium as long as you keep the feature turned on.”
But why stop at safety, what about adding performance features and different suspension setups for days spent at a local race track? What about temporarily turning features on for long trips – yes, that’s right, on-demand safety or safety as a subscription service?
It’s enough to make one wonder: Is Elon Musk from the future?
Tragic implications
For the incumbent car maker community, Tesla’s free trial proposition along with his huge head start on over-the-air (or, really, over Wi-Fi mainly) software updates and now remote function unlock is tragically embarrassing. The highly silo-ed structure of the typical auto maker with its hide-bound engineering practices (ie. “You can’t do that.”) are virtually incapable of responding to the Tesla value proposition and disruption.
For the typical auto maker, safety systems, infotainment systems and communications gateways are managed by different and sometimes competing departments. Even worse, sometimes these departments compete with, resent or otherwise struggle between themselves riven as they are by conflicting technology life-cycles, business models, and marketing priorities.
Like an alien saucering into the automotive market, Tesla’s CEO Elon Musk continually brings news of the future. An Autopilot free trial is only the latest case of aftersales delight from Tesla. But the implications for a car that gets safer and sexier over time is devastating.
What’s next from Tesla? Greater driving range on demand? New cloud services on the fly? Aftermarket hovercraft mode? Next time you run into Elon, don’t forget to say: “Klaatu barada nikto.”
Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk
Semiconductor Merger Mania Explained!
Next week is the Mentor U2U Conference in Silicon Valley. By chance I had coffee with one of the U2U keynote speakers while we were waiting for the FD-SOI Symposium to start last week and can tell you this FREE event is one you don’t want to miss:
Continue reading “Semiconductor Merger Mania Explained!”
Dr. Evil and On-Chip "LASERS" for Silicon Photonics
In the 1999 comedy, The Spy Who Shagged Me, Dr. Evil laments about why he can’t have sharks with “laser beams” attached to their heads. I get the feeling that silicon photonic designers sometimes feel the same way about why they don’t yet have integrated on-chip laser light sources. While off-chip light sources have good light-emitting efficiency and thermal stability they suffer from relatively large coupling losses between the laser and the photonic IC (PIC) and higher packaging costs. At ITC 2015 W.R. Bottoms presented on ensuring reliability in the era of heterogeneous integration (see paper here). In his presentation he stated that 2015 was the year in which the number of mobile-connected devices first exceeded the number of people on the earth. He went on to project that broadband speeds need to more than double by the year 2019 and that in order to do this our concept of network architectures will need to change. Key to that change will be the movement of network photonics closer to the chip level.
On-chip light sources have the potential for moving photonics onto the chip itself promising higher integration density, compact size and better energy efficiency. Unfortunately, silicon(Si) is an indirect band gap semiconductor and is very inefficient at light generation. This has caused the on-chip light source to be one of the last lagging components of a truly integrated photonics solution. Companies like Luxtera have been successful using off-chip light sources in telecom markets but lack of progress on an on-chip light source is currently limiting the progress of chip level optical interconnect technology. According to an article published in Light Sciences and Applications, an ideal on-chip light source should be able to emit light at 1310 or 1550nm wavelengths to connect directly to the external fiber optical networks, lase under electrical pumping for compact size & high integration density, display high power efficiency for sufficient output power and low energy cost-per-bit transmission and be able to integrate on Si with CMOS compatible fabrication techniques for large scale manufacturing. The paper reviews three most likely solutions for an on-chip light source, those being Erbium (Er) related light sources, Germanium-on-Si lasers and III-V-based hybrid Si lasers. Table 1 from the article lists these light source candidates with their advantages and disadvantages.
While good progress has been made on ER-doped fiber amplifiers and lasers (EDFAs/EDFLs) they have yet to make the jump to electrically pumped lasers, one of the key criteria for an on-chip light source so for now Er is not on the short term horizon.
Germanium (Ge) is an interesting candidate for on-chip lasing in that it is the material most closely matched to Si, to the point that it too is an indirect band gap material. However, Ge is different from Si in that it exhibits a pseudo-direct band gap behavior that enables it to emit light of approximately the magical 1550nm wavelength. Much research exists around what is known as band gap engineering with the idea to modify the band structure of Ge enough to effectively turn it into a direct band gap material. Good progress has been made to this end using strategies such as enhanced n-type doping to fill-up the valence band with electrons used for lasing, and using tensile strain and alloys of Ge and Tin (Sn) to shrink the band gap to enable efficient lasing.
One of the main challenges is to establish a trade-off between these strategies in terms of optimizing the performance of a Ge laser while also avoiding operating wavelength redshift, an artifact of narrowing the bandgap. An additional challenge yet to be overcome is the relatively high threshold current density required for Ge lasers. Challenges notwithstanding, Ge’s large gain spectrum and ability to work at high temperatures makes it very attractive in wavelength division multiplexing (WDM) systems and high-density optical-electrical ICs. Additionally, Ge is also widely used for modulation and detection and therefore could simultaneously address all of these areas in a monolithic integrated SiGe-based photonic platform while maintaining compatibility within a CMOS process flow needed to reduce process complexity and cost.
In the meantime, III-V-based hybrid Si lasers using various bonding techniques currently represent the most practical on-chip silicon photonic light sources. These lasers however suffer from poor heat dissipation due to the high thermal resistance of the bonding layers. Given this, these types of lasers may not be suitable for large-scale dense monolithic integration in terms of yield and cost over the long term. The alternative with growing momentum is high-quality quantum dot (QD) materials that have been successfully grown on Si using direct hetero-epitaxial growth (III-V QDs). These III-V lasers have been demonstrated to maintain lasing operation at up to 120 °C with low threshold current densities of 62.5 A/cm[SUP]2[/SUP]. Monolithically grown on Si, they could be more promising as on-chip lasers, and may satisfy the requirements for low-cost, high-yield, temperature-insensitive, and large-scale high-density monolithic integration.
So what would Dr. Evil have done with an integrated on-chip “laser”? Strapped it onto the head of “Mini-Me” of course!
Single Electron Transistors; the Single Answer?
According to a press release made last year by Gartner, “the world’s leading information technology research and advisory company,” there is projected to be nearly 21 billion internet connected devices by the year 2020 [1]. With the Internet of Things’ ever growing list of network connected devices, the demand for more compact, more cost effective, and more power efficient microprocessors is at an all time high and will only continue to grow. In order to keep up with this demand, engineers across multiple continents have begun to research the next generation of microscopic transistors. A recent project titled “Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology”(IONS4SET), coordinated by Helmholtz-Zentrum Dresden-Rossendorf, is exploring one possible answer to this demand that comes in the form of single electron transistors.
Single electron transistors, referred to as (SETs), like the more common field effect transistors (FETs) are a “three terminal switching device” [2]. Both SETs and FETs have a source and a drain terminal, whose connection to one another is controlled by a signal on the gate, however, the similarities begin to end there. In addition to gate, source, and drain, SETs also have a quantum dot, called the island, in the center with an insulating barrier known as the tunneling junction on either side, creating a barrier between the island and the source and drain. When a capacitance is created on the gate and thus a capacitance on the island, it raises the electron’s energy above the coulomb blockade energy, allowing the quantum phenomenon known as Tunnel Effect to occur, transferring (as the name suggests) a single electron from the source to the drain through the tunneling junctions [2]. The design is in contrast to the many, many electrons that are simultaneously allowed to flow from source to drain in a field effect transistor.
Because SETs only manipulate one electron at a time, single electron transistors offer two very promising advantages over transistors in use today. The first being, the incredibly small size. Current generation transistors in production today by Intel are 22nm with 14nm arriving in the near future, on the other hand, the SETs being developed by the IONS4SET group using their “bottom-up self assembly process” for fabrication are achieving feature sizes of approximately 2 nm [3]. With a decrease in size there is a decrease in power consumption. SETs with feature sizes of only a few atoms take an astonishing little amount of power to function. SETs small size and low power consumption are what make them so promising, with two-thirds of the holy trinity of transistors(smaller size, lower power consumption, and lower cost), SETs are well on their way to being a favorite of manufacturers to use in their products.
While very promising, SETs do not operate with impunity. SETs are very sensitive to thermal noise, meaning in their current state they are incapable of operating at room temperature requiring a very low temperature operation of 4 to 2 kelvin. Another major obstacle in SET implementation is its incompatibility with current CMOS logic. Current CMOS technology has a voltage threshold that must be met before normal operation is possible and also require, when compared to SETs, a relatively large amount of power. Current SETs are so low power that transfer of energy beyond itself is very difficult and is too weak to interact with CMOS. In order to bridge the gap between SET and MOSFET the signal from the SET must be amplified to a level suitable for MOSFETs, which in itself is difficult, requiring “very sensitive MOSFET transistors” [4]. A way around this amplification process would be to create an all new logic based on the single electron transistor and its quantum functions, but this is still very far from being a viable option and wouldn’t help the compatibility issues already present.
Beyond the limitations of the SET itself is the issue of fabricating SETs on a large scale. The widely used lithographic and photolithographic fabrication methods are difficult to control at the resolution required to create the SETs [4]. A new fabrication method is one of the main goals of the IONS4SET project, potentially resulting in a new, reliable mass fabrication method with the precision needed, but not yet met by current methods.
There are various applications of Single Electron transistors . The primary implementation of SETs is in memory cells, as it utilizes quantum dots to store a large amount of information. Due to its incredibly small size of 2 nm, SETs allow more cells to be used in a small area thus lowering the power usage and making the circuit integration more effective . The SETs are also used as efficient charge sensors meaning it reads the charges of the qubits stored in the Quantum dot. By this process , the charge transition for both high and low conductance can be observed [5]. Due to its sensitive nature ,SETs can also detect infrared radiations; “By exciting electrons over an electrically induced energy barrier, both the range of detectable wavelengths and the sensitivity of the device can be controlled” [6]. Other applications also include SET oscillators which is useful for radio frequency systems
The future of electronics relies on the production of smaller and more efficient transistors. Engineers are working hard to discover the next great advancement in transistor design and fabrication to meet the growing demand. Single electron transistors offer one promising path leading to that advancement, but there is still a long way to go. It has to overcome difficulties in production, as well as, problems with implementation with current technology. Even still, the future is very bright for single electron transistors hopefully leading to new microscopic transistors making it possible to connect the new, vast array of future devices.
By Maisha Sadia and Beau McCarty
Sources cited
[1]R. van der Meulen, “Gartner Says 6.4 Billion Connected ‘Things’ Will Be in Use in 2016, Up 30 Percent From 2015,” “Things” Will Be in Use in 2016, Up 30 Percent From 2015, 10-Nov-2015. [Online]. Available at: http://www.gartner.com/newsroom/id/3165317. [Accessed: 23-Feb-2016].
[2]V. P. Singh, A. Agrawal, and S. B. Singh, “Analytical Discussion of Single Electron Transistor (SET),” International Journal of Soft Computing and Engineering(TM), 03-Jul-2012. [Online]. Available at: http://www.ijsce.org/. [Accessed: 23-Feb-2016].
[3]H.-Z. D.-R., “Ion-irradiation-induced Si Nanodot SelfAssembly for Hybrid SET-CMOS Technology,” Ion-irradiation-induced Si Nanodot SelfAssembly for Hybrid SET-CMOS Technology, 02-Aug-2016. [Online]. Available at: https://www.hzdr.de/db/cms?poid=45667.
[4]D. AGUIAM and O. B. R. E. C. Z. Á. N. Vince, “A Brief Introduction to Single Electron Transistors,” Tecnico Lisboa, 18-Dec-2011. [Online]. Available at: https://fenix.tecnico.ulisboa.pt/downloadfile/3779578912209/aguiam_obreczan__introset_nov2011.pdf. [Accessed: 23-Feb-2016].
[5]E. P. Nordberg, H. L. Stalford, R. Young, G. A. T. Eyck, K. Eng, L. A. Tracy, K. D. Childs, J. R. Wendt, R. K. Grubbs, J. Stevens, M. P. Lilly, M. A. Eriksson, and M. S. Carroll, “Charge sensing in enhancement mode double-top-gated metal-oxide-semiconductor quantum dots,” Appl. Phys. Lett. Applied Physics Letters, vol. 95, no. 20, p. 202102, 2009.
[6]A. Kumar and D. Dubey, “Single Electron Transistor: Applications and Limitations ,” Advance in Electronic and Electric Engineering, vol. 3, no. 1, 2013 pp. 57-62.
Intel Dinner Keynote – IOT Solutions: System scaling during the convergence of IT and OT
The Electronic Design Processes (EDP) 2016 Workshop and Symposium, in its 23rd year, has fostered the free exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry. It has provided a forum for this cross-section of the design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.
EDPS Symposium: IoT Workshop
SemiWiki-EDPS2016 promo code for a $50 savings
The EDPS was founded by Bill McCallah in 1978 as key activity of the Design Automation Technical Committee (DATC). This annual EDPS Workshop and Symposium takes place each year in Monterey, California, and emphasizes both the here and now and the future.
Attendees of this elite workshop have met each year since 1993. It has attracted some of the most far-seeing people in the electronics industry and academia as speakers. If you need to know where the industry is and where it’s going with respect to the design and development, and especially methodologies and technology of design, you should consider attending this year.
The dinner keynote this year is Ken Caviasca, Intel Vice President and GM of IOT Platform Engineering. Ken has the exciting role of developing a broad range of IOT systems from things to the cloud. The pace of innovation has never been faster with the advent of performance/cost scaling of 3 key attributes. Compute, Connectivity, and Data.
Dinner Keynote – IOT Solutions:
System scaling during the convergence of IT and OT
The multi-fold improvement in the prior attribute has given lift to new IOT solutions. IOT solutions span a wide range of markets, industries, and technologies. There are many real world improvements and problems which can be solved at technology solutions moves from people driven solutions to a “things” driven solutions. As this shift occurs there are several foundational capabilities that must scale across vendors and device performance levels. An additional challenge in these emerging IOT systems is to converge attributes of IT and OT as the systems enter the interface with physical systems. When IT and OT is blended correctly the best of both domains can be applied to solving real world problems in a cost effective, safe and reliable manner. This requires a cloud through edge capabilities that combine in a way to implement new systems. Systems that would have been too cost prohibitive to build only 5 years ago. Today we are building and deploying these IOT innovations which are improving efficiency, driving valued improvements to operations and people lives. It certainly is an exciting industry inflection point we are innovating in today.
Kenneth P. Caviascais vice president in the Internet of Things Group and general manager of platform engineering and development at Intel Corporation. He has overall responsibility for computing platforms targeted to the Internet of Things (IoT) market segment, including planning, architecture, user experience priorities, silicon definition, operating system porting, hardware, firmware, validation and manufacturing test. The IoT platforms developed by his team encompass product offerings based on Intel® Atom™, Intel® Core™ and Intel® Xeon® processors.
Since joining Intel in 1984 as a silicon engineer in automotive controllers, Caviasca has held various technical and management positions in flash microcontrollers, embedded devices, video signal processors, security devices, chipsets, network processors, server processors and manufacturing operation startup. Before assuming his current position, he managed platform development for the Intelligent Systems Group, overseeing hardware, validation and software integration development. Earlier in his Intel career, he managed silicon development for the Communication Infrastructure Group and led a team responsible for delivering system-on-chip, server-class and chipset products for the embedded and communications market segment.
Between 2008 and 2010, Caviasca’s development team won several premier supplier awards from industry-leading communications equipment suppliers. He and his team also won an Intel Achievement Award in 2004 for excellence in network processor development.
Caviasca earned his bachelor’s degree in computer and electrical engineering from the University of Bridgeport in Connecticut and his MBA degree from the W. P. Carey School of Business at Arizona State University. He holds seven patents in circuits, CPU and video systems architecture.
EDPS Symposium: IoT Workshop
SemiWiki-EDPS2016 promo code for a $50 savings
Debugging is the whole point of prototyping
The prototype is obviously the end goal of FPGA-based prototyping, however success of the journey relies on how quickly defects can be found and rectified. Winning in the debug phase involves a combination of methodology, capability, and planning. Synopsys recently aired a webinar on their HAPS environment and its debug ecosystem. Continue reading “Debugging is the whole point of prototyping”
Singularity, Semiconductors and Software
One of my all-time favorite movies is 2001 A Space Odyssey where one of the leading roles is an AI-based system aboard a spacecraft named Hal that is designed to be a perfect machine yet makes a mistake and then cascades into assaulting and eliminating the human crew members. The future time when semiconductors and software combine to create a machine intelligence that outpaces humans has become known as “the singularity“, a phrase coined by Ray Kurzweil now the Director of Engineering at Google.
In my lifetime we have seen domain-specific software and hardware systems that defeat humans in many tasks, like:
- Chess
- Backgammon
- Poker
- Go
- Jeopardy
- Blackjack
- Stock market trading
One very positive life impact with decreasing costs of semiconductors coupled with higher processing speeds has been in the area of sequencing DNA, where the cost per Genome has gone from $100M in 2001 to just about $1K in 2016, a rapid decline in price greater than the improvement in Moore’s Law:
Source: National Human Genome Research Institute
Should we be fearful of AI based systems?
Even Stephen Hawking is cautionary about AI when he endorsed an open letter along with other world influencers:
Autonomous weapons are ideal for tasks such as assassinations, destabilizing nations, subduing populations and selectively killing a particular ethnic group. We therefore believe that a military AI arms race would not be beneficial for humanity. There are many ways in which AI can make battlefields safer for humans, especially civilians, without creating new tools for killing people.
IJCAI 2015 Conference
In health care we certainly want the best diagnosis, which may include scanning our DNA, reviewing our medical history, and analyzing our vital signs using an AI-based system instead of a doctor. The only downside of giving machines and software access to health records is the whole area of data privacy and opening ourselves up to the risks of hacking.
Many industries are undoing fundamental change as automation is used to relieve labor-intensive tasks like: printing, fast-food order taking, etc. Just take a look at the steady decline in number of employees per print shop since 1998 as they use more automated approaches, requiring fewer humans:
Imagine what could happen with the trucking industry where autonomous vehicles could help cut operating costs by 50% during the vehicle’s lifetime of 600K miles, replacing or augmenting human drivers to improve safety, avoid accidents and shorten deliver times.
Leading automotive companies like Tesla are now able to update their electric vehicles wirelessly to add new features like Autopilot. This feature allowed a Tesla owner to drive across the US in under 60 hours by using Autopilot 96% of the trip.
What’s your plan to stay ahead of a machine replacing your job? When I started out doing IC design we did manual DRC (Design Rule Checking), but now that task is quite automated by software, so that freed me up to be more creative on the circuit design decision.
Our society needs to adapt to the coming challenges and prepare our children to do things that AI and machines cannot do. Mr. Kurzweil predicted that the singularity could arrive as soon as 2045, a scant 29 years from now, so make your own plans accordingly.