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ARM and FD-SOI are like Peanut Butter and Jelly!

ARM and FD-SOI are like Peanut Butter and Jelly!
by Daniel Nenni on 04-19-2016 at 4:00 pm
Categories: Arm, FD-SOI, Foundries, GlobalFoundries, Samsung Foundry

When I first heard about a foundry possibly licensing FD-SOI I would have bet it was SMIC in China. What better market for a low cost, low power, easy to manufacture alternative to FinFETs? The foundry of course was Samsung which also made complete sense since they have 28nm gate-first capacity that matches up nicely to 28nm FD-SOI. Same thing goes for GlobalFoundries and the Dresden Fab with gate-first 28nm capacity ready to be converted to 22nm FD-SOI.

Instead of taking the short road to FD-SOI, SMIC will take the long road to 14nm FinFETs and in my opinion they will fail miserably yet again. Seriously, how competitive will a first generation 14nm FinFET process be in 2020? Remember, third generation FinFETs will hit the new Nanjing TSMC fab in 2018.

The other bet I lost was on FD-SOI and ARM. For the life of me I have no idea why ARM did not champion FD-SOI from the very beginning. Seriously, what better fit for FD-SOI than ARM IP and IoT? That all changed at the FD-SOI Symposium in San Jose last week. Will Abbey of ARM presented “Realize the Potential of FD-SOI in Growing Markets”with the opening line “An honest confession is good for the soul, but not for the reputation”. The quote originated from Thomas Robert Dewar, 1st Baron Dewar founder of the Scottish whisky distiller by the way.

Will Abbey admitted that ARM had been on the FD-SOI sidelines before presenting data from a skunk works project that had never been seen before. Unfortunately his slides are not on the FD-SOI Symposium website as of yet (hopefully they will be soon) but I did get a picture of the summary slide:


Another presentation worth viewing that is not up yet is “Enabling Next Generation Semiconductor Product Innovations with 22FDX”by Subramani Kengeri, VP CMOS Business Unit, GLOBALFOUNDRIES“. Fortunately Subi and I go way back so he gave me his slides. You can find them HERE.

I was at the 22FDX Launch in Dresden last year and was very impressed not only by the technology, but also by the conservative approach of the launch. Everything I was told in Dresden is right on schedule according to the PDK releases I have seen thus far so congratulations to GF and I look forward to the official 22FDX HVM launch in 1H 2017 as planned, absolutely.

An interesting note, in looking at the many badges on the table I did not see anyone from SMIC or UMC which is a mistake. I did see people from TSMC so that was interesting and lots of people from the fabless semiconductor ecosystem. More badges that I could easily count actually, it was standing room only.

Another interesting note, the EDA, IP, and ASIC companies I know and love are fully behind FD-SOI so it is not just press release fluff going around. I have counted close to 100 FD-SOI tape-outs that are in progress and a dozen or so of those have already taped-out (Samsung 28nm FD-SOI) so I hereby declare 2017 the year of FD-SOI HVM!

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IOT Security Trends – Is the online world more dangerous??

IOT Security Trends – Is the online world more dangerous??
by Bill McCabe on 04-19-2016 at 12:00 pm
Categories: IoT, Security

Security threats are the biggest concern among the main concerns on the Internet of Things. Due to its very nature, it is a target of interest for those who want to commit either industrial or national espionage. By hacking into these systems and putting them under a denial of service, or other attacks, an entire network of systems can be taken out. This has caused cyber criminals to become very interested in the IoT and the possibilities that surround its misuse

Fortunately, companies are realizing that there are many potential problems with their framework. This has caused a new trend of companies reviewing these areas and coming up with an effective solution. Until that is done, those using these devices should remain wary. The IoT allows devices to exchange contextual information and to execute certain decisions based on this information. This means cars, homes, power supplies, and even water supplies using the IoT could potentially be at risk. In these cases, physical security is irrelevant, as a simple change of data could impact the control of systems and cause them to function as a dangerous item.

The idea of a security breach through the IoT isn’t something that is a possibility that could happen either. There are already cases of hackers breaking into the systems. Two cars were hacked, their brakes were disabled, and the lights turned off. All without the driver having the ability to control them in a test situation. Another instance of a yacht being taken off course by a hijacked GPS system is another.

Even in the home, people are at risk. Devices that have video cameras, children’s monitors, and similar devices that should be safe are actually giving hackers the chance to cause havoc in the home. Smart wired homes are having their temperature settings and lights flickering on and off, as these hackers explore the possibilities that are out there. Even the latest electric power meters that are digital are allowing hackers to steal power with ease.

But these device annoyances aren’t where the heart and soul of the IoT lies. Instead, it is the possibility of what can be done with these systems. Since everything is attached through the internet, these devices have the potential to perform a third party attack on websites. If millions of devices hit a website at the same time, it can overwhelm the bandwidth and potentially take down a competitor’s website, effectively crippling them until they find a workaround solution. Corporate espionage becomes a real concern as competition realizes they can turn simple devices against their main competition and draw in their business

All this means that the virtual world has the ability to have an impact on the physical world. The solution right now is to boost security on our devices that use the IoT. With added security tools and advanced API that can detect usage that goes beyond what the system is designed to do, there is a lower risk for the world.

With terrorism one of the main concerns in the world, and growing dangers around us, we need to be smart how we use technology. That’s why when we look at the IoT that we don’t write these devices off as being nothing more than simple tools to make our lives easier, but recognize them for the potential dangers they could also possess.

For more information about looking for IOT/Security Talent check our our website at www.internetofthingsrecruiting.com

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A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs
by Pawan Fangaria on 04-19-2016 at 7:00 am
Categories: Defacto Technologies, EDA

In one of my whitepapers “SoCs in New Context – Look beyond PPA”, I had mentioned about several considerations which have become very important in addition to power, performance, and area (PPA) of an SoC. This whitepaper was also posted in parts as blogs on Semiwiki (links are mentioned below). Two important considerations mentioned in that whitepaper were ‘Target Segment’ and ‘IP integration’ from a design standpoint.

Considering the possibility of several segments within a single market, for example desktop, laptop, tablet, and even smartphone in computing market, imagine how many variations of an SoC or IP within it may be required. A desktop processor can be less power efficient than a tablet or smartphone processor, but needs to be highly efficient in performance.

The IP selection and integration can be more complex than we can perceive. Now a day, among a suite of standard IP blocks for particular functionalities, there can be further customization in each IP to match a particular operating environment, thus introducing differentiation in an IP. Also, IP development environments can vary with different vendors.

It’s evident that these design requirements for SoCs and IP in modern context necessitate design platforms to be versatile enough to support development and integration in multiple environments. The design platforms must be supported with multiple language APIs for development of custom applications. It’s impressive to see this innovative design framework coming up to satisfy such critical requirements for the chip design industry; designers are no longer stuck with one proprietary or standard/popular language.


Defacto Technologies’ STAR platform provides a unique multi-language API development environment that offers the user to choose a language best suited for a particular task. While scripting languages such as Tcl, Perl, or Ruby are well-suited for tool integration, traditional programming languages along with complex data-structures and algorithms are used for application development, performance enhancement, and optimization of resources. The STAR platform is fully equipped for development of new applications as well as integration with existing tools and flows.

The STAR platform provides a differentiated solution for custom design automation that can be used for development of stand-alone applications as well as plug-ins. The key salient features in the STAR platform include –

  • Unified (HDL format agnostic) APIs for design exploration and editing

    • Extended support for SystemVerilog and VHDL data types
    • Mixed language support
    • Mixed gate-level and RTL support
  • Handling of design hierarchy with queries and editing
  • Advanced APIs for connectivity handling (bundle, slice, bit blasted views) through hierarchy
  • File list support for simplified HDL input management
  • Add-on libraries (Tcl, Perl, Java, etc.) with sample applications


The STAR Application Development Environmentin STAR platform is an extensive software framework with multiple sets of libraries including Perl, Python and Java. It is supported with language independent and persistent data-structures.

By using the STAR platform designers can create, explore, modify, and verify RTL designs within the same design flow. This is an ideal platform for fast design prototyping as well as development of complete new applications in shortest possible time.

Major semiconductor design companies across the globe built their custom tools on top of the STAR platform that enabled them to accelerate their design completions through seamless design flows from start to finish. A typical flow of tasks integrated on STAR platform by these design companies include –

  • Design metrics and SoC topology extraction
  • IP assembly at sub-system or top level
  • Automatic design hierarchy restructuring based on physical design constraints
  • Power aware driven design partitioning
  • Feedthrough insertion to accommodate channel-less physical implementation
  • Verification of structural connections including clock, I/O, and other connections

With Defacto’s solution, the design houses can quickly build their customized yet versatile development and integration environment for a variety of SoCs catering to different target segments. Different versions of PPA optimized IPs from various heterogeneous environments can be integrated with ease on a single development platform. And design restructuring can be done automatically to keep the RTL in sync with physical implementation, thus reducing verification and debug cycles. The STAR RTL platform is sure to improve designers’ productivity and is proven through working silicon in several semiconductor companies.

Defacto Technologies has a booth #1129 at 53[SUP]rd[/SUP] DAC in Austin, Texas. Visit them to know more about their innovative technology in design automation with the STAR platform.

Refer the following blogs to know more about new requirements of modern SoCs –
SoCs in New Context Look beyond PPA
SoCs in New Context Look beyond PPA – Part2

More Articles from Pawan

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Get ready for hypergrade in automotive

Get ready for hypergrade in automotive
by Don Dingee on 04-18-2016 at 4:00 pm
Categories: Automotive, IP, Sidense

With use cases expanding, the meaning of “automotive qualified” semiconductors is changing. What we’re now hearing about now is beyond the AEC-Q100 Grade 0 upper end of 150°C, while still meeting other reliability, retention, and security requirements. What does hypergrade mean for complex digital chip designs moving forward? Continue reading “Get ready for hypergrade in automotive”

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More on the Practical Uses of Automation

More on the Practical Uses of Automation
by Bernard Murphy on 04-18-2016 at 12:00 pm
Categories: General

There’s a good article in the March issue of the Communications of the ACM which follows a theme I commented in my “One, Two Many” post. But the CACM article has a better title: “Automation should be like Iron Man, not Ultron”.

For anyone who hasn’t seen the movies, Iron Man is a man (Tony Stark) who has built a suit to enhance his abilities. Ultron is an automaton, made in a similar form to the Iron Man suit but not requiring a human operator. Of course the CACM article doesn’t use the movie as an argument – that would be silly. What the author (Tom Limoncelli) does is to talk about different classes of automation and why one class may ultimately prove superior to the others.

The leftover principle
This is the first class – automate the easy stuff and leave the hard stuff to the humans. A problem with this is that what’s leftover gets progressively harder and within the abilities of only a small number of people. Also we develop skills to solve harder problems while we are solving easier problems. Take away the easy problems and our general problem-solving skills deteriorate. In the limit, this is the Ultron approach. There’s another problem he didn’t mention. The economics of solving easy problems are not very attractive because we don’t assign much value to solving easy problems. Of course as the problems get harder they should gain value, but difficulty is in the eye of the beholder. Ultimately this path is self-defeating because it makes obsolescent the things (us) it is supposed to be helping and even then with questionable rate of return for solution builders, at least in the early stages.

The compensatory principle
In the second class, you separate what is best done by machines (repetitive, data-driven tasks, requiring 24-7 operation, dangerous tasks, tasks requiring more than human strength or precision, …) from what is best done by humans (improvisation, flexibility, adaptability, judgment, …). Man and machine compensate for each others respective weaknesses. This should be a good guide in principle though it seems that many, perhaps most tasks do not break down so cleanly into these two categories, as is clear when you consider recent progress in vision automation. This area has seen a lot of success but progress extends less clearly to complex action consequences. Braking to avoid hitting an object is comparatively easy but if there isn’t sufficient stopping distance, choosing from the next set of options (collide anyway at lower speed, turn to avoid, thus possibly hitting something else, ..) may not always be so easy to rank-order. This path is useful case-by-case but but doesn’t provide a larger guiding philosophy.

The complementarity principle
In this final class in the article, you look at automation as a way to complement us, to extend what we can do, not a way to replace us (unless whatever you do is easily automated). In other words, automation should be more like Iron Man, not Ultron. The author brings up an interesting value for this approach, illustrated by a system he and others created to take a (hardware) system out of a cloud, send it for repair and later recommission the repaired system back into the cloud. In this case, the automation was treated as an extension to the team, working in areas it was told to work, avoiding systems it was told to leave alone and filing problem tickets where it became confused and did not know how to proceed. Over time the team learned and refined the system and were dealing with less cases manually, but never fully disengaged – they continued to learn as they refined the system and perhaps (my view) could only asymptotically move towards full automation.

For tasks on an assembly line, whether in a factory or an office, you don’t need an Iron Man, you need an Ultron. But this automation chips away only at the lower rungs of labor, as has always been the case (there really is nothing truly new under the sun). For anything higher up, we need more Iron Man suits, not more Ultrons.

You can access the CACM article HERE. Sorry you have to have a subscription or you have to buy the article.

More articles by Bernard…

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A Better Way for Analog Designers to Perform Variation Analysis

A Better Way for Analog Designers to Perform Variation Analysis
by Tom Dillinger on 04-18-2016 at 7:00 am
Categories: EDA, Solido

The impact of process variation at advanced nodes is increasing — no surprise there. In recent years, the principal design emphasis to better reflect this variation has been the adoption of two new methodologies: (1) advanced on-chip variation (AOCV, as well as POCV/LVF) for digital static timing analysis, and (2) advanced statistical analysis and Monte Carlo methods, including high-sigma Monte Carlo analysis.

High-sigma Monte Carlo has been adopted for applications where circuit performance and reliability requirements necessitate results beyond a traditional 3-sigma yield. Although high-sigma Monte Carlo methods are most often used in memory array analysis, a growing proportion of analog designers are also using high-sigma Monte Carlo verification to meet their customers’ performance and yield requirements. Whereas memory circuits require 6-sigma analysis to estimate the failure rate and confirm a suitable yield for the vast number of bitcells integrated on-die, analog designs require 6-sigma analysis to achieve the extreme reliability and yield requirements necessary for products upon which human life depends or where extreme environmental conditions are present — such as medical and automotive applications.

The team at Solido Design Automation has focused on optimization of Monte Carlo methodologies, with sophisticated algorithms to provide process variation analysis results that are both accurate and efficient. Their parameter sampling approaches cover two regions: (1) the 3-sigma region, where historically analog designers have concentrated the majority of their statistical simulation efforts, and (2) the high-sigma region, which has become more accessible to designers of all types in recent years due to advanced technology like Solido’s High-Sigma Monte Carlo. Solido’s high-sigma approach minimizes the number of Monte Carlo circuit simulations required to provide extreme statistical distribution data, which having specific testcase parameter detail for design exploration and optimization.

I recently spoke with members of the Solido team about features in the latest Version 4 release of Variation Designer. For memory designers, one of the key enhancements in this release is the Hierarchical Monte Carlo support for high-sigma array analysis — a brief summary of that discussion is available here.

Then, the Solido team discussed another new feature in Variation Designer — Statistical PVT.

They highlighted, “Digital library IP designers are used to dealing with process variation in terms of a fast/slow global corner, at best-case/worst-case voltage and temperature conditions. The (correlated) local variation around that global definition is used to verify setup/hold timing checks and array yield. Yet, that method won’t suffice for analog IP designers, whose designs can’t reliably be bounded by fixed fast/slow corners. What is a ‘fast’ gain, or a ‘slow’ bandwidth? Analog designers need design-specific, technology-specific, measurement-specific corners that correctly capture the bounds of their circuit specifications.”

Solido’s Variation Designer now offers Statistical PVT, in which fixed digital corners are supplanted by accurate analog statistical corners. Unlike the traditional approach of simulating combinations of fixed process, voltage, and temperature conditions and then also running Monte Carlo simulation, Statistical PVT combines Monte Carlo and PVT simulation to extract design-specific statistical corners and verify those across voltage, temperature, and other environmental conditions. This results in a more accurate and efficient analog variation analysis. (Actually, the “temperature inversion” characteristic of FET devices at advanced nodes increasingly impacts digital circuit performance, as well — Statistical PVT may not be solely of interest to analog designers.)

The figure below illustrates a setup screenshot from the application, which includes an extended sampling space for Spice simulations.

Analog IP typically incorporates a diverse set of additional on-chip components — e.g., R’s, C’s, diodes. In addition to applying variation to digital FF/SS MOS corners, Statistical PVT determines design-specific, technology-specific, and measurement-specific variation corners for the desired yield using variation models for each of these components. The following figure highlights how important it is to consider (passive) component variation, as well as device parameters. Considering only MOS devices fails to capture the possible variation present when other elements are included.

The sample sampling expertise used in the Solido HSMC methods is applied to an alternate method in Statistical PVT, to derive results representative of the 3-sigma performance with a reduced set of Monte Carlo simulations. For analog IP, the circuit simulation measurement specifications are vastly different than memory or cell library statistical characterization — e.g., gain, bandwidth, phase margin, duty cycle. The Solido team reminded me that their sampling optimization methodology is agnostic — “if you can measure it, we can analyze it” is their credo.

A key facet to statistical analysis is the evaluation and debug of post-simulation results.

The figure above illustrates the post-simulation user interface for a number of analog specification measurements. Note that the Solido results are not an extrapolation of a model or a brute-force exploration of the entire PVT space, but rather a specific set of simulation testcase parameters for the designer to examine in detail. Design optimization requires this testcase parameter detail, to help identify the circuit elements (and parasitics) to address. Although the description above uses an analog block for illustration, Statistical PVT is certainly applicable to RF circuits, too.

Key to analog IP design productivity is the Design History results view in Variation Designer, to provide the required perspective on the iterative optimization progress. The figure below illustrates the Design History user interface for a set of Statistical PVT runs and their corresponding revisions.

With an increasing breadth of application markets for advanced semiconductor processes — e.g., automotive, mil/aero, medical (and health-related IoT devices) — the SoC reliability requirements are demanding. Analog/RF IP validation requires a comparable simulation solution to High-Sigma Monte Carlo, as array and cell library designs have successfully applied. Solido’s Statistical PVT application within Variation Designer fits that need.

For more information on Statistical PVT in Variation Designer, please follow this link.

-chipguy

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Is Elon Musk from the Future?

Is Elon Musk from the Future?
by Roger C. Lanctot on 04-17-2016 at 10:00 pm
Categories: Automotive

One of the more annoying (ie. delightful) things about Tesla Motors is the way the company casually disrupts long established auto industry business models. Whether it is vehicle sales and service or overcoming EV range anxiety or using your car to as an extension of the power grid or letting your car drive itself.

The latest twist from Tesla, revealed in Tesla owner posts on Facebook, is a one-month free trial of Autopilot mode. The function is enabled within 30 seconds if you choose to take it.


Tesla began making cars in 2014 with the Autopilot capability built in. The feature was available as part of a convenience package with emergency braking and side collision avoidance. For $2,500 at the time of purchase, the Model S owner could add active cruise control and automatic highway steering.

Tesla buyers not choosing the option at the time of purchase can activate it later for $3,000. But Tesla has gone one step further with the free trial. The simplicity of the offer disguises its mind-blowing possibilities and the tragic implications for traditional auto makers.

Mind-blowing possibilities
With the Autopilot free trial Tesla is demonstrating what advanced driver assist technology analysts have been pointing out for quite some time.

Camera-based sensors on cars can be used for multiple purposes including everything from detecting driver inattention to enabling collision avoidance, lane keeping, blind spot detection, self-parking, all-around views of the vehicle, emergency braking and adaptive cruise control.

Once the sensors, including radar and sonar, have been added to the car at the factory the process of turning on features may not even require a software “download.” It may only require an update to deliver the latest algorithms along with a “switch” to activate the software which is already on-board in the car.

The power of the free trial strategy for safety features lies in the ability to tease and delight customers with safety features that might not normally be selected at the original vehicle purchase. Many of these features require demonstration, something the average car buyer these days simply doesn’t make time for. But as a free trial, Tesla has opened the door to pushing and promoting safety enhancements long after the original sale of the car.

The insurance-related opportunities are endless here. Sponsored safety anyone? “Download or turn on this safety feature and we’ll give you a discount on your insurance.” “Collision avoidance brought to you by State Farm and Mobileye.” “Ten percent off your premium as long as you keep the feature turned on.”

But why stop at safety, what about adding performance features and different suspension setups for days spent at a local race track? What about temporarily turning features on for long trips – yes, that’s right, on-demand safety or safety as a subscription service?

It’s enough to make one wonder: Is Elon Musk from the future?

Tragic implications
For the incumbent car maker community, Tesla’s free trial proposition along with his huge head start on over-the-air (or, really, over Wi-Fi mainly) software updates and now remote function unlock is tragically embarrassing. The highly silo-ed structure of the typical auto maker with its hide-bound engineering practices (ie. “You can’t do that.”) are virtually incapable of responding to the Tesla value proposition and disruption.

For the typical auto maker, safety systems, infotainment systems and communications gateways are managed by different and sometimes competing departments. Even worse, sometimes these departments compete with, resent or otherwise struggle between themselves riven as they are by conflicting technology life-cycles, business models, and marketing priorities.

Like an alien saucering into the automotive market, Tesla’s CEO Elon Musk continually brings news of the future. An Autopilot free trial is only the latest case of aftersales delight from Tesla. But the implications for a car that gets safer and sexier over time is devastating.
What’s next from Tesla? Greater driving range on demand? New cloud services on the fly? Aftermarket hovercraft mode? Next time you run into Elon, don’t forget to say: “Klaatu barada nikto.”

Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

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Dr. Evil and On-Chip "LASERS" for Silicon Photonics

Dr. Evil and On-Chip "LASERS" for Silicon Photonics
by Mitch Heins on 04-17-2016 at 12:00 pm
Categories: Silicon Photonics

In the 1999 comedy, The Spy Who Shagged Me, Dr. Evil laments about why he can’t have sharks with “laser beams” attached to their heads. I get the feeling that silicon photonic designers sometimes feel the same way about why they don’t yet have integrated on-chip laser light sources. While off-chip light sources have good light-emitting efficiency and thermal stability they suffer from relatively large coupling losses between the laser and the photonic IC (PIC) and higher packaging costs. At ITC 2015 W.R. Bottoms presented on ensuring reliability in the era of heterogeneous integration (see paper here). In his presentation he stated that 2015 was the year in which the number of mobile-connected devices first exceeded the number of people on the earth. He went on to project that broadband speeds need to more than double by the year 2019 and that in order to do this our concept of network architectures will need to change. Key to that change will be the movement of network photonics closer to the chip level.

On-chip light sources have the potential for moving photonics onto the chip itself promising higher integration density, compact size and better energy efficiency. Unfortunately, silicon(Si) is an indirect band gap semiconductor and is very inefficient at light generation. This has caused the on-chip light source to be one of the last lagging components of a truly integrated photonics solution. Companies like Luxtera have been successful using off-chip light sources in telecom markets but lack of progress on an on-chip light source is currently limiting the progress of chip level optical interconnect technology. According to an article published in Light Sciences and Applications, an ideal on-chip light source should be able to emit light at 1310 or 1550nm wavelengths to connect directly to the external fiber optical networks, lase under electrical pumping for compact size & high integration density, display high power efficiency for sufficient output power and low energy cost-per-bit transmission and be able to integrate on Si with CMOS compatible fabrication techniques for large scale manufacturing. The paper reviews three most likely solutions for an on-chip light source, those being Erbium (Er) related light sources, Germanium-on-Si lasers and III-V-based hybrid Si lasers. Table 1 from the article lists these light source candidates with their advantages and disadvantages.


While good progress has been made on ER-doped fiber amplifiers and lasers (EDFAs/EDFLs) they have yet to make the jump to electrically pumped lasers, one of the key criteria for an on-chip light source so for now Er is not on the short term horizon.

Germanium (Ge) is an interesting candidate for on-chip lasing in that it is the material most closely matched to Si, to the point that it too is an indirect band gap material. However, Ge is different from Si in that it exhibits a pseudo-direct band gap behavior that enables it to emit light of approximately the magical 1550nm wavelength. Much research exists around what is known as band gap engineering with the idea to modify the band structure of Ge enough to effectively turn it into a direct band gap material. Good progress has been made to this end using strategies such as enhanced n-type doping to fill-up the valence band with electrons used for lasing, and using tensile strain and alloys of Ge and Tin (Sn) to shrink the band gap to enable efficient lasing.


One of the main challenges is to establish a trade-off between these strategies in terms of optimizing the performance of a Ge laser while also avoiding operating wavelength redshift, an artifact of narrowing the bandgap. An additional challenge yet to be overcome is the relatively high threshold current density required for Ge lasers. Challenges notwithstanding, Ge’s large gain spectrum and ability to work at high temperatures makes it very attractive in wavelength division multiplexing (WDM) systems and high-density optical-electrical ICs. Additionally, Ge is also widely used for modulation and detection and therefore could simultaneously address all of these areas in a monolithic integrated SiGe-based photonic platform while maintaining compatibility within a CMOS process flow needed to reduce process complexity and cost.

In the meantime, III-V-based hybrid Si lasers using various bonding techniques currently represent the most practical on-chip silicon photonic light sources. These lasers however suffer from poor heat dissipation due to the high thermal resistance of the bonding layers. Given this, these types of lasers may not be suitable for large-scale dense monolithic integration in terms of yield and cost over the long term. The alternative with growing momentum is high-quality quantum dot (QD) materials that have been successfully grown on Si using direct hetero-epitaxial growth (III-V QDs). These III-V lasers have been demonstrated to maintain lasing operation at up to 120 °C with low threshold current densities of 62.5 A/cm[SUP]2[/SUP]. Monolithically grown on Si, they could be more promising as on-chip lasers, and may satisfy the requirements for low-cost, high-yield, temperature-insensitive, and large-scale high-density monolithic integration.

So what would Dr. Evil have done with an integrated on-chip “laser”? Strapped it onto the head of “Mini-Me” of course!

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Single Electron Transistors; the Single Answer?

Single Electron Transistors; the Single Answer?
by Students@olemiss.edu on 04-17-2016 at 7:00 am
Categories: IoT

According to a press release made last year by Gartner, “the world’s leading information technology research and advisory company,” there is projected to be nearly 21 billion internet connected devices by the year 2020 [1]. With the Internet of Things’ ever growing list of network connected devices, the demand for more compact, more cost effective, and more power efficient microprocessors is at an all time high and will only continue to grow. In order to keep up with this demand, engineers across multiple continents have begun to research the next generation of microscopic transistors. A recent project titled “Ion-irradiation-induced Si Nanodot Self-Assembly for Hybrid SET-CMOS Technology”(IONS4SET), coordinated by Helmholtz-Zentrum Dresden-Rossendorf, is exploring one possible answer to this demand that comes in the form of single electron transistors.

Single electron transistors, referred to as (SETs), like the more common field effect transistors (FETs) are a “three terminal switching device” [2]. Both SETs and FETs have a source and a drain terminal, whose connection to one another is controlled by a signal on the gate, however, the similarities begin to end there. In addition to gate, source, and drain, SETs also have a quantum dot, called the island, in the center with an insulating barrier known as the tunneling junction on either side, creating a barrier between the island and the source and drain. When a capacitance is created on the gate and thus a capacitance on the island, it raises the electron’s energy above the coulomb blockade energy, allowing the quantum phenomenon known as Tunnel Effect to occur, transferring (as the name suggests) a single electron from the source to the drain through the tunneling junctions [2]. The design is in contrast to the many, many electrons that are simultaneously allowed to flow from source to drain in a field effect transistor.

Because SETs only manipulate one electron at a time, single electron transistors offer two very promising advantages over transistors in use today. The first being, the incredibly small size. Current generation transistors in production today by Intel are 22nm with 14nm arriving in the near future, on the other hand, the SETs being developed by the IONS4SET group using their “bottom-up self assembly process” for fabrication are achieving feature sizes of approximately 2 nm [3]. With a decrease in size there is a decrease in power consumption. SETs with feature sizes of only a few atoms take an astonishing little amount of power to function. SETs small size and low power consumption are what make them so promising, with two-thirds of the holy trinity of transistors(smaller size, lower power consumption, and lower cost), SETs are well on their way to being a favorite of manufacturers to use in their products.

While very promising, SETs do not operate with impunity. SETs are very sensitive to thermal noise, meaning in their current state they are incapable of operating at room temperature requiring a very low temperature operation of 4 to 2 kelvin. Another major obstacle in SET implementation is its incompatibility with current CMOS logic. Current CMOS technology has a voltage threshold that must be met before normal operation is possible and also require, when compared to SETs, a relatively large amount of power. Current SETs are so low power that transfer of energy beyond itself is very difficult and is too weak to interact with CMOS. In order to bridge the gap between SET and MOSFET the signal from the SET must be amplified to a level suitable for MOSFETs, which in itself is difficult, requiring “very sensitive MOSFET transistors” [4]. A way around this amplification process would be to create an all new logic based on the single electron transistor and its quantum functions, but this is still very far from being a viable option and wouldn’t help the compatibility issues already present.

Beyond the limitations of the SET itself is the issue of fabricating SETs on a large scale. The widely used lithographic and photolithographic fabrication methods are difficult to control at the resolution required to create the SETs [4]. A new fabrication method is one of the main goals of the IONS4SET project, potentially resulting in a new, reliable mass fabrication method with the precision needed, but not yet met by current methods.

There are various applications of Single Electron transistors . The primary implementation of SETs is in memory cells, as it utilizes quantum dots to store a large amount of information. Due to its incredibly small size of 2 nm, SETs allow more cells to be used in a small area thus lowering the power usage and making the circuit integration more effective . The SETs are also used as efficient charge sensors meaning it reads the charges of the qubits stored in the Quantum dot. By this process , the charge transition for both high and low conductance can be observed [5]. Due to its sensitive nature ,SETs can also detect infrared radiations; “By exciting electrons over an electrically induced energy barrier, both the range of detectable wavelengths and the sensitivity of the device can be controlled” [6]. Other applications also include SET oscillators which is useful for radio frequency systems

The future of electronics relies on the production of smaller and more efficient transistors. Engineers are working hard to discover the next great advancement in transistor design and fabrication to meet the growing demand. Single electron transistors offer one promising path leading to that advancement, but there is still a long way to go. It has to overcome difficulties in production, as well as, problems with implementation with current technology. Even still, the future is very bright for single electron transistors hopefully leading to new microscopic transistors making it possible to connect the new, vast array of future devices.

By Maisha Sadia and Beau McCarty

Sources cited
[1]R. van der Meulen, “Gartner Says 6.4 Billion Connected ‘Things’ Will Be in Use in 2016, Up 30 Percent From 2015,” “Things” Will Be in Use in 2016, Up 30 Percent From 2015, 10-Nov-2015. [Online]. Available at: http://www.gartner.com/newsroom/id/3165317. [Accessed: 23-Feb-2016].

[2]V. P. Singh, A. Agrawal, and S. B. Singh, “Analytical Discussion of Single Electron Transistor (SET),” International Journal of Soft Computing and Engineering(TM), 03-Jul-2012. [Online]. Available at: http://www.ijsce.org/. [Accessed: 23-Feb-2016].

[3]H.-Z. D.-R., “Ion-irradiation-induced Si Nanodot SelfAssembly for Hybrid SET-CMOS Technology,” Ion-irradiation-induced Si Nanodot SelfAssembly for Hybrid SET-CMOS Technology, 02-Aug-2016. [Online]. Available at: https://www.hzdr.de/db/cms?poid=45667.

[4]D. AGUIAM and O. B. R. E. C. Z. Á. N. Vince, “A Brief Introduction to Single Electron Transistors,” Tecnico Lisboa, 18-Dec-2011. [Online]. Available at: https://fenix.tecnico.ulisboa.pt/downloadfile/3779578912209/aguiam_obreczan__introset_nov2011.pdf. [Accessed: 23-Feb-2016].

[5]E. P. Nordberg, H. L. Stalford, R. Young, G. A. T. Eyck, K. Eng, L. A. Tracy, K. D. Childs, J. R. Wendt, R. K. Grubbs, J. Stevens, M. P. Lilly, M. A. Eriksson, and M. S. Carroll, “Charge sensing in enhancement mode double-top-gated metal-oxide-semiconductor quantum dots,” Appl. Phys. Lett. Applied Physics Letters, vol. 95, no. 20, p. 202102, 2009.

[6]A. Kumar and D. Dubey, “Single Electron Transistor: Applications and Limitations ,” Advance in Electronic and Electric Engineering, vol. 3, no. 1, 2013 pp. 57-62.