IHS has put out its 1Q2016 Application Market Forecast predicting the highest growth rate segments for semiconductors over the next five years – and what was once old is new yet again. There it is, in the top right corner: industrial, projected to outpace even the automotive sector. Continue reading “Moving chips from industrial to industrial IoT”
How TSMC Tackles Variation at Advanced Nodes
The design community is always hungry for high-performance, low-power, and low-cost devices. There is emergence of FinFET and FDSOI technologies at ultra-low process nodes to provide high-performance and low-power requirements at lower die-size. However, these advanced process nodes are prone to new sources of variation. Moreover, cutting-edge designs with best PPA (Power, Performance, and Area) leave very less design margins.
In such a situation with high variation and low design margin, the designers have to struggle doing more variation analysis, thus impacting design schedule. To achieve a successful design closure in time, it’s important that the variation analysis tool must be robust to provide high performance, accuracy, and coverage.
In 2015, at 52[SUP]nd[/SUP] DAC, Cypress, Applied Micro Circuits, and Microsemi had presented their successful stories about dealing with variations in their designs. They used Solido’s Variation Designer which is scalable over large number of process variables and prioritizes simulations for most-likely-to-fail cases. I had blogged about this at that time, the link is provided below; the blog also contains the links to their video presentations.
Over the year, the Variation Designer is further improved in verification speed, accuracy, and coverage for leading-edge designs with high-performance, low-power, and low-voltage. The Variation Designer platform has a very efficient variation debugging environment. This is the next generation ‘Variation Designer 4’ from Solido.
Solido will be coming up with their new developments in this year’s 53[SUP]rd[/SUP] DAC as well, but before that I wanted to highlight how TSMCand Solido are collaborating to realize variation-aware designs at advanced process nodes.
TSMC and Solido are jointly offering the following free webinar –
TSMC and Solido Collaborate for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
Abstract:
Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule. This webinar will discuss on how TSMC and Solido collaborate to offer variation-aware design techniques for memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.
Speakers– Jacob Ou, Technical Marketing Manager at TSMC (on left) andKristopher Breen,VP Customer Applications at Solido
Date: June 1, 2016
Time: 10am Pacific
Duration: 55 minutes
Click here to register!
Also read: Moving with Purpose for Certainty
Google, Deep Reasoning and Natural Language Understanding
Understanding natural language is considered a hard problem in artificial intelligence. You could be forgiven for thinking this can’t be right – surely language recognition systems already have this problem mostly solved? If so, you might be confusing recognition with understanding – loosely, recognition is the phonology (for voice) and syntax part of the problem and understanding is the semantic part.
A lot of progress has been made in recognition and this is largely thanks to deep reasoning. Voice recognition is a natural for these methods – systems can be trained to recognize a voice or a range of voices then can, thanks to probabilistic weighting, recognize a pre-determined vocabulary with high accuracy. The same applies to text recognition trained for reading selected content (stories, web-content, etc).
The quality of recognition depends on a few things – a relevant vocabulary, a sufficient grammar and a method to resolve the ambiguities which are typical in natural language. A typical English speaker has a vocabulary of ~20k words – very manageable with a large-enough neural net, though most applications today work with a much smaller task-specific vocabulary (for example in voice commands for your car). Grammars on the other hand tend to be quite simple in most applications. They throw away most of what they see and look for a likely verb and object (assuming you are the subject) to decide what you want. There are much more capable systems like IBM’s Watson, but these have required massive investment to get to better recognition.
But now there’s a big assist to building equally capable systems, and that helps with the ambiguity problem. Google recently released Syntax Net (which runs on top of Tensor Flow) as an open-source syntax engine to recognize syntax structures in a text sentence. The release also includes an English language parser called Parsey McParseface identifying the syntax tree for a sentence, including relative clauses, and tagging parts of speech like nouns, verbs (including tense and mode), pronouns and more.
While the system works with text, it is also built on deep reasoning to handle ambiguity in sentence structure. An example given in the link below considers “Alice drove down the street in her car”. Sounds pretty simple to us, but a possible machine interpretation is that she drove down a street which is inside her car. Trained neural net processing helps resolve these ambiguities.
Based on training with carefully-labelled Washington Post newswire texts, the parser is able to come very close to human accuracy in structuring sentences. It doesn’t do quite as well with unlabeled text, especially web examples, showing there is still more research required in self-guided training.
Google’s goal in this release is to encourage wider research on the deeper problems in natural language understanding, for example completing parts of speech identification (identifying that this is the subject, not just a noun or pronoun) and the semantics. Syntax Net helps other researchers and commercial developers avoid needing to reinvent a solution to a solved problem (and presumably they can now be confident that Google will be sympathetic to fair-use claims for products based on this software :cool:).
A lot of the interesting semantic challenges revolve around ambiguity and context-awareness: “Everyone loves someone” (one fortunate person is loved by everyone or possibly many people are loved?) and “John kissed his wife and so did Tom” (Tom kissed John’s wife or his own wife?). These problems might also be amenable to deep reasoning (what is the most probable interpretation) but it’s not yet as clear how you would constrain training examples for specific applications.
Natural language processing is becoming a competitive frontier as personal assistant software and translation tools become more popular and as our expectation for accuracy in dictation continue to rise (who wouldn’t love to get rid of keyboards?). This is a domain worth watching. You can read more about the Google release HERE. And HERE is a Berkeley paper on training neural nets to recognize continuous speech with a 65k word lexicon.
How Microsoft Could Become A Mobile Player
Microsoft BUILD is the company’s annual developer conference where they communicate their latest strategies and deliverables to developers and launch many new innovations. BUILD is extremely developer- focused and is intended to inform current Microsoft developers as well as recruit more developers to develop for Microsoft platforms.
Continue reading “How Microsoft Could Become A Mobile Player”
How AT&T Will Turn on Car 2 Car Connectivity
Cnet reports that, starting this week, AT&T is offering “Unlimited Plan” customers the option to add connected cars or a ZTE Mobley Wi-Fi plug-in device to their plan for $40/month for unlimited data – $10/month will buy 1GB. The plan applies to certain Buick, Audi, Chevrolet, Cadillac, GMC, Jaguar, Land Rover and Volvo vehicles equipped with AT&T telecom modules by their manufacturers.
Cnet goes on to note that AT&T stated in its first quarter earnings report that it had more than 8M cars on its network (in the U.S., more globally) and has connected more than 50% of all new connected passenger vehicles in the U.S. AT&T’s dominance of factory-fit or “embedded” connectivity in the U.S. puts the company in the unique position of being able to enable multiple connectivity options for drivers potentially integrating their smartphones, the embedded devices in their cars and/or aftermarket devices – in this case from ZTE and Audiovox.
The current offer is focused on delivering Wi-Fi for families to enable Internet access for children with mobile devices. Business use of Wi-Fi probably makes some sense as well. The Audiovox offering is skewed toward usage-based insurance and vehicle servicing.
With the new offer, AT&T is opening a window to possibilities that might boggle the minds of its car making customers and their car driving customers. Jaguar and Volvo, in particular, are interesting connected car partners for AT&T because both have been working on solutions to share data between cars. GM (Chevrolet, Cadillac, Buick, GMC) and Audi have been slow to embrace the emerging vehicle-to-vehicle communication opportunity but not these two European car makers.
In Volvo’s case, the company has been experimenting with sharing “black ice” notifications from one Volvo car to another via cloud connectivity over the embedded modem. In essence, Volvo cars will share their ABS, ESC or other sensor data when the car encounters an icy patch and notify following drivers via the LTE connection.
SOURCE: Volvo
Similarly, Jaguar is testing an application to notify following vehicles (presumably other similarly connected Jaguars) of potholes or other hazards on the road ahead. As in the Volvo case, Jaguar intends to use cloud connectivity via the LTE connection.
SOURCE: Jaguar Land Rover
What may be most attractive about these inter-vehicle communications is that they may also be shared with local traffic information authorities. But this isn’t just about road hazards, LTE connections are increasingly being used to communicate the signal phase and timing of traffic lights, variable message sign information and dynamic tolling data to enhance navigation guidance.
Given its unique role in the market, AT&T is in a privileged position to define a new path forward in vehicle connectivity combining smartphone applications with on-board data to enhance the driving experience. Mobile devices will serve as proxies for embedded connectivity where car companies are dragging their feet in embracing this new connectivity opportunity.
Notably absent from the new AT&T offer are AT&T customers Tesla, BMW, Nissan, Infiniti and Volkswagen. BMW’s absence is especially surprising given the companies embrace and advocacy of wireless cellular connectivity as an inter-vehicle and vehicle-to-infrastructure communication medium. AT&T will also soon be adding Chrysler, Mitsubishi, Ford, Porsche, Honda, Acura, and Subaru to its client roster in the U.S.
Like Vodafone in Europe, which dominates the market for embedded connections, AT&T has an unprecedented opportunity to lead the automotive industry forward in redefining vehicle connectivity to include communications between cars – including, maybe, cars from different manufacturers. It’s a tantalizing prospect and one that has not gone unnoticed by Google and Apple. (As an industry, we’re not really going to leave inter-vehicle communications to those guys, are we?)
It doesn’t hurt that AT&T has partnered with Ericsson to facilitate these cloud-based connections. The opportunities only become more fascinating as we prepare for 5G connectivity with its low latency and ability to convert every 5G-equipped vehicle into a hub. Sign me up.
Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/ac…e#.VuGdXfkrKUk
Banks and Retailers need to win in IOT
In the runtime for the current mobile ecosystem – apps:
- Average user has 21 apps on her smart phone, out of the total 1.5m apps on app-store
- While apps account for more than half the time user spends on digital/smart platform, an average user spend more than 40% of that time on a single app
- 2/3rd of all smartphone user did not download any new app last month
- 25 most-used-apps did not feature a single bank or retailer app
The mainstream Fortune500 banks and retailers have totally lost the mobile ecosystem race. The key question to their CEO and board is – want to lose the next one (IOT) too?
The story of run-time…
All computing ecosystems are defined by their run-time, or, the user interface. Sure, we should, and will, take the ‘stack’ view. It’s the overall system that provides the full range of functionality and capability to the computing ecosystem. However, form, inevitability, follows function – and nothing defines function of the computing ecosystem as their runtime environment. That is the primary ‘constrain’.
We all know the standard chronology – Mainframe ecosystem, followed by PC ecosystem, followed by Web ecosystem, followed by the current mobile ecosystem. The runtime also evolved, and it shaped the ‘applications’ and the resulting capabilities of the system. What is often hidden from this view is that the productivity benefits are also defined (or constrained) by this runtime as well.
The next runtime, for the emerging new computing ecosystem – Internet Of Things – is also coming into view. And it will be BOTs!
BOTs are coming!
Why do we need a new runtime? Why can’t the runtime of our current mobile ecosystem – based on APIs – serve us for the next computing ecosystem?
The answer to that lies in the definition of IOT – A Network Infrastructure That Enables The Interaction Among Physical And Digital Capabilities
By definition, it is impossible for us to interact with 10 or 100 connecting ‘things’ – digital and physical – by using a user-initiated runtime. The only way to effectively do so will be a combination of Augmented Reality and AI-driven ‘command line’ – i.e., a bot
Now, tech leaders are already investing billions (yes, billions) into this. Remember, Facebook bought Oculus for $2B to own the new runtime/UI. It already uses AI techniques to identify people in photos, and to decide which status updates and ads to show to each user. Facebook is also pushing into AI-powered digital assistants and chatbot programs which interact with users via messages. And last week, it is opened up its Messenger service to broaden the range of chatbots.
Google is using AI techniques to improve its internet services and guide self-driving cars, and other industry giants are also investing heavily in AI driven bots. Microsoft also recently launched its own chatbots. And despite the embarrassment it faced when its chatbot turned racist, it also (ironically) demonstrated how powerful the deep-learning algorithm behind its chatbot really was, as it accurately picked up the filth (sadly abundant) on the internet.
The point behind collating all these public news here is to drive home a central fact – the new computing platform is coming – fast – and top tech leaders are working on the new runtime. So, will the history repeat itself (as with smartphone based ecosystem)?
How should the current leaders – Banks and Fortune 500 Retailers – position themselves?
Despite seriously lagging behind the tech giants/innovators in defining the AI standards, the banks and Fortune 500 retailers have an ace up their sleeves. Its called Context.
Put simply – if Context will be the king of bots, then Data is the king maker!
And who has the best data on consumers?
This race is for the banks and retailers to lose.
Also see: Designing Low-Power IoT Systems
ARM tests out TSMC 10FinFET – with two cores
About 13 months ago, the leak blogs posted news of “Artemis” on an alleged ARM roadmap slide, supposedly a new 16FF ARM core positioned as the presumptive successor to the Cortex-A57. Now, we’re finding out what “Artemis” may actually be, inside a multi-core PPA test chip on TSMC 10FinFET. Continue reading “ARM tests out TSMC 10FinFET – with two cores”
Who protects power protection chips?
Power protection chips are widely used these days to protect sensitive circuitry from over-voltage and over-current stress. However, these workhorse chips are often subjected to extraordinary thermal stress themselves and need to be protected from burning up – literally.
Power protection chips work like electronic fuses, switching off supply lines when voltage or current passing through them becomes too high. They have several advantages over other types of fuses though. First off they can be reset automatically or at the control of external logic. Additionally, they can limit current or voltage to allow a sensitive device to continue to operate normally even if there are spikes in the supply line.
ON Semiconductor’s electronic fuses are used heavily for hot swap devices like USB ports, and SAS and SATA disk drives. Upon insertion there is usually a power surge that can damage controller circuitry. The ON Semi devices provide soft start so devices see their power supply presented in a manageable way.
Looking at the block diagram for an electronic fuse, we see that there is circuitry for over-temperature and over-current protection. Both of these need sensors to provide the raw input for each of these operations. While it is obvious that the thermal sensor needs to collect accurate thermal information, it is also the case that the current sensor, which is a replica device, needs to have to same operating conditions as the large power transistor that controls the output.
The problem with large power transistors is that there are significant temperature gradients across the surface. The temperature is determined by the joule heating and the device’s ability to dissipate that heat. However, the junction temperature in turn determines the electrical operation of the segments of the transistor. In other words, there is an interdependency between localized temperature and operating voltage and current.
As a result, the highest temperature in a power transistor can be hard to locate and predict without the right tools. The penalty for placing either sensor in the wrong location can be incorrect over-current protection, or even worse, complete and dramatic device thermal failure. The highest power dissipation occurs at the highest current and voltage operation. This is where the risk of device failure is most extreme.
On Semi has chosen to rely on the “Power Transistor Modeler – Electro-Thermal” (PTM-ET) tool from Magwel to pinpoint the hottest location within their power transistors.
PTM-ET reads in the layout and also a model for the junction device used in the power transistor. PTM-ET extracts the metal and poly structures to be able to fully model the current flow in the device. Then, user defined stimulus is applied over a time interval. PTM-ET uses advanced modeling methods to concurrently solve for transient electrical and thermal behavior. PTM-ET can also use surrounding thermal source and sink information to include an accurate view of the device including substrate, bond-wire, package and even board thermodynamics.
The end result is a 3-D visualization of the transient thermal and electrical performance of the entire device that can be graphically viewed or output in tabular report format. This can be used to determine the location and temperature of the device hotspot. With this information the designer can accurately place the over-temperature and replica devices in the optimal location.
There is a complicating twist however, once the device layout is altered to place the sense devices, the active area changes, resulting in movement of the hotspot. PTM-ET can be used again after sense device placement to ensure that they are placed as close as possible to the resultant hot spot(s).
PTM-ET is part of the suite of power transistor modeling tools from Magwel. The base product, PTM, is used to predict steady state Rdson and current density on the source/drain metal-poly network of large power devices. Also, PTM-TR can accurately predict non-uniform switching by fully modeling and simulating transient electrical behavior using the device metal-poly gate network and the active area device model.
Companies like ON Semiconductor rely on Magwel tools to solve challenging design problems so they can deliver high quality and high performance semiconductors. For more information about Magwel’s complete line of solutions for power transistor design, on-chip ESD simulation and power/ground network analysis tools, visit their website at www.magwel.com
IMEC Technology Forum (ITF) – IC Innovation
IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.
Luc Van Den Hove is the president and CEO of IMEC and he kicked off the ITF with a talk entitled “IC Innovation The Heartbeat of Yesterday, Today, Tomorrow. His talk gave a really interesting overview of the challenges and opportunities the semiconductor industry faces today.
We are now in the middle of the second decade of the century and it is a decade of disruption. Today Uber is the largest Taxi company in the world but it doesn’t own any Taxis, Facebook is the largest provider of content but it doesn’t produce any content and airbnb is the larger housing provider without owning any housing.
We are now on the eve of the Internet of Things (IoT) and IoT will disrupt everything. There will be billions of sensors providing data to tailor the environment.
In Integrated Circuit technology, scaling has historically given us, smaller, faster and cheaper with less power consumption. The trade-offs today are that scaling no longer provides all of the historical benefits. He is convinced that scaling will continue for a couple of more decades but Moore’s law will be different, it won’t just be dimensional scaling.
On the device technology front, FinFETs will transition to horizontal nanowires and then to vertical nanowires.
A cost effective lithography solution is needed and IMEC is convinced EUV is the only option, he is convinced it will succeed.
2D scaling will get harder and the time from node to node will get longer, we will need to make more use of the third dimension. For example, if you build a 3D SRAM cell once you have that building block you may be able to stack them up. SRAMs are very regular but then so are FPGAs and you can also build up standard cells.
Another opportunity is to do heterogeneous chip stacking so that each chip can be optimized for its portion of the work load. Combining Through Silicon Via (TSV) and interposers you can combine processing, memory and optical Input Output (I/O) together.
Magnetic spin based circuitry can create integration with less components than CMOS.
System innovation is also needed. To-date everything has been based on Von Neumann computing but we can evolve to Neuromorphic computing that is more like the human brain using fuzzy logic. Each neuron in the human brain is connected to 10 to 15,000 other neurons. Mimic the brains interconnection scheme using hardware. RRAM has synaptic like behavior.
Quantum computing is a long term option but he believes it is still several tens of years away. He is convinced a semiconductor platform will be needed to make it practical.
Systems and technology will need to both be co-optimized.
IC Technology will enable precision medicine. Today medicine is generic but in the future it will be tailored to the individual by genetic profiling. A DNA sequence has 6 billion characters. Targeting tumors based on DNA will allow more effective treatment but sequencing needs to be faster for it to be economical. They can sequence DNA for a few thousand dollars today. The short reads of the sequence require billions of reads that have to be reconstructed. They can now reconstruct a DNA sequence in a 2 hours instead of the 5 days it previously took. Sequencing is getting better faster than Moore’s law.
Automotive is evolving to smart connected cars for safety, inclusiveness and sustainability. To make this happen requires better sensors that are smarter and less expensive. They are integrating LIDAR onto silicon for an orders of magnitude reduction in cost. 70 GHz going to 140 GHz enable antenna on chip and better detection and identification. They are working on a full 360 degree image but it needs to combine a lot of data. This will require a lot of on-board processing power and automotive will need access to the latest technology. Cars will be the first implementation of robots in our life that will then spill over into daily service, health care and autonomous delivery.
We will need innovation in hardware and software, smarter sensors with – sensors, processing, storage and wireless communications all integrated together (computation is cheaper than bandwidth, process first to minimize transmission of data).
IoT will become the super brain of the world. We will need distributed intelligence to handle the data. Security and privacy will need to be implemented at a hardware levels and all of this will need to be tested in actual use.
In order to make this all happen all of the key players will need to work together. IMECs core is silicon technology but they are spreading out and leveraging silicon. Technology at the core needs to be surrounded by a system to deliver smart: health, mobility, cities, manufacturing, energy, media, government, etc. To this end they are merging iMind into IMEC bringing iMind’s application knowledge under the IMEC umbrella to accelerate IoT.
He believes that the chance that the next innovations will be built on semiconductor technology is pretty high just like the last fifty years. To bring about the next wave of innovation will require specific technologies optimized for the application, hardware-application and system-technology will all have to be co-optimized. IMEC is bringing together top applications partners, fabless companies, semiconductor companies and major suppliers to accomplish this. They are fully committed to develop the next wave of building blocks.
TSMC Leads Again with 3-D Packaging!
Continuing to find new ways to extend Moore’s Law, the foundry and technology leader is ready to show off its wafer level system integration prowess with two scalable platforms targeting key growth markets.
CoWoS® (Chip-On-Wafer-On-Substrate) goes after high-performance applications, providing the highest bandwidth and pin count in a large package size. CoWoS is well-suited for diverse markets including graphics, networking and high-performance computing.
InFO, on the other hand, offers an ideal fit for today’s high-volume mobile, consumer and IoT devices that require compactness, integration flexibility and cost-effectiveness. Compared to existing options, InFO delivers a 20% thinner package, 20% performance gain and a 10% improvement in power dissipation. Based on wafer molding and metal process without a substrate, InFO’s reduced thickness and optimized performance make it a superior replacement for traditional Flip Chips.
With molding and metal between the logic die and the package I/Os there is neither an interposer nor a separate package – the metal and molding compound is the package. With its 5-micron metal pitch and no substrate, InFO makes for a very slim package (less than 1mm), reducing the thickness of smartphones and wearables for example. TSMC has also introduced InFO-POP with a DRAM die connected by a new “Through-InFO-Via,” and InFO_S that integrates multiple dies and will be launched by the end of 2016.
The following picture shows a cross-sectional view of an InFO PoP technology platform, with the logic chip at the bottom and a standard, industry-available DRAM package. The technologies are integrated using TIV to produce the thinnest solution in the industry. InFO PoP enables a thinner PoP stack with better routing density, higher operating frequency (Fmax), higher memory bandwidth DRAM and better heat dissipation.
In the critical area of InFO design support, TSMC helped pioneer EDA solutions for congruent IC and package design, including packaging layout and DRC signoff, along with its Open Innovation Platform® (OIP) partners last year. This ensures that InFO designs are fully compliant with TSMC’s packaging design rules and advances the company’s plans to provide a complete InFO design flow for its customers. Through OIP, the company is expanding InFO tool support, including electrical analysis and signoff such as RLC extraction for designers to analyze the parasitic impacts from InFO and its neighboring layers. The analysis of electrical migration and IP drop are also essential to ensure design reliability for the multiple dies on InFO. In addition, TSMC and its ecosystem partners are enhancing physical implementation with inter-die connection and physical signoff with inter-die DRC and LVS solutions.
To serve its customers as high-performance computing and mobile markets accelerate their pace of innovation, TSMC plans to invest not only on the front end silicon side, but the backend technology as well. The company has completed a new facility in Longtan InFO manufacturing and will begin volume production in 2Q16.